generic_timer.c

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    1 /*-
    2  * Copyright (c) 2011 The FreeBSD Foundation
    3  * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
    4  * All rights reserved.
    5  *
    6  * Based on mpcore_timer.c developed by Ben Gray <ben.r.gray@gmail.com>
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. The name of the company nor the name of the author may be used to
   17  *    endorse or promote products derived from this software without specific
   18  *    prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  */
   32 
   33 /**
   34  *      Cortex-A15 (and probably A7) Generic Timer
   35  */
   36 
   37 #include <sys/cdefs.h>
   38 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/generic_timer.c 252780 2013-07-05 13:37:57Z ray $");
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/kernel.h>
   44 #include <sys/module.h>
   45 #include <sys/malloc.h>
   46 #include <sys/rman.h>
   47 #include <sys/timeet.h>
   48 #include <sys/timetc.h>
   49 #include <sys/watchdog.h>
   50 #include <machine/bus.h>
   51 #include <machine/cpu.h>
   52 #include <machine/frame.h>
   53 #include <machine/intr.h>
   54 
   55 #include <dev/fdt/fdt_common.h>
   56 #include <dev/ofw/openfirm.h>
   57 #include <dev/ofw/ofw_bus.h>
   58 #include <dev/ofw/ofw_bus_subr.h>
   59 
   60 #include <machine/bus.h>
   61 #include <machine/fdt.h>
   62 
   63 #define GT_CTRL_ENABLE          (1 << 0)
   64 #define GT_CTRL_INT_MASK        (1 << 1)
   65 #define GT_CTRL_INT_STAT        (1 << 2)
   66 #define GT_REG_CTRL             0
   67 #define GT_REG_TVAL             1
   68 
   69 #define GT_CNTKCTL_PL0PTEN      (1 << 9) /* PL0 Physical timer reg access */
   70 #define GT_CNTKCTL_PL0VTEN      (1 << 8) /* PL0 Virtual timer reg access */
   71 #define GT_CNTKCTL_EVNTI        (1 << 4) /* Virtual counter event bits */
   72 #define GT_CNTKCTL_EVNTDIR      (1 << 3) /* Virtual counter event transition */
   73 #define GT_CNTKCTL_EVNTEN       (1 << 2) /* Enables virtual counter events */
   74 #define GT_CNTKCTL_PL0VCTEN     (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
   75 #define GT_CNTKCTL_PL0PCTEN     (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
   76 
   77 #define GT_CNTPSIRQ     29
   78 
   79 struct arm_tmr_softc {
   80         struct resource         *irq_res;
   81         uint32_t                clkfreq;
   82         struct eventtimer       et;
   83 };
   84 
   85 static struct arm_tmr_softc *arm_tmr_sc = NULL;
   86 
   87 static timecounter_get_t arm_tmr_get_timecount;
   88 
   89 static struct timecounter arm_tmr_timecount = {
   90         .tc_name           = "ARM MPCore Timecounter",
   91         .tc_get_timecount  = arm_tmr_get_timecount,
   92         .tc_poll_pps       = NULL,
   93         .tc_counter_mask   = ~0u,
   94         .tc_frequency      = 0,
   95         .tc_quality        = 1000,
   96 };
   97 
   98 static inline int
   99 get_freq(void)
  100 {
  101         uint32_t val;
  102 
  103         __asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
  104 
  105         return (val);
  106 }
  107 
  108 static inline int
  109 set_freq(uint32_t val)
  110 {
  111 
  112         __asm volatile("mcr p15, 0, %[val], c14, c0, 0" : :
  113             [val] "r" (val));
  114         isb();
  115 
  116         return (val);
  117 }
  118 
  119 
  120 static inline long
  121 get_cntpct(void)
  122 {
  123         uint64_t val;
  124 
  125         __asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val));
  126 
  127         return (val);
  128 }
  129 
  130 static inline int
  131 set_ctrl(uint32_t val)
  132 {
  133 
  134         __asm volatile("mcr p15, 0, %[val], c14, c2, 1" : :
  135             [val] "r" (val));
  136         isb();
  137 
  138         return (0);
  139 }
  140 
  141 static inline int
  142 set_tval(uint32_t val)
  143 {
  144 
  145         __asm volatile("mcr p15, 0, %[val], c14, c2, 0" : :
  146             [val] "r" (val));
  147         isb();
  148 
  149         return (0);
  150 }
  151 
  152 static inline int
  153 get_ctrl(void)
  154 {
  155         uint32_t val;
  156 
  157         __asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
  158 
  159         return (val);
  160 }
  161 
  162 static inline int
  163 get_tval(void)
  164 {
  165         uint32_t val;
  166 
  167         __asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
  168 
  169         return (val);
  170 }
  171 
  172 static inline void
  173 disable_user_access(void)
  174 {
  175         uint32_t cntkctl;
  176 
  177         __asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
  178         cntkctl &= ~(GT_CNTKCTL_PL0PTEN | GT_CNTKCTL_PL0VTEN |
  179             GT_CNTKCTL_EVNTEN | GT_CNTKCTL_PL0VCTEN | GT_CNTKCTL_PL0PCTEN);
  180         __asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
  181         isb();
  182 }
  183 
  184 static unsigned
  185 arm_tmr_get_timecount(struct timecounter *tc)
  186 {
  187 
  188         return (get_cntpct());
  189 }
  190 
  191 static int
  192 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  193 {
  194         struct arm_tmr_softc *sc;
  195         int counts, ctrl;
  196 
  197         sc = (struct arm_tmr_softc *)et->et_priv;
  198 
  199         if (first != 0) {
  200                 counts = ((uint32_t)et->et_frequency * first) >> 32;
  201                 ctrl = get_ctrl();
  202                 ctrl &= ~GT_CTRL_INT_MASK;
  203                 ctrl |= GT_CTRL_ENABLE;
  204                 set_tval(counts);
  205                 set_ctrl(ctrl);
  206                 return (0);
  207         }
  208 
  209         return (EINVAL);
  210 
  211 }
  212 
  213 static int
  214 arm_tmr_stop(struct eventtimer *et)
  215 {
  216         int ctrl;
  217 
  218         ctrl = get_ctrl();
  219         ctrl &= GT_CTRL_ENABLE;
  220         set_ctrl(ctrl);
  221 
  222         return (0);
  223 }
  224 
  225 static int
  226 arm_tmr_intr(void *arg)
  227 {
  228         struct arm_tmr_softc *sc;
  229         int ctrl;
  230 
  231         sc = (struct arm_tmr_softc *)arg;
  232         ctrl = get_ctrl();
  233         if (ctrl & GT_CTRL_INT_STAT) {
  234                 ctrl |= GT_CTRL_INT_MASK;
  235                 set_ctrl(ctrl);
  236         }
  237 
  238         if (sc->et.et_active)
  239                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  240 
  241         return (FILTER_HANDLED);
  242 }
  243 
  244 static int
  245 arm_tmr_probe(device_t dev)
  246 {
  247 
  248         if (!ofw_bus_is_compatible(dev, "arm,armv7-timer"))
  249                 return (ENXIO);
  250 
  251         device_set_desc(dev, "ARMv7 Generic Timer");
  252         return (BUS_PROBE_DEFAULT);
  253 }
  254 
  255 
  256 static int
  257 arm_tmr_attach(device_t dev)
  258 {
  259         struct arm_tmr_softc *sc;
  260         phandle_t node;
  261         pcell_t clock;
  262         void *ihl;
  263         int rid;
  264         int error;
  265 
  266         sc = device_get_softc(dev);
  267         if (arm_tmr_sc)
  268                 return (ENXIO);
  269 
  270         /* Get the base clock frequency */
  271         node = ofw_bus_get_node(dev);
  272         error = OF_getprop(node, "clock-frequency", &clock, sizeof(clock));
  273         if (error <= 0) {
  274                 device_printf(dev, "missing clock-frequency "
  275                     "attribute in FDT\n");
  276                 return (ENXIO);
  277         }
  278         sc->clkfreq = fdt32_to_cpu(clock);
  279 
  280         rid = 0;
  281         sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
  282             GT_CNTPSIRQ, GT_CNTPSIRQ,
  283             1, RF_SHAREABLE | RF_ACTIVE);
  284 
  285         arm_tmr_sc = sc;
  286 
  287         /* Setup and enable the timer */
  288         if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK, arm_tmr_intr,
  289                 NULL, sc, &ihl) != 0) {
  290                 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->irq_res);
  291                 device_printf(dev, "Unable to setup the CLK irq handler.\n");
  292                 return (ENXIO);
  293         }
  294 
  295         set_freq(sc->clkfreq);
  296         disable_user_access();
  297 
  298         arm_tmr_timecount.tc_frequency = sc->clkfreq;
  299         tc_init(&arm_tmr_timecount);
  300 
  301         sc->et.et_name = "ARM MPCore Eventtimer";
  302         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
  303         sc->et.et_quality = 1000;
  304 
  305         sc->et.et_frequency = sc->clkfreq;
  306         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  307         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  308         sc->et.et_start = arm_tmr_start;
  309         sc->et.et_stop = arm_tmr_stop;
  310         sc->et.et_priv = sc;
  311         et_register(&sc->et);
  312 
  313         return (0);
  314 }
  315 
  316 static device_method_t arm_tmr_methods[] = {
  317         DEVMETHOD(device_probe,         arm_tmr_probe),
  318         DEVMETHOD(device_attach,        arm_tmr_attach),
  319         { 0, 0 }
  320 };
  321 
  322 static driver_t arm_tmr_driver = {
  323         "generic_timer",
  324         arm_tmr_methods,
  325         sizeof(struct arm_tmr_softc),
  326 };
  327 
  328 static devclass_t arm_tmr_devclass;
  329 
  330 DRIVER_MODULE(timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
  331 
  332 void
  333 cpu_initclocks(void)
  334 {
  335 
  336         if (PCPU_GET(cpuid) == 0)
  337                 cpu_initclocks_bsp();
  338         else
  339                 cpu_initclocks_ap();
  340 }
  341 
  342 void
  343 DELAY(int usec)
  344 {
  345         int32_t counts, counts_per_usec;
  346         uint32_t first, last;
  347 
  348         /*
  349          * Check the timers are setup, if not just
  350          * use a for loop for the meantime
  351          */
  352         if (arm_tmr_sc == NULL) {
  353                 for (; usec > 0; usec--)
  354                         for (counts = 200; counts > 0; counts--)
  355                                 /*
  356                                  * Prevent gcc from optimizing
  357                                  * out the loop
  358                                  */
  359                                 cpufunc_nullop();
  360                 return;
  361         }
  362 
  363         /* Get the number of times to count */
  364         counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
  365 
  366         /*
  367          * Clamp the timeout at a maximum value (about 32 seconds with
  368          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
  369          * near that length of time and if they are, they should be hung
  370          * out to dry.
  371          */
  372         if (usec >= (0x80000000U / counts_per_usec))
  373                 counts = (0x80000000U / counts_per_usec) - 1;
  374         else
  375                 counts = usec * counts_per_usec;
  376 
  377         first = get_cntpct();
  378 
  379         while (counts > 0) {
  380                 last = get_cntpct();
  381                 counts -= (int32_t)(last - first);
  382                 first = last;
  383         }
  384 }
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FreeBSD/Linux Kernel Cross Reference sys/arm/arm/generic_timer.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/generic_timer.c
