FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/gic.c
1 /*-
2 * Copyright (c) 2011 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * Developed by Damjan Marion <damjan.marion@gmail.com>
6 *
7 * Based on OMAP4 GIC code by Ben Gray
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/ktr.h>
42 #include <sys/module.h>
43 #include <sys/rman.h>
44 #include <sys/pcpu.h>
45 #include <sys/proc.h>
46 #include <sys/cpuset.h>
47 #include <sys/lock.h>
48 #include <sys/mutex.h>
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51 #include <machine/smp.h>
52
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/ofw/openfirm.h>
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57
58 /* We are using GICv2 register naming */
59
60 /* Distributor Registers */
61 #define GICD_CTLR 0x000 /* v1 ICDDCR */
62 #define GICD_TYPER 0x004 /* v1 ICDICTR */
63 #define GICD_IIDR 0x008 /* v1 ICDIIDR */
64 #define GICD_IGROUPR(n) (0x0080 + ((n) * 4)) /* v1 ICDISER */
65 #define GICD_ISENABLER(n) (0x0100 + ((n) * 4)) /* v1 ICDISER */
66 #define GICD_ICENABLER(n) (0x0180 + ((n) * 4)) /* v1 ICDICER */
67 #define GICD_ISPENDR(n) (0x0200 + ((n) * 4)) /* v1 ICDISPR */
68 #define GICD_ICPENDR(n) (0x0280 + ((n) * 4)) /* v1 ICDICPR */
69 #define GICD_ICACTIVER(n) (0x0380 + ((n) * 4)) /* v1 ICDABR */
70 #define GICD_IPRIORITYR(n) (0x0400 + ((n) * 4)) /* v1 ICDIPR */
71 #define GICD_ITARGETSR(n) (0x0800 + ((n) * 4)) /* v1 ICDIPTR */
72 #define GICD_ICFGR(n) (0x0C00 + ((n) * 4)) /* v1 ICDICFR */
73 #define GICD_SGIR(n) (0x0F00 + ((n) * 4)) /* v1 ICDSGIR */
74
75 /* CPU Registers */
76 #define GICC_CTLR 0x0000 /* v1 ICCICR */
77 #define GICC_PMR 0x0004 /* v1 ICCPMR */
78 #define GICC_BPR 0x0008 /* v1 ICCBPR */
79 #define GICC_IAR 0x000C /* v1 ICCIAR */
80 #define GICC_EOIR 0x0010 /* v1 ICCEOIR */
81 #define GICC_RPR 0x0014 /* v1 ICCRPR */
82 #define GICC_HPPIR 0x0018 /* v1 ICCHPIR */
83 #define GICC_ABPR 0x001C /* v1 ICCABPR */
84 #define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
85
86 #define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */
87 #define GIC_LAST_IPI 15
88 #define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
89 #define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
90 #define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
91
92 /* First bit is a polarity bit (0 - low, 1 - high) */
93 #define GICD_ICFGR_POL_LOW (0 << 0)
94 #define GICD_ICFGR_POL_HIGH (1 << 0)
95 #define GICD_ICFGR_POL_MASK 0x1
96 /* Second bit is a trigger bit (0 - level, 1 - edge) */
97 #define GICD_ICFGR_TRIG_LVL (0 << 1)
98 #define GICD_ICFGR_TRIG_EDGE (1 << 1)
99 #define GICD_ICFGR_TRIG_MASK 0x2
100
101 struct arm_gic_softc {
102 struct resource * gic_res[3];
103 bus_space_tag_t gic_c_bst;
104 bus_space_tag_t gic_d_bst;
105 bus_space_handle_t gic_c_bsh;
106 bus_space_handle_t gic_d_bsh;
107 uint8_t ver;
108 device_t dev;
109 struct mtx mutex;
110 uint32_t nirqs;
111 };
112
113 static struct resource_spec arm_gic_spec[] = {
114 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
115 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
116 { -1, 0 }
117 };
118
119 static struct arm_gic_softc *arm_gic_sc = NULL;
120
121 #define gic_c_read_4(reg) \
122 bus_space_read_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg)
123 #define gic_c_write_4(reg, val) \
124 bus_space_write_4(arm_gic_sc->gic_c_bst, arm_gic_sc->gic_c_bsh, reg, val)
125 #define gic_d_read_4(reg) \
126 bus_space_read_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg)
127 #define gic_d_write_4(reg, val) \
128 bus_space_write_4(arm_gic_sc->gic_d_bst, arm_gic_sc->gic_d_bsh, reg, val)
129
130 static int gic_config_irq(int irq, enum intr_trigger trig,
131 enum intr_polarity pol);
132 static void gic_post_filter(void *);
133
134 static struct ofw_compat_data compat_data[] = {
135 {"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */
136 {"arm,gic-400", true},
137 {"arm,cortex-a15-gic", true},
138 {"arm,cortex-a9-gic", true},
139 {"arm,cortex-a7-gic", true},
140 {"arm,arm11mp-gic", true},
141 {"brcm,brahma-b15-gic", true},
142 {NULL, false}
143 };
144
145 static int
146 arm_gic_probe(device_t dev)
147 {
148
149 if (!ofw_bus_status_okay(dev))
150 return (ENXIO);
151
152 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
153 return (ENXIO);
154 device_set_desc(dev, "ARM Generic Interrupt Controller");
155 return (BUS_PROBE_DEFAULT);
156 }
157
158 void
159 gic_init_secondary(void)
160 {
161 int i, nirqs;
162
163 /* Get the number of interrupts */
164 nirqs = gic_d_read_4(GICD_TYPER);
165 nirqs = 32 * ((nirqs & 0x1f) + 1);
166
167 for (i = 0; i < nirqs; i += 4)
168 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
169
170 /* Set all the interrupts to be in Group 0 (secure) */
171 for (i = 0; i < nirqs; i += 32) {
172 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
173 }
174
175 /* Enable CPU interface */
176 gic_c_write_4(GICC_CTLR, 1);
177
178 /* Set priority mask register. */
179 gic_c_write_4(GICC_PMR, 0xff);
180
181 /* Enable interrupt distribution */
182 gic_d_write_4(GICD_CTLR, 0x01);
183
184 /* Activate IRQ 29, ie private timer IRQ*/
185 gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
186 }
187
188 int
189 gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
190 int *trig, int *pol)
191 {
192 static u_int num_intr_cells;
193
194 if (num_intr_cells == 0) {
195 if (OF_searchencprop(OF_node_from_xref(iparent),
196 "#interrupt-cells", &num_intr_cells,
197 sizeof(num_intr_cells)) == -1) {
198 num_intr_cells = 1;
199 }
200 }
201
202 if (num_intr_cells == 1) {
203 *interrupt = fdt32_to_cpu(intr[0]);
204 *trig = INTR_TRIGGER_CONFORM;
205 *pol = INTR_POLARITY_CONFORM;
206 } else {
207 if (fdt32_to_cpu(intr[0]) == 0)
208 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_SPI;
209 else
210 *interrupt = fdt32_to_cpu(intr[1]) + GIC_FIRST_PPI;
211 /*
212 * In intr[2], bits[3:0] are trigger type and level flags.
213 * 1 = low-to-high edge triggered
214 * 2 = high-to-low edge triggered
215 * 4 = active high level-sensitive
216 * 8 = active low level-sensitive
217 * The hardware only supports active-high-level or rising-edge.
218 */
219 if (fdt32_to_cpu(intr[2]) & 0x0a) {
220 printf("unsupported trigger/polarity configuration "
221 "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f);
222 return (ENOTSUP);
223 }
224 *pol = INTR_POLARITY_CONFORM;
225 if (fdt32_to_cpu(intr[2]) & 0x01)
226 *trig = INTR_TRIGGER_EDGE;
227 else
228 *trig = INTR_TRIGGER_LEVEL;
229 }
230 return (0);
231 }
232
233 static int
234 arm_gic_attach(device_t dev)
235 {
236 struct arm_gic_softc *sc;
237 int i;
238 uint32_t icciidr;
239
240 if (arm_gic_sc)
241 return (ENXIO);
242
243 sc = device_get_softc(dev);
244 sc->dev = dev;
245
246 if (bus_alloc_resources(dev, arm_gic_spec, sc->gic_res)) {
247 device_printf(dev, "could not allocate resources\n");
248 return (ENXIO);
249 }
250
251 /* Initialize mutex */
252 mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
253
254 /* Distributor Interface */
255 sc->gic_d_bst = rman_get_bustag(sc->gic_res[0]);
256 sc->gic_d_bsh = rman_get_bushandle(sc->gic_res[0]);
257
258 /* CPU Interface */
259 sc->gic_c_bst = rman_get_bustag(sc->gic_res[1]);
260 sc->gic_c_bsh = rman_get_bushandle(sc->gic_res[1]);
261
262 arm_gic_sc = sc;
263
264 /* Disable interrupt forwarding to the CPU interface */
265 gic_d_write_4(GICD_CTLR, 0x00);
266
267 /* Get the number of interrupts */
268 sc->nirqs = gic_d_read_4(GICD_TYPER);
269 sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
270
271 /* Set up function pointers */
272 arm_post_filter = gic_post_filter;
273 arm_config_irq = gic_config_irq;
274
275 icciidr = gic_c_read_4(GICC_IIDR);
276 device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
277 icciidr>>20, (icciidr>>16) & 0xF, (icciidr>>12) & 0xf,
278 (icciidr & 0xfff), sc->nirqs);
279
280 /* Set all global interrupts to be level triggered, active low. */
281 for (i = 32; i < sc->nirqs; i += 16) {
282 gic_d_write_4(GICD_ICFGR(i >> 4), 0x00000000);
283 }
284
285 /* Disable all interrupts. */
286 for (i = 32; i < sc->nirqs; i += 32) {
287 gic_d_write_4(GICD_ICENABLER(i >> 5), 0xFFFFFFFF);
288 }
289
290 for (i = 0; i < sc->nirqs; i += 4) {
291 gic_d_write_4(GICD_IPRIORITYR(i >> 2), 0);
292 gic_d_write_4(GICD_ITARGETSR(i >> 2), 1 << 0 | 1 << 8 | 1 << 16 | 1 << 24);
293 }
294
295 /* Set all the interrupts to be in Group 0 (secure) */
296 for (i = 0; i < sc->nirqs; i += 32) {
297 gic_d_write_4(GICD_IGROUPR(i >> 5), 0);
298 }
299
300 /* Enable CPU interface */
301 gic_c_write_4(GICC_CTLR, 1);
302
303 /* Set priority mask register. */
304 gic_c_write_4(GICC_PMR, 0xff);
305
306 /* Enable interrupt distribution */
307 gic_d_write_4(GICD_CTLR, 0x01);
308
309 return (0);
310 }
311
312 static device_method_t arm_gic_methods[] = {
313 DEVMETHOD(device_probe, arm_gic_probe),
314 DEVMETHOD(device_attach, arm_gic_attach),
315 { 0, 0 }
316 };
317
318 static driver_t arm_gic_driver = {
319 "gic",
320 arm_gic_methods,
321 sizeof(struct arm_gic_softc),
322 };
323
324 static devclass_t arm_gic_devclass;
325
326 EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0,
327 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
328 EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0,
329 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
330
331 static void
332 gic_post_filter(void *arg)
333 {
334 uintptr_t irq = (uintptr_t) arg;
335
336 if (irq > GIC_LAST_IPI)
337 arm_irq_memory_barrier(irq);
338 gic_c_write_4(GICC_EOIR, irq);
339 }
340
341 int
342 arm_get_next_irq(int last_irq)
343 {
344 uint32_t active_irq;
345
346 active_irq = gic_c_read_4(GICC_IAR);
347
348 /*
349 * Immediatly EOIR the SGIs, because doing so requires the other
350 * bits (ie CPU number), not just the IRQ number, and we do not
351 * have this information later.
352 */
353
354 if ((active_irq & 0x3ff) <= GIC_LAST_IPI)
355 gic_c_write_4(GICC_EOIR, active_irq);
356 active_irq &= 0x3FF;
357
358 if (active_irq == 0x3FF) {
359 if (last_irq == -1)
360 printf("Spurious interrupt detected\n");
361 return -1;
362 }
363
364 return active_irq;
365 }
366
367 void
368 arm_mask_irq(uintptr_t nb)
369 {
370
371 gic_d_write_4(GICD_ICENABLER(nb >> 5), (1UL << (nb & 0x1F)));
372 gic_c_write_4(GICC_EOIR, nb);
373 }
374
375 void
376 arm_unmask_irq(uintptr_t nb)
377 {
378
379 if (nb > GIC_LAST_IPI)
380 arm_irq_memory_barrier(nb);
381 gic_d_write_4(GICD_ISENABLER(nb >> 5), (1UL << (nb & 0x1F)));
382 }
383
384 static int
385 gic_config_irq(int irq, enum intr_trigger trig,
386 enum intr_polarity pol)
387 {
388 uint32_t reg;
389 uint32_t mask;
390
391 /* Function is public-accessible, so validate input arguments */
392 if ((irq < 0) || (irq >= arm_gic_sc->nirqs))
393 goto invalid_args;
394 if ((trig != INTR_TRIGGER_EDGE) && (trig != INTR_TRIGGER_LEVEL) &&
395 (trig != INTR_TRIGGER_CONFORM))
396 goto invalid_args;
397 if ((pol != INTR_POLARITY_HIGH) && (pol != INTR_POLARITY_LOW) &&
398 (pol != INTR_POLARITY_CONFORM))
399 goto invalid_args;
400
401 mtx_lock_spin(&arm_gic_sc->mutex);
402
403 reg = gic_d_read_4(GICD_ICFGR(irq >> 4));
404 mask = (reg >> 2*(irq % 16)) & 0x3;
405
406 if (pol == INTR_POLARITY_LOW) {
407 mask &= ~GICD_ICFGR_POL_MASK;
408 mask |= GICD_ICFGR_POL_LOW;
409 } else if (pol == INTR_POLARITY_HIGH) {
410 mask &= ~GICD_ICFGR_POL_MASK;
411 mask |= GICD_ICFGR_POL_HIGH;
412 }
413
414 if (trig == INTR_TRIGGER_LEVEL) {
415 mask &= ~GICD_ICFGR_TRIG_MASK;
416 mask |= GICD_ICFGR_TRIG_LVL;
417 } else if (trig == INTR_TRIGGER_EDGE) {
418 mask &= ~GICD_ICFGR_TRIG_MASK;
419 mask |= GICD_ICFGR_TRIG_EDGE;
420 }
421
422 /* Set mask */
423 reg = reg & ~(0x3 << 2*(irq % 16));
424 reg = reg | (mask << 2*(irq % 16));
425 gic_d_write_4(GICD_ICFGR(irq >> 4), reg);
426
427 mtx_unlock_spin(&arm_gic_sc->mutex);
428
429 return (0);
430
431 invalid_args:
432 device_printf(arm_gic_sc->dev, "gic_config_irg, invalid parameters\n");
433 return (EINVAL);
434 }
435
436 #ifdef SMP
437 void
438 pic_ipi_send(cpuset_t cpus, u_int ipi)
439 {
440 uint32_t val = 0, i;
441
442 for (i = 0; i < MAXCPU; i++)
443 if (CPU_ISSET(i, &cpus))
444 val |= 1 << (16 + i);
445 gic_d_write_4(GICD_SGIR(0), val | ipi);
446
447 }
448
449 int
450 pic_ipi_get(int i)
451 {
452
453 if (i != -1) {
454 /*
455 * The intr code will automagically give the frame pointer
456 * if the interrupt argument is 0.
457 */
458 if ((unsigned int)i > 16)
459 return (0);
460 return (i);
461 }
462 return (0x3ff);
463 }
464
465 void
466 pic_ipi_clear(int ipi)
467 {
468 }
469 #endif
470
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