Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/identcpu.c
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1 /* $NetBSD: cpu.c,v 1.55 2004/02/13 11:36:10 wiz Exp $ */ 2 3 /*- 4 * Copyright (c) 1995 Mark Brinicombe. 5 * Copyright (c) 1995 Brini. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpu.c 38 * 39 * Probing and configuration for the master CPU 40 * 41 * Created : 10/10/95 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD: releng/9.0/sys/arm/arm/identcpu.c 207954 2010-05-12 05:50:56Z kevlo $"); 46 #include <sys/systm.h> 47 #include <sys/param.h> 48 #include <sys/malloc.h> 49 #include <sys/time.h> 50 #include <sys/proc.h> 51 #include <sys/conf.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <machine/cpu.h> 55 56 #include <machine/cpuconf.h> 57 #include <machine/md_var.h> 58 59 char machine[] = "arm"; 60 61 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 62 machine, 0, "Machine class"); 63 64 static const char * const generic_steppings[16] = { 65 "rev 0", "rev 1", "rev 2", "rev 3", 66 "rev 4", "rev 5", "rev 6", "rev 7", 67 "rev 8", "rev 9", "rev 10", "rev 11", 68 "rev 12", "rev 13", "rev 14", "rev 15", 69 }; 70 71 static const char * const sa110_steppings[16] = { 72 "rev 0", "step J", "step K", "step S", 73 "step T", "rev 5", "rev 6", "rev 7", 74 "rev 8", "rev 9", "rev 10", "rev 11", 75 "rev 12", "rev 13", "rev 14", "rev 15", 76 }; 77 78 static const char * const sa1100_steppings[16] = { 79 "rev 0", "step B", "step C", "rev 3", 80 "rev 4", "rev 5", "rev 6", "rev 7", 81 "step D", "step E", "rev 10" "step G", 82 "rev 12", "rev 13", "rev 14", "rev 15", 83 }; 84 85 static const char * const sa1110_steppings[16] = { 86 "step A-0", "rev 1", "rev 2", "rev 3", 87 "step B-0", "step B-1", "step B-2", "step B-3", 88 "step B-4", "step B-5", "rev 10", "rev 11", 89 "rev 12", "rev 13", "rev 14", "rev 15", 90 }; 91 92 static const char * const ixp12x0_steppings[16] = { 93 "(IXP1200 step A)", "(IXP1200 step B)", 94 "rev 2", "(IXP1200 step C)", 95 "(IXP1200 step D)", "(IXP1240/1250 step A)", 96 "(IXP1240 step B)", "(IXP1250 step B)", 97 "rev 8", "rev 9", "rev 10", "rev 11", 98 "rev 12", "rev 13", "rev 14", "rev 15", 99 }; 100 101 static const char * const xscale_steppings[16] = { 102 "step A-0", "step A-1", "step B-0", "step C-0", 103 "step D-0", "rev 5", "rev 6", "rev 7", 104 "rev 8", "rev 9", "rev 10", "rev 11", 105 "rev 12", "rev 13", "rev 14", "rev 15", 106 }; 107 108 static const char * const i80219_steppings[16] = { 109 "step A-0", "rev 1", "rev 2", "rev 3", 110 "rev 4", "rev 5", "rev 6", "rev 7", 111 "rev 8", "rev 9", "rev 10", "rev 11", 112 "rev 12", "rev 13", "rev 14", "rev 15", 113 }; 114 115 static const char * const i80321_steppings[16] = { 116 "step A-0", "step B-0", "rev 2", "rev 3", 117 "rev 4", "rev 5", "rev 6", "rev 7", 118 "rev 8", "rev 9", "rev 10", "rev 11", 119 "rev 12", "rev 13", "rev 14", "rev 15", 120 }; 121 122 static const char * const i81342_steppings[16] = { 123 "step A-0", "rev 1", "rev 2", "rev 3", 124 "rev 4", "rev 5", "rev 6", "rev 7", 125 "rev 8", "rev 9", "rev 10", "rev 11", 126 "rev 12", "rev 13", "rev 14", "rev 15", 127 }; 128 129 /* Steppings for PXA2[15]0 */ 130 static const char * const pxa2x0_steppings[16] = { 131 "step A-0", "step A-1", "step B-0", "step B-1", 132 "step B-2", "step C-0", "rev 6", "rev 7", 133 "rev 8", "rev 9", "rev 10", "rev 11", 134 "rev 12", "rev 13", "rev 14", "rev 15", 135 }; 136 137 /* Steppings for PXA255/26x. 138 * rev 5: PXA26x B0, rev 6: PXA255 A0 139 */ 140 static const char * const pxa255_steppings[16] = { 141 "rev 0", "rev 1", "rev 2", "step A-0", 142 "rev 4", "step B-0", "step A-0", "rev 7", 143 "rev 8", "rev 9", "rev 10", "rev 11", 144 "rev 12", "rev 13", "rev 14", "rev 15", 145 }; 146 147 /* Stepping for PXA27x */ 148 static const char * const pxa27x_steppings[16] = { 149 "step A-0", "step A-1", "step B-0", "step B-1", 150 "step C-0", "rev 5", "rev 6", "rev 7", 151 "rev 8", "rev 9", "rev 10", "rev 11", 152 "rev 12", "rev 13", "rev 14", "rev 15", 153 }; 154 155 static const char * const ixp425_steppings[16] = { 156 "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", 157 "rev 4", "rev 5", "rev 6", "rev 7", 158 "rev 8", "rev 9", "rev 10", "rev 11", 159 "rev 12", "rev 13", "rev 14", "rev 15", 160 }; 161 162 struct cpuidtab { 163 u_int32_t cpuid; 164 enum cpu_class cpu_class; 165 const char *cpu_name; 166 const char * const *cpu_steppings; 167 }; 168 169 const struct cpuidtab cpuids[] = { 170 { CPU_ID_ARM2, CPU_CLASS_ARM2, "ARM2", 171 generic_steppings }, 172 { CPU_ID_ARM250, CPU_CLASS_ARM2AS, "ARM250", 173 generic_steppings }, 174 175 { CPU_ID_ARM3, CPU_CLASS_ARM3, "ARM3", 176 generic_steppings }, 177 178 { CPU_ID_ARM600, CPU_CLASS_ARM6, "ARM600", 179 generic_steppings }, 180 { CPU_ID_ARM610, CPU_CLASS_ARM6, "ARM610", 181 generic_steppings }, 182 { CPU_ID_ARM620, CPU_CLASS_ARM6, "ARM620", 183 generic_steppings }, 184 185 { CPU_ID_ARM700, CPU_CLASS_ARM7, "ARM700", 186 generic_steppings }, 187 { CPU_ID_ARM710, CPU_CLASS_ARM7, "ARM710", 188 generic_steppings }, 189 { CPU_ID_ARM7500, CPU_CLASS_ARM7, "ARM7500", 190 generic_steppings }, 191 { CPU_ID_ARM710A, CPU_CLASS_ARM7, "ARM710a", 192 generic_steppings }, 193 { CPU_ID_ARM7500FE, CPU_CLASS_ARM7, "ARM7500FE", 194 generic_steppings }, 195 { CPU_ID_ARM710T, CPU_CLASS_ARM7TDMI, "ARM710T", 196 generic_steppings }, 197 { CPU_ID_ARM720T, CPU_CLASS_ARM7TDMI, "ARM720T", 198 generic_steppings }, 199 { CPU_ID_ARM740T8K, CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)", 200 generic_steppings }, 201 { CPU_ID_ARM740T4K, CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)", 202 generic_steppings }, 203 204 { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810", 205 generic_steppings }, 206 207 { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T", 208 generic_steppings }, 209 { CPU_ID_ARM920T_ALT, CPU_CLASS_ARM9TDMI, "ARM920T", 210 generic_steppings }, 211 { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", 212 generic_steppings }, 213 { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", 214 generic_steppings }, 215 { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", 216 generic_steppings }, 217 { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", 218 generic_steppings }, 219 { CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S", 220 generic_steppings }, 221 { CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S", 222 generic_steppings }, 223 { CPU_ID_FA526, CPU_CLASS_ARM9TDMI, "FA526", 224 generic_steppings }, 225 { CPU_ID_FA626TE, CPU_CLASS_ARM9ES, "FA626TE", 226 generic_steppings }, 227 228 { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T", 229 generic_steppings }, 230 231 { CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E", 232 generic_steppings }, 233 { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", 234 generic_steppings }, 235 { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", 236 generic_steppings }, 237 238 { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", 239 sa110_steppings }, 240 { CPU_ID_SA1100, CPU_CLASS_SA1, "SA-1100", 241 sa1100_steppings }, 242 { CPU_ID_SA1110, CPU_CLASS_SA1, "SA-1110", 243 sa1110_steppings }, 244 245 { CPU_ID_IXP1200, CPU_CLASS_SA1, "IXP1200", 246 ixp12x0_steppings }, 247 248 { CPU_ID_80200, CPU_CLASS_XSCALE, "i80200", 249 xscale_steppings }, 250 251 { CPU_ID_80321_400, CPU_CLASS_XSCALE, "i80321 400MHz", 252 i80321_steppings }, 253 { CPU_ID_80321_600, CPU_CLASS_XSCALE, "i80321 600MHz", 254 i80321_steppings }, 255 { CPU_ID_80321_400_B0, CPU_CLASS_XSCALE, "i80321 400MHz", 256 i80321_steppings }, 257 { CPU_ID_80321_600_B0, CPU_CLASS_XSCALE, "i80321 600MHz", 258 i80321_steppings }, 259 260 { CPU_ID_81342, CPU_CLASS_XSCALE, "i81342", 261 i81342_steppings }, 262 263 { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", 264 i80219_steppings }, 265 { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", 266 i80219_steppings }, 267 268 { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", 269 pxa27x_steppings }, 270 { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", 271 pxa2x0_steppings }, 272 { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", 273 pxa2x0_steppings }, 274 { CPU_ID_PXA250B, CPU_CLASS_XSCALE, "PXA250", 275 pxa2x0_steppings }, 276 { CPU_ID_PXA210B, CPU_CLASS_XSCALE, "PXA210", 277 pxa2x0_steppings }, 278 { CPU_ID_PXA250C, CPU_CLASS_XSCALE, "PXA255", 279 pxa255_steppings }, 280 { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", 281 pxa2x0_steppings }, 282 283 { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", 284 ixp425_steppings }, 285 { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", 286 ixp425_steppings }, 287 { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", 288 ixp425_steppings }, 289 290 /* XXX ixp435 steppings? */ 291 { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", 292 ixp425_steppings }, 293 294 { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", 295 generic_steppings }, 296 { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", 297 generic_steppings }, 298 299 { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", 300 generic_steppings }, 301 302 { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", 303 generic_steppings }, 304 305 { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571", 306 generic_steppings }, 307 308 { 0, CPU_CLASS_NONE, NULL, NULL } 309 }; 310 311 struct cpu_classtab { 312 const char *class_name; 313 const char *class_option; 314 }; 315 316 const struct cpu_classtab cpu_classes[] = { 317 { "unknown", NULL }, /* CPU_CLASS_NONE */ 318 { "ARM2", "CPU_ARM2" }, /* CPU_CLASS_ARM2 */ 319 { "ARM2as", "CPU_ARM250" }, /* CPU_CLASS_ARM2AS */ 320 { "ARM3", "CPU_ARM3" }, /* CPU_CLASS_ARM3 */ 321 { "ARM6", "CPU_ARM6" }, /* CPU_CLASS_ARM6 */ 322 { "ARM7", "CPU_ARM7" }, /* CPU_CLASS_ARM7 */ 323 { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ 324 { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ 325 { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ 326 { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ 327 { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ 328 { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ 329 { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ 330 { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ 331 { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ 332 { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ 333 { "Marvell", "CPU_MARVELL" }, /* CPU_CLASS_MARVELL */ 334 }; 335 336 /* 337 * Report the type of the specified arm processor. This uses the generic and 338 * arm specific information in the cpu structure to identify the processor. 339 * The remaining fields in the cpu structure are filled in appropriately. 340 */ 341 342 static const char * const wtnames[] = { 343 "write-through", 344 "write-back", 345 "write-back", 346 "**unknown 3**", 347 "**unknown 4**", 348 "write-back-locking", /* XXX XScale-specific? */ 349 "write-back-locking-A", 350 "write-back-locking-B", 351 "**unknown 8**", 352 "**unknown 9**", 353 "**unknown 10**", 354 "**unknown 11**", 355 "**unknown 12**", 356 "**unknown 13**", 357 "write-back-locking-C", 358 "**unknown 15**", 359 }; 360 361 362 extern int ctrl; 363 enum cpu_class cpu_class = CPU_CLASS_NONE; 364 void 365 identify_arm_cpu(void) 366 { 367 u_int cpuid; 368 int i; 369 370 cpuid = cpu_id(); 371 372 if (cpuid == 0) { 373 printf("Processor failed probe - no CPU ID\n"); 374 return; 375 } 376 377 for (i = 0; cpuids[i].cpuid != 0; i++) 378 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) { 379 cpu_class = cpuids[i].cpu_class; 380 printf("CPU: %s %s (%s core)\n", 381 cpuids[i].cpu_name, 382 cpuids[i].cpu_steppings[cpuid & 383 CPU_ID_REVISION_MASK], 384 cpu_classes[cpu_class].class_name); 385 break; 386 } 387 if (cpuids[i].cpuid == 0) 388 printf("unknown CPU (ID = 0x%x)\n", cpuid); 389 390 printf(" "); 391 switch (cpu_class) { 392 case CPU_CLASS_ARM6: 393 case CPU_CLASS_ARM7: 394 case CPU_CLASS_ARM7TDMI: 395 case CPU_CLASS_ARM8: 396 if ((ctrl & CPU_CONTROL_IDC_ENABLE) == 0) 397 printf(" IDC disabled"); 398 else 399 printf(" IDC enabled"); 400 break; 401 case CPU_CLASS_ARM9TDMI: 402 case CPU_CLASS_ARM9ES: 403 case CPU_CLASS_ARM9EJS: 404 case CPU_CLASS_ARM10E: 405 case CPU_CLASS_ARM10EJ: 406 case CPU_CLASS_SA1: 407 case CPU_CLASS_XSCALE: 408 case CPU_CLASS_ARM11J: 409 case CPU_CLASS_MARVELL: 410 if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0) 411 printf(" DC disabled"); 412 else 413 printf(" DC enabled"); 414 if ((ctrl & CPU_CONTROL_IC_ENABLE) == 0) 415 printf(" IC disabled"); 416 else 417 printf(" IC enabled"); 418 #ifdef CPU_XSCALE_81342 419 if ((ctrl & CPU_CONTROL_L2_ENABLE) == 0) 420 printf(" L2 disabled"); 421 else 422 printf(" L2 enabled"); 423 #endif 424 break; 425 default: 426 break; 427 } 428 if ((ctrl & CPU_CONTROL_WBUF_ENABLE) == 0) 429 printf(" WB disabled"); 430 else 431 printf(" WB enabled"); 432 433 if (ctrl & CPU_CONTROL_LABT_ENABLE) 434 printf(" LABT"); 435 else 436 printf(" EABT"); 437 438 if (ctrl & CPU_CONTROL_BPRD_ENABLE) 439 printf(" branch prediction enabled"); 440 441 printf("\n"); 442 /* Print cache info. */ 443 if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0) 444 return; 445 446 if (arm_pcache_unified) { 447 printf(" %dKB/%dB %d-way %s unified cache\n", 448 arm_pdcache_size / 1024, 449 arm_pdcache_line_size, arm_pdcache_ways, 450 wtnames[arm_pcache_type]); 451 } else { 452 printf(" %dKB/%dB %d-way Instruction cache\n", 453 arm_picache_size / 1024, 454 arm_picache_line_size, arm_picache_ways); 455 printf(" %dKB/%dB %d-way %s Data cache\n", 456 arm_pdcache_size / 1024, 457 arm_pdcache_line_size, arm_pdcache_ways, 458 wtnames[arm_pcache_type]); 459 } 460 } 461
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