1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2011 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * Developed by Ben Gray <ben.r.gray@gmail.com>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the company nor the name of the author may be used to
18 * endorse or promote products derived from this software without specific
19 * prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /**
35 * The ARM Cortex-A9 core can support a global timer plus a private and
36 * watchdog timer per core. This driver reserves memory and interrupt
37 * resources for accessing both timer register sets, these resources are
38 * stored globally and used to setup the timecount and eventtimer.
39 *
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
42 *
43 *
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
45 */
46
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/bus.h>
53 #include <sys/kernel.h>
54 #include <sys/module.h>
55 #include <sys/malloc.h>
56 #include <sys/rman.h>
57 #include <sys/timeet.h>
58 #include <sys/timetc.h>
59 #include <sys/watchdog.h>
60 #include <machine/bus.h>
61 #include <machine/cpu.h>
62 #include <machine/intr.h>
63
64 #include <machine/machdep.h> /* For arm_set_delay */
65
66 #include <dev/ofw/openfirm.h>
67 #include <dev/ofw/ofw_bus.h>
68 #include <dev/ofw/ofw_bus_subr.h>
69
70 #include <machine/bus.h>
71
72 #include <arm/arm/mpcore_timervar.h>
73
74 /* Private (per-CPU) timer register map */
75 #define PRV_TIMER_LOAD 0x0000
76 #define PRV_TIMER_COUNT 0x0004
77 #define PRV_TIMER_CTRL 0x0008
78 #define PRV_TIMER_INTR 0x000C
79
80 #define PRV_TIMER_CTR_PRESCALER_SHIFT 8
81 #define PRV_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
82 #define PRV_TIMER_CTRL_AUTO_RELOAD (1UL << 1)
83 #define PRV_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
84
85 #define PRV_TIMER_INTR_EVENT (1UL << 0)
86
87 /* Global timer register map */
88 #define GBL_TIMER_COUNT_LOW 0x0000
89 #define GBL_TIMER_COUNT_HIGH 0x0004
90 #define GBL_TIMER_CTRL 0x0008
91 #define GBL_TIMER_INTR 0x000C
92
93 #define GBL_TIMER_CTR_PRESCALER_SHIFT 8
94 #define GBL_TIMER_CTRL_AUTO_INC (1UL << 3)
95 #define GBL_TIMER_CTRL_IRQ_ENABLE (1UL << 2)
96 #define GBL_TIMER_CTRL_COMP_ENABLE (1UL << 1)
97 #define GBL_TIMER_CTRL_TIMER_ENABLE (1UL << 0)
98
99 #define GBL_TIMER_INTR_EVENT (1UL << 0)
100
101 struct arm_tmr_softc {
102 device_t dev;
103 int irqrid;
104 int memrid;
105 struct resource * gbl_mem;
106 struct resource * prv_mem;
107 struct resource * prv_irq;
108 uint64_t clkfreq;
109 struct eventtimer et;
110 };
111
112 static struct eventtimer *arm_tmr_et;
113 static struct timecounter *arm_tmr_tc;
114 static uint64_t arm_tmr_freq;
115 static boolean_t arm_tmr_freq_varies;
116
117 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
118 #define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
119 #define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
120 #define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)
121
122 static void arm_tmr_delay(int, void *);
123
124 static timecounter_get_t arm_tmr_get_timecount;
125
126 static struct timecounter arm_tmr_timecount = {
127 .tc_name = "MPCore",
128 .tc_get_timecount = arm_tmr_get_timecount,
129 .tc_poll_pps = NULL,
130 .tc_counter_mask = ~0u,
131 .tc_frequency = 0,
132 .tc_quality = 800,
133 };
134
135 #define TMR_GBL 0x01
136 #define TMR_PRV 0x02
137 #define TMR_BOTH (TMR_GBL | TMR_PRV)
138 #define TMR_NONE 0
139
140 static struct ofw_compat_data compat_data[] = {
141 {"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
142 {"arm,cortex-a9-global-timer", TMR_GBL},
143 {"arm,cortex-a5-global-timer", TMR_GBL},
144 {"arm,cortex-a9-twd-timer", TMR_PRV},
145 {"arm,cortex-a5-twd-timer", TMR_PRV},
146 {"arm,arm11mp-twd-timer", TMR_PRV},
147 {NULL, TMR_NONE}
148 };
149
150 /**
151 * arm_tmr_get_timecount - reads the timecount (global) timer
152 * @tc: pointer to arm_tmr_timecount struct
153 *
154 * We only read the lower 32-bits, the timecount stuff only uses 32-bits
155 * so (for now?) ignore the upper 32-bits.
156 *
157 * RETURNS
158 * The lower 32-bits of the counter.
159 */
160 static unsigned
161 arm_tmr_get_timecount(struct timecounter *tc)
162 {
163 struct arm_tmr_softc *sc;
164
165 sc = tc->tc_priv;
166 return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW));
167 }
168
169 /**
170 * arm_tmr_start - starts the eventtimer (private) timer
171 * @et: pointer to eventtimer struct
172 * @first: the number of seconds and fractional sections to trigger in
173 * @period: the period (in seconds and fractional sections) to set
174 *
175 * If the eventtimer is required to be in oneshot mode, period will be
176 * NULL and first will point to the time to trigger. If in periodic mode
177 * period will contain the time period and first may optionally contain
178 * the time for the first period.
179 *
180 * RETURNS
181 * Always returns 0
182 */
183 static int
184 arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
185 {
186 struct arm_tmr_softc *sc;
187 uint32_t load, count;
188 uint32_t ctrl;
189
190 sc = et->et_priv;
191 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
192 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
193
194 ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
195
196 if (period != 0) {
197 load = ((uint32_t)et->et_frequency * period) >> 32;
198 ctrl |= PRV_TIMER_CTRL_AUTO_RELOAD;
199 } else
200 load = 0;
201
202 if (first != 0)
203 count = (uint32_t)((et->et_frequency * first) >> 32);
204 else
205 count = load;
206
207 tmr_prv_write_4(sc, PRV_TIMER_LOAD, load);
208 tmr_prv_write_4(sc, PRV_TIMER_COUNT, count);
209 tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);
210
211 return (0);
212 }
213
214 /**
215 * arm_tmr_stop - stops the eventtimer (private) timer
216 * @et: pointer to eventtimer struct
217 *
218 * Simply stops the private timer by clearing all bits in the ctrl register.
219 *
220 * RETURNS
221 * Always returns 0
222 */
223 static int
224 arm_tmr_stop(struct eventtimer *et)
225 {
226 struct arm_tmr_softc *sc;
227
228 sc = et->et_priv;
229 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
230 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
231 return (0);
232 }
233
234 /**
235 * arm_tmr_intr - ISR for the eventtimer (private) timer
236 * @arg: pointer to arm_tmr_softc struct
237 *
238 * Clears the event register and then calls the eventtimer callback.
239 *
240 * RETURNS
241 * Always returns FILTER_HANDLED
242 */
243 static int
244 arm_tmr_intr(void *arg)
245 {
246 struct arm_tmr_softc *sc;
247
248 sc = arg;
249 tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
250 if (sc->et.et_active)
251 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
252 return (FILTER_HANDLED);
253 }
254
255 /**
256 * arm_tmr_probe - timer probe routine
257 * @dev: new device
258 *
259 * The probe function returns success when probed with the fdt compatible
260 * string set to "arm,mpcore-timers".
261 *
262 * RETURNS
263 * BUS_PROBE_DEFAULT if the fdt device is compatible, otherwise ENXIO.
264 */
265 static int
266 arm_tmr_probe(device_t dev)
267 {
268
269 if (!ofw_bus_status_okay(dev))
270 return (ENXIO);
271
272 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE)
273 return (ENXIO);
274
275 device_set_desc(dev, "ARM MPCore Timers");
276 return (BUS_PROBE_DEFAULT);
277 }
278
279 static int
280 attach_tc(struct arm_tmr_softc *sc)
281 {
282 int rid;
283
284 if (arm_tmr_tc != NULL)
285 return (EBUSY);
286
287 rid = sc->memrid;
288 sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
289 RF_ACTIVE);
290 if (sc->gbl_mem == NULL) {
291 device_printf(sc->dev, "could not allocate gbl mem resources\n");
292 return (ENXIO);
293 }
294 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000);
295
296 arm_tmr_timecount.tc_frequency = sc->clkfreq;
297 arm_tmr_timecount.tc_priv = sc;
298 tc_init(&arm_tmr_timecount);
299 arm_tmr_tc = &arm_tmr_timecount;
300
301 tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
302
303 return (0);
304 }
305
306 static int
307 attach_et(struct arm_tmr_softc *sc)
308 {
309 void *ihl;
310 int irid, mrid;
311
312 if (arm_tmr_et != NULL)
313 return (EBUSY);
314
315 mrid = sc->memrid;
316 sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid,
317 RF_ACTIVE);
318 if (sc->prv_mem == NULL) {
319 device_printf(sc->dev, "could not allocate prv mem resources\n");
320 return (ENXIO);
321 }
322 tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000);
323
324 irid = sc->irqrid;
325 sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE);
326 if (sc->prv_irq == NULL) {
327 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
328 device_printf(sc->dev, "could not allocate prv irq resources\n");
329 return (ENXIO);
330 }
331
332 if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr,
333 NULL, sc, &ihl) != 0) {
334 bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
335 bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq);
336 device_printf(sc->dev, "unable to setup the et irq handler.\n");
337 return (ENXIO);
338 }
339
340 /*
341 * Setup and register the eventtimer. Most event timers set their min
342 * and max period values to some value calculated from the clock
343 * frequency. We might not know yet what our runtime clock frequency
344 * will be, so we just use some safe values. A max of 2 seconds ensures
345 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
346 * we won't overflow our 32-bit timer count register. A min of 20
347 * nanoseconds is pretty much completely arbitrary.
348 */
349 sc->et.et_name = "MPCore";
350 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
351 sc->et.et_quality = 1000;
352 sc->et.et_frequency = sc->clkfreq;
353 sc->et.et_min_period = nstosbt(20);
354 sc->et.et_max_period = 2 * SBT_1S;
355 sc->et.et_start = arm_tmr_start;
356 sc->et.et_stop = arm_tmr_stop;
357 sc->et.et_priv = sc;
358 et_register(&sc->et);
359 arm_tmr_et = &sc->et;
360
361 return (0);
362 }
363
364 /**
365 * arm_tmr_attach - attaches the timer to the simplebus
366 * @dev: new device
367 *
368 * Reserves memory and interrupt resources, stores the softc structure
369 * globally and registers both the timecount and eventtimer objects.
370 *
371 * RETURNS
372 * Zero on success or ENXIO if an error occuried.
373 */
374 static int
375 arm_tmr_attach(device_t dev)
376 {
377 struct arm_tmr_softc *sc;
378 phandle_t node;
379 pcell_t clock;
380 int et_err, tc_err, tmrtype;
381
382 sc = device_get_softc(dev);
383 sc->dev = dev;
384
385 if (arm_tmr_freq_varies) {
386 sc->clkfreq = arm_tmr_freq;
387 } else {
388 if (arm_tmr_freq != 0) {
389 sc->clkfreq = arm_tmr_freq;
390 } else {
391 /* Get the base clock frequency */
392 node = ofw_bus_get_node(dev);
393 if ((OF_getencprop(node, "clock-frequency", &clock,
394 sizeof(clock))) <= 0) {
395 device_printf(dev, "missing clock-frequency "
396 "attribute in FDT\n");
397 return (ENXIO);
398 }
399 sc->clkfreq = clock;
400 }
401 }
402
403 tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
404 tc_err = ENXIO;
405 et_err = ENXIO;
406
407 /*
408 * If we're handling the global timer and it is fixed-frequency, set it
409 * up to use as a timecounter. If it's variable frequency it won't work
410 * as a timecounter. We also can't use it for DELAY(), so hopefully the
411 * platform provides its own implementation. If it doesn't, ours will
412 * get used, but since the frequency isn't set, it will only use the
413 * bogus loop counter.
414 */
415 if (tmrtype & TMR_GBL) {
416 if (!arm_tmr_freq_varies)
417 tc_err = attach_tc(sc);
418 else if (bootverbose)
419 device_printf(sc->dev,
420 "not using variable-frequency device as timecounter\n");
421 sc->memrid++;
422 sc->irqrid++;
423 }
424
425 /* If we are handling the private timer, set it up as an eventtimer. */
426 if (tmrtype & TMR_PRV) {
427 et_err = attach_et(sc);
428 }
429
430 /*
431 * If we didn't successfully set up a timecounter or eventtimer then we
432 * didn't actually attach at all, return error.
433 */
434 if (tc_err != 0 && et_err != 0) {
435 return (ENXIO);
436 }
437
438 #ifdef PLATFORM
439 /*
440 * We can register as the DELAY() implementation only if we successfully
441 * set up the global timer.
442 */
443 if (tc_err == 0)
444 arm_set_delay(arm_tmr_delay, sc);
445 #endif
446
447 return (0);
448 }
449
450 static device_method_t arm_tmr_methods[] = {
451 DEVMETHOD(device_probe, arm_tmr_probe),
452 DEVMETHOD(device_attach, arm_tmr_attach),
453 { 0, 0 }
454 };
455
456 static driver_t arm_tmr_driver = {
457 "mp_tmr",
458 arm_tmr_methods,
459 sizeof(struct arm_tmr_softc),
460 };
461
462 static devclass_t arm_tmr_devclass;
463
464 EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
465 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
466 EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
467 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
468
469 /*
470 * Handle a change in clock frequency. The mpcore timer runs at half the CPU
471 * frequency. When the CPU frequency changes due to power-saving or thermal
472 * management, the platform-specific code that causes the frequency change calls
473 * this routine to inform the clock driver, and we in turn inform the event
474 * timer system, which actually updates the value in et->frequency for us and
475 * reschedules the current event(s) in a way that's atomic with respect to
476 * start/stop/intr code that may be running on various CPUs at the time of the
477 * call.
478 *
479 * This routine can also be called by a platform's early init code. If the
480 * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
481 * to register as an eventtimer, but not a timecounter. If the value passed in
482 * is any other non-zero value it is used as the fixed frequency for the timer.
483 */
484 void
485 arm_tmr_change_frequency(uint64_t newfreq)
486 {
487
488 if (newfreq == ARM_TMR_FREQUENCY_VARIES) {
489 arm_tmr_freq_varies = true;
490 return;
491 }
492
493 arm_tmr_freq = newfreq;
494 if (arm_tmr_et != NULL)
495 et_change_frequency(arm_tmr_et, newfreq);
496 }
497
498 static void
499 arm_tmr_delay(int usec, void *arg)
500 {
501 struct arm_tmr_softc *sc = arg;
502 int32_t counts_per_usec;
503 int32_t counts;
504 uint32_t first, last;
505
506 /* Get the number of times to count */
507 counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
508
509 /*
510 * Clamp the timeout at a maximum value (about 32 seconds with
511 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
512 * near that length of time and if they are, they should be hung
513 * out to dry.
514 */
515 if (usec >= (0x80000000U / counts_per_usec))
516 counts = (0x80000000U / counts_per_usec) - 1;
517 else
518 counts = usec * counts_per_usec;
519
520 first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
521
522 while (counts > 0) {
523 last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
524 counts -= (int32_t)(last - first);
525 first = last;
526 }
527 }
528
529 #ifndef PLATFORM
530 /**
531 * DELAY - Delay for at least usec microseconds.
532 * @usec: number of microseconds to delay by
533 *
534 * This function is called all over the kernel and is suppose to provide a
535 * consistent delay. This function may also be called before the console
536 * is setup so no printf's can be called here.
537 *
538 * RETURNS:
539 * nothing
540 */
541 void
542 DELAY(int usec)
543 {
544 struct arm_tmr_softc *sc;
545 int32_t counts;
546
547 TSENTER();
548 /* Check the timers are setup, if not just use a for loop for the meantime */
549 if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) {
550 for (; usec > 0; usec--)
551 for (counts = 200; counts > 0; counts--)
552 cpufunc_nullop(); /* Prevent gcc from optimizing
553 * out the loop
554 */
555 } else {
556 sc = arm_tmr_tc->tc_priv;
557 arm_tmr_delay(usec, sc);
558 }
559 TSEXIT();
560 }
561 #endif
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