Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/pl310.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2012 Olivier Houchard <cognet@FreeBSD.org> 5 * Copyright (c) 2011 6 * Ben Gray <ben.r.gray@gmail.com>. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the company nor the name of the author may be used to 18 * endorse or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 30 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/rman.h> 40 #include <sys/module.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <machine/intr.h> 44 45 #include <machine/bus.h> 46 #include <machine/pl310.h> 47 #ifdef PLATFORM 48 #include <machine/platformvar.h> 49 #endif 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #ifdef PLATFORM 56 #include "platform_pl310_if.h" 57 #endif 58 59 /* 60 * Define this if you need to disable PL310 for debugging purpose 61 * Spec: 62 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246e/DDI0246E_l2c310_r3p1_trm.pdf 63 */ 64 65 /* 66 * Hardcode errata for now 67 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246b/pr01s02s02.html 68 */ 69 #define PL310_ERRATA_588369 70 #define PL310_ERRATA_753970 71 #define PL310_ERRATA_727915 72 73 #define PL310_LOCK(sc) do { \ 74 mtx_lock_spin(&(sc)->sc_mtx); \ 75 } while(0); 76 77 #define PL310_UNLOCK(sc) do { \ 78 mtx_unlock_spin(&(sc)->sc_mtx); \ 79 } while(0); 80 81 static int pl310_enabled = 1; 82 TUNABLE_INT("hw.pl310.enabled", &pl310_enabled); 83 84 static uint32_t g_l2cache_way_mask; 85 86 static const uint32_t g_l2cache_line_size = 32; 87 static const uint32_t g_l2cache_align_mask = (32 - 1); 88 89 static uint32_t g_l2cache_size; 90 static uint32_t g_way_size; 91 static uint32_t g_ways_assoc; 92 93 static struct pl310_softc *pl310_softc; 94 95 static struct ofw_compat_data compat_data[] = { 96 {"arm,pl310", true}, /* Non-standard, FreeBSD. */ 97 {"arm,pl310-cache", true}, 98 {NULL, false} 99 }; 100 101 #ifdef PLATFORM 102 static void 103 platform_pl310_init(struct pl310_softc *sc) 104 { 105 106 PLATFORM_PL310_INIT(platform_obj(), sc); 107 } 108 109 static void 110 platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val) 111 { 112 113 PLATFORM_PL310_WRITE_CTRL(platform_obj(), sc, val); 114 } 115 116 static void 117 platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val) 118 { 119 120 PLATFORM_PL310_WRITE_DEBUG(platform_obj(), sc, val); 121 } 122 #endif 123 124 static void 125 pl310_print_config(struct pl310_softc *sc) 126 { 127 uint32_t aux, prefetch; 128 const char *dis = "disabled"; 129 const char *ena = "enabled"; 130 131 aux = pl310_read4(sc, PL310_AUX_CTRL); 132 prefetch = pl310_read4(sc, PL310_PREFETCH_CTRL); 133 134 device_printf(sc->sc_dev, "Early BRESP response: %s\n", 135 (aux & AUX_CTRL_EARLY_BRESP) ? ena : dis); 136 device_printf(sc->sc_dev, "Instruction prefetch: %s\n", 137 (aux & AUX_CTRL_INSTR_PREFETCH) ? ena : dis); 138 device_printf(sc->sc_dev, "Data prefetch: %s\n", 139 (aux & AUX_CTRL_DATA_PREFETCH) ? ena : dis); 140 device_printf(sc->sc_dev, "Non-secure interrupt control: %s\n", 141 (aux & AUX_CTRL_NS_INT_CTRL) ? ena : dis); 142 device_printf(sc->sc_dev, "Non-secure lockdown: %s\n", 143 (aux & AUX_CTRL_NS_LOCKDOWN) ? ena : dis); 144 device_printf(sc->sc_dev, "Share override: %s\n", 145 (aux & AUX_CTRL_SHARE_OVERRIDE) ? ena : dis); 146 147 device_printf(sc->sc_dev, "Double linefill: %s\n", 148 (prefetch & PREFETCH_CTRL_DL) ? ena : dis); 149 device_printf(sc->sc_dev, "Instruction prefetch: %s\n", 150 (prefetch & PREFETCH_CTRL_INSTR_PREFETCH) ? ena : dis); 151 device_printf(sc->sc_dev, "Data prefetch: %s\n", 152 (prefetch & PREFETCH_CTRL_DATA_PREFETCH) ? ena : dis); 153 device_printf(sc->sc_dev, "Double linefill on WRAP request: %s\n", 154 (prefetch & PREFETCH_CTRL_DL_ON_WRAP) ? ena : dis); 155 device_printf(sc->sc_dev, "Prefetch drop: %s\n", 156 (prefetch & PREFETCH_CTRL_PREFETCH_DROP) ? ena : dis); 157 device_printf(sc->sc_dev, "Incr double Linefill: %s\n", 158 (prefetch & PREFETCH_CTRL_INCR_DL) ? ena : dis); 159 device_printf(sc->sc_dev, "Not same ID on exclusive sequence: %s\n", 160 (prefetch & PREFETCH_CTRL_NOTSAMEID) ? ena : dis); 161 device_printf(sc->sc_dev, "Prefetch offset: %d\n", 162 (prefetch & PREFETCH_CTRL_OFFSET_MASK)); 163 } 164 165 void 166 pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg, 167 uint32_t read, uint32_t write, uint32_t setup) 168 { 169 uint32_t v; 170 171 KASSERT(which_reg == PL310_TAG_RAM_CTRL || 172 which_reg == PL310_DATA_RAM_CTRL, 173 ("bad pl310 ram latency register address")); 174 175 v = pl310_read4(sc, which_reg); 176 if (setup != 0) { 177 KASSERT(setup <= 8, ("bad pl310 setup latency: %d", setup)); 178 v &= ~RAM_CTRL_SETUP_MASK; 179 v |= (setup - 1) << RAM_CTRL_SETUP_SHIFT; 180 } 181 if (read != 0) { 182 KASSERT(read <= 8, ("bad pl310 read latency: %d", read)); 183 v &= ~RAM_CTRL_READ_MASK; 184 v |= (read - 1) << RAM_CTRL_READ_SHIFT; 185 } 186 if (write != 0) { 187 KASSERT(write <= 8, ("bad pl310 write latency: %d", write)); 188 v &= ~RAM_CTRL_WRITE_MASK; 189 v |= (write - 1) << RAM_CTRL_WRITE_SHIFT; 190 } 191 pl310_write4(sc, which_reg, v); 192 } 193 194 static int 195 pl310_filter(void *arg) 196 { 197 struct pl310_softc *sc = arg; 198 uint32_t intr; 199 200 intr = pl310_read4(sc, PL310_INTR_MASK); 201 202 if (!sc->sc_enabled && (intr & INTR_MASK_ECNTR)) { 203 /* 204 * This is for debug purpose, so be blunt about it 205 * We disable PL310 only when something fishy is going 206 * on and we need to make sure L2 cache is 100% disabled 207 */ 208 panic("pl310: caches disabled but cache event detected\n"); 209 } 210 211 return (FILTER_HANDLED); 212 } 213 214 static __inline void 215 pl310_wait_background_op(uint32_t off, uint32_t mask) 216 { 217 218 while (pl310_read4(pl310_softc, off) & mask) 219 continue; 220 } 221 222 /** 223 * pl310_cache_sync - performs a cache sync operation 224 * 225 * According to the TRM: 226 * 227 * "Before writing to any other register you must perform an explicit 228 * Cache Sync operation. This is particularly important when the cache is 229 * enabled and changes to how the cache allocates new lines are to be made." 230 * 231 * 232 */ 233 static __inline void 234 pl310_cache_sync(void) 235 { 236 237 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 238 return; 239 240 /* Do not sync outer cache on IO coherent platform */ 241 if (pl310_softc->sc_io_coherent) 242 return; 243 244 #ifdef PL310_ERRATA_753970 245 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0) 246 /* Write uncached PL310 register */ 247 pl310_write4(pl310_softc, 0x740, 0xffffffff); 248 else 249 #endif 250 pl310_write4(pl310_softc, PL310_CACHE_SYNC, 0xffffffff); 251 } 252 253 static void 254 pl310_wbinv_all(void) 255 { 256 257 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 258 return; 259 260 PL310_LOCK(pl310_softc); 261 #ifdef PL310_ERRATA_727915 262 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r2p0) { 263 int i, j; 264 265 for (i = 0; i < g_ways_assoc; i++) { 266 for (j = 0; j < g_way_size / g_l2cache_line_size; j++) { 267 pl310_write4(pl310_softc, 268 PL310_CLEAN_INV_LINE_IDX, 269 (i << 28 | j << 5)); 270 } 271 } 272 pl310_cache_sync(); 273 PL310_UNLOCK(pl310_softc); 274 return; 275 } 276 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0) 277 platform_pl310_write_debug(pl310_softc, 3); 278 #endif 279 pl310_write4(pl310_softc, PL310_CLEAN_INV_WAY, g_l2cache_way_mask); 280 pl310_wait_background_op(PL310_CLEAN_INV_WAY, g_l2cache_way_mask); 281 pl310_cache_sync(); 282 #ifdef PL310_ERRATA_727915 283 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0) 284 platform_pl310_write_debug(pl310_softc, 0); 285 #endif 286 PL310_UNLOCK(pl310_softc); 287 } 288 289 static void 290 pl310_wbinv_range(vm_paddr_t start, vm_size_t size) 291 { 292 293 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 294 return; 295 296 PL310_LOCK(pl310_softc); 297 if (start & g_l2cache_align_mask) { 298 size += start & g_l2cache_align_mask; 299 start &= ~g_l2cache_align_mask; 300 } 301 if (size & g_l2cache_align_mask) { 302 size &= ~g_l2cache_align_mask; 303 size += g_l2cache_line_size; 304 } 305 306 #ifdef PL310_ERRATA_727915 307 if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 && 308 pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1) 309 platform_pl310_write_debug(pl310_softc, 3); 310 #endif 311 while (size > 0) { 312 #ifdef PL310_ERRATA_588369 313 if (pl310_softc->sc_rtl_revision <= CACHE_ID_RELEASE_r1p0) { 314 /* 315 * Errata 588369 says that clean + inv may keep the 316 * cache line if it was clean, the recommanded 317 * workaround is to clean then invalidate the cache 318 * line, with write-back and cache linefill disabled. 319 */ 320 pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start); 321 pl310_write4(pl310_softc, PL310_INV_LINE_PA, start); 322 } else 323 #endif 324 pl310_write4(pl310_softc, PL310_CLEAN_INV_LINE_PA, 325 start); 326 start += g_l2cache_line_size; 327 size -= g_l2cache_line_size; 328 } 329 #ifdef PL310_ERRATA_727915 330 if (pl310_softc->sc_rtl_revision >= CACHE_ID_RELEASE_r2p0 && 331 pl310_softc->sc_rtl_revision < CACHE_ID_RELEASE_r3p1) 332 platform_pl310_write_debug(pl310_softc, 0); 333 #endif 334 335 pl310_cache_sync(); 336 PL310_UNLOCK(pl310_softc); 337 } 338 339 static void 340 pl310_wb_range(vm_paddr_t start, vm_size_t size) 341 { 342 343 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 344 return; 345 346 PL310_LOCK(pl310_softc); 347 if (start & g_l2cache_align_mask) { 348 size += start & g_l2cache_align_mask; 349 start &= ~g_l2cache_align_mask; 350 } 351 352 if (size & g_l2cache_align_mask) { 353 size &= ~g_l2cache_align_mask; 354 size += g_l2cache_line_size; 355 } 356 357 while (size > 0) { 358 pl310_write4(pl310_softc, PL310_CLEAN_LINE_PA, start); 359 start += g_l2cache_line_size; 360 size -= g_l2cache_line_size; 361 } 362 363 pl310_cache_sync(); 364 PL310_UNLOCK(pl310_softc); 365 } 366 367 static void 368 pl310_inv_range(vm_paddr_t start, vm_size_t size) 369 { 370 371 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 372 return; 373 374 PL310_LOCK(pl310_softc); 375 if (start & g_l2cache_align_mask) { 376 size += start & g_l2cache_align_mask; 377 start &= ~g_l2cache_align_mask; 378 } 379 if (size & g_l2cache_align_mask) { 380 size &= ~g_l2cache_align_mask; 381 size += g_l2cache_line_size; 382 } 383 while (size > 0) { 384 pl310_write4(pl310_softc, PL310_INV_LINE_PA, start); 385 start += g_l2cache_line_size; 386 size -= g_l2cache_line_size; 387 } 388 389 pl310_cache_sync(); 390 PL310_UNLOCK(pl310_softc); 391 } 392 393 static void 394 pl310_drain_writebuf(void) 395 { 396 397 if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) 398 return; 399 400 PL310_LOCK(pl310_softc); 401 pl310_cache_sync(); 402 PL310_UNLOCK(pl310_softc); 403 } 404 405 static void 406 pl310_set_way_sizes(struct pl310_softc *sc) 407 { 408 uint32_t aux_value; 409 410 aux_value = pl310_read4(sc, PL310_AUX_CTRL); 411 g_way_size = (aux_value & AUX_CTRL_WAY_SIZE_MASK) >> 412 AUX_CTRL_WAY_SIZE_SHIFT; 413 g_way_size = 1 << (g_way_size + 13); 414 if (aux_value & (1 << AUX_CTRL_ASSOCIATIVITY_SHIFT)) 415 g_ways_assoc = 16; 416 else 417 g_ways_assoc = 8; 418 g_l2cache_way_mask = (1 << g_ways_assoc) - 1; 419 g_l2cache_size = g_way_size * g_ways_assoc; 420 } 421 422 /* 423 * Setup interrupt handling. This is done only if the cache controller is 424 * disabled, for debugging. We set counters so when a cache event happens we'll 425 * get interrupted and be warned that something is wrong, because no cache 426 * events should happen if we're disabled. 427 */ 428 static void 429 pl310_config_intr(void *arg) 430 { 431 struct pl310_softc * sc; 432 433 sc = arg; 434 435 /* activate the interrupt */ 436 bus_setup_intr(sc->sc_dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 437 pl310_filter, NULL, sc, &sc->sc_irq_h); 438 439 /* Cache Line Eviction for Counter 0 */ 440 pl310_write4(sc, PL310_EVENT_COUNTER0_CONF, 441 EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_CO); 442 /* Data Read Request for Counter 1 */ 443 pl310_write4(sc, PL310_EVENT_COUNTER1_CONF, 444 EVENT_COUNTER_CONF_INCR | EVENT_COUNTER_CONF_DRREQ); 445 446 /* Enable and clear pending interrupts */ 447 pl310_write4(sc, PL310_INTR_CLEAR, INTR_MASK_ECNTR); 448 pl310_write4(sc, PL310_INTR_MASK, INTR_MASK_ALL); 449 450 /* Enable counters and reset C0 and C1 */ 451 pl310_write4(sc, PL310_EVENT_COUNTER_CTRL, 452 EVENT_COUNTER_CTRL_ENABLED | 453 EVENT_COUNTER_CTRL_C0_RESET | 454 EVENT_COUNTER_CTRL_C1_RESET); 455 456 config_intrhook_disestablish(sc->sc_ich); 457 free(sc->sc_ich, M_DEVBUF); 458 sc->sc_ich = NULL; 459 } 460 461 static int 462 pl310_probe(device_t dev) 463 { 464 465 if (!ofw_bus_status_okay(dev)) 466 return (ENXIO); 467 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 468 return (ENXIO); 469 device_set_desc(dev, "PL310 L2 cache controller"); 470 return (0); 471 } 472 473 static int 474 pl310_attach(device_t dev) 475 { 476 struct pl310_softc *sc = device_get_softc(dev); 477 int rid; 478 uint32_t cache_id, debug_ctrl; 479 phandle_t node; 480 481 sc->sc_dev = dev; 482 rid = 0; 483 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 484 RF_ACTIVE); 485 if (sc->sc_mem_res == NULL) 486 panic("%s: Cannot map registers", device_get_name(dev)); 487 488 /* Allocate an IRQ resource */ 489 rid = 0; 490 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 491 RF_ACTIVE | RF_SHAREABLE); 492 if (sc->sc_irq_res == NULL) { 493 device_printf(dev, "cannot allocate IRQ, not using interrupt\n"); 494 } 495 496 pl310_softc = sc; 497 mtx_init(&sc->sc_mtx, "pl310lock", NULL, MTX_SPIN); 498 499 cache_id = pl310_read4(sc, PL310_CACHE_ID); 500 sc->sc_rtl_revision = (cache_id >> CACHE_ID_RELEASE_SHIFT) & 501 CACHE_ID_RELEASE_MASK; 502 device_printf(dev, "Part number: 0x%x, release: 0x%x\n", 503 (cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK, 504 (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK); 505 506 /* 507 * Test for "arm,io-coherent" property and disable sync operation if 508 * platform is I/O coherent. Outer sync operations are not needed 509 * on coherent platform and may be harmful in certain situations. 510 */ 511 node = ofw_bus_get_node(dev); 512 if (OF_hasprop(node, "arm,io-coherent")) 513 sc->sc_io_coherent = true; 514 515 /* 516 * If L2 cache is already enabled then something has violated the rules, 517 * because caches are supposed to be off at kernel entry. The cache 518 * must be disabled to write the configuration registers without 519 * triggering an access error (SLVERR), but there's no documented safe 520 * procedure for disabling the L2 cache in the manual. So we'll try to 521 * invent one: 522 * - Use the debug register to force write-through mode and prevent 523 * linefills (allocation of new lines on read); now anything we do 524 * will not cause new data to come into the L2 cache. 525 * - Writeback and invalidate the current contents. 526 * - Disable the controller. 527 * - Restore the original debug settings. 528 */ 529 if (pl310_read4(sc, PL310_CTRL) & CTRL_ENABLED) { 530 device_printf(dev, "Warning: L2 Cache should not already be " 531 "active; trying to de-activate and re-initialize...\n"); 532 sc->sc_enabled = 1; 533 debug_ctrl = pl310_read4(sc, PL310_DEBUG_CTRL); 534 platform_pl310_write_debug(sc, debug_ctrl | 535 DEBUG_CTRL_DISABLE_WRITEBACK | DEBUG_CTRL_DISABLE_LINEFILL); 536 pl310_set_way_sizes(sc); 537 pl310_wbinv_all(); 538 platform_pl310_write_ctrl(sc, CTRL_DISABLED); 539 platform_pl310_write_debug(sc, debug_ctrl); 540 } 541 sc->sc_enabled = pl310_enabled; 542 543 if (sc->sc_enabled) { 544 platform_pl310_init(sc); 545 pl310_set_way_sizes(sc); /* platform init might change these */ 546 pl310_write4(pl310_softc, PL310_INV_WAY, 0xffff); 547 pl310_wait_background_op(PL310_INV_WAY, 0xffff); 548 platform_pl310_write_ctrl(sc, CTRL_ENABLED); 549 device_printf(dev, "L2 Cache enabled: %uKB/%dB %d ways\n", 550 (g_l2cache_size / 1024), g_l2cache_line_size, g_ways_assoc); 551 if (bootverbose) 552 pl310_print_config(sc); 553 } else { 554 if (sc->sc_irq_res != NULL) { 555 sc->sc_ich = malloc(sizeof(*sc->sc_ich), M_DEVBUF, M_WAITOK); 556 sc->sc_ich->ich_func = pl310_config_intr; 557 sc->sc_ich->ich_arg = sc; 558 if (config_intrhook_establish(sc->sc_ich) != 0) { 559 device_printf(dev, 560 "config_intrhook_establish failed\n"); 561 free(sc->sc_ich, M_DEVBUF); 562 return(ENXIO); 563 } 564 } 565 566 device_printf(dev, "L2 Cache disabled\n"); 567 } 568 569 /* Set the l2 functions in the set of cpufuncs */ 570 cpufuncs.cf_l2cache_wbinv_all = pl310_wbinv_all; 571 cpufuncs.cf_l2cache_wbinv_range = pl310_wbinv_range; 572 cpufuncs.cf_l2cache_inv_range = pl310_inv_range; 573 cpufuncs.cf_l2cache_wb_range = pl310_wb_range; 574 cpufuncs.cf_l2cache_drain_writebuf = pl310_drain_writebuf; 575 576 return (0); 577 } 578 579 static device_method_t pl310_methods[] = { 580 DEVMETHOD(device_probe, pl310_probe), 581 DEVMETHOD(device_attach, pl310_attach), 582 DEVMETHOD_END 583 }; 584 585 static driver_t pl310_driver = { 586 "l2cache", 587 pl310_methods, 588 sizeof(struct pl310_softc), 589 }; 590 static devclass_t pl310_devclass; 591 592 EARLY_DRIVER_MODULE(pl310, simplebus, pl310_driver, pl310_devclass, 0, 0, 593 BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE);
Cache object: eed947fe5ac2126b3df8b68d748d9518
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