FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/pmap.c
1 /* From: $NetBSD: pmap.c,v 1.148 2004/04/03 04:35:48 bsh Exp $ */
2 /*-
3 * Copyright 2004 Olivier Houchard.
4 * Copyright 2003 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*-
39 * Copyright (c) 2002-2003 Wasabi Systems, Inc.
40 * Copyright (c) 2001 Richard Earnshaw
41 * Copyright (c) 2001-2002 Christopher Gilbert
42 * All rights reserved.
43 *
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. The name of the company nor the name of the author may be used to
50 * endorse or promote products derived from this software without specific
51 * prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
54 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
55 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
57 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
58 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
60 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
61 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
62 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
63 * SUCH DAMAGE.
64 */
65 /*-
66 * Copyright (c) 1999 The NetBSD Foundation, Inc.
67 * All rights reserved.
68 *
69 * This code is derived from software contributed to The NetBSD Foundation
70 * by Charles M. Hannum.
71 *
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
74 * are met:
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
80 * 3. All advertising materials mentioning features or use of this software
81 * must display the following acknowledgement:
82 * This product includes software developed by the NetBSD
83 * Foundation, Inc. and its contributors.
84 * 4. Neither the name of The NetBSD Foundation nor the names of its
85 * contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
89 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
90 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
91 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
92 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
98 * POSSIBILITY OF SUCH DAMAGE.
99 */
100
101 /*-
102 * Copyright (c) 1994-1998 Mark Brinicombe.
103 * Copyright (c) 1994 Brini.
104 * All rights reserved.
105 *
106 * This code is derived from software written for Brini by Mark Brinicombe
107 *
108 * Redistribution and use in source and binary forms, with or without
109 * modification, are permitted provided that the following conditions
110 * are met:
111 * 1. Redistributions of source code must retain the above copyright
112 * notice, this list of conditions and the following disclaimer.
113 * 2. Redistributions in binary form must reproduce the above copyright
114 * notice, this list of conditions and the following disclaimer in the
115 * documentation and/or other materials provided with the distribution.
116 * 3. All advertising materials mentioning features or use of this software
117 * must display the following acknowledgement:
118 * This product includes software developed by Mark Brinicombe.
119 * 4. The name of the author may not be used to endorse or promote products
120 * derived from this software without specific prior written permission.
121 *
122 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
123 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
124 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
125 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
126 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
127 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
128 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
129 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
130 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
131 *
132 * RiscBSD kernel project
133 *
134 * pmap.c
135 *
136 * Machine dependant vm stuff
137 *
138 * Created : 20/09/94
139 */
140
141 /*
142 * Special compilation symbols
143 * PMAP_DEBUG - Build in pmap_debug_level code
144 */
145 /* Include header files */
146
147 #include "opt_vm.h"
148
149 #include <sys/cdefs.h>
150 __FBSDID("$FreeBSD: releng/6.2/sys/arm/arm/pmap.c 159889 2006-06-23 17:41:02Z cognet $");
151 #include <sys/param.h>
152 #include <sys/systm.h>
153 #include <sys/kernel.h>
154 #include <sys/proc.h>
155 #include <sys/malloc.h>
156 #include <sys/msgbuf.h>
157 #include <sys/vmmeter.h>
158 #include <sys/mman.h>
159 #include <sys/smp.h>
160 #include <sys/sx.h>
161 #include <sys/sched.h>
162
163 #include <vm/vm.h>
164 #include <vm/uma.h>
165 #include <vm/pmap.h>
166 #include <vm/vm_kern.h>
167 #include <vm/vm_object.h>
168 #include <vm/vm_map.h>
169 #include <vm/vm_page.h>
170 #include <vm/vm_pageout.h>
171 #include <vm/vm_extern.h>
172 #include <sys/lock.h>
173 #include <sys/mutex.h>
174 #include <machine/md_var.h>
175 #include <machine/vmparam.h>
176 #include <machine/cpu.h>
177 #include <machine/cpufunc.h>
178 #include <machine/pcb.h>
179
180 #ifdef PMAP_DEBUG
181 #define PDEBUG(_lev_,_stat_) \
182 if (pmap_debug_level >= (_lev_)) \
183 ((_stat_))
184 #define dprintf printf
185
186 int pmap_debug_level = 0;
187 #define PMAP_INLINE
188 #else /* PMAP_DEBUG */
189 #define PDEBUG(_lev_,_stat_) /* Nothing */
190 #define dprintf(x, arg...)
191 #define PMAP_INLINE __inline
192 #endif /* PMAP_DEBUG */
193
194 extern struct pv_addr systempage;
195 /*
196 * Internal function prototypes
197 */
198 static void pmap_free_pv_entry (pv_entry_t);
199 static pv_entry_t pmap_get_pv_entry(void);
200
201 static void pmap_vac_me_harder(struct vm_page *, pmap_t,
202 vm_offset_t);
203 static void pmap_vac_me_kpmap(struct vm_page *, pmap_t,
204 vm_offset_t);
205 static void pmap_vac_me_user(struct vm_page *, pmap_t, vm_offset_t);
206 static void pmap_alloc_l1(pmap_t);
207 static void pmap_free_l1(pmap_t);
208 static void pmap_use_l1(pmap_t);
209
210 static int pmap_clearbit(struct vm_page *, u_int);
211
212 static struct l2_bucket *pmap_get_l2_bucket(pmap_t, vm_offset_t);
213 static struct l2_bucket *pmap_alloc_l2_bucket(pmap_t, vm_offset_t);
214 static void pmap_free_l2_bucket(pmap_t, struct l2_bucket *, u_int);
215 static vm_offset_t kernel_pt_lookup(vm_paddr_t);
216
217 static MALLOC_DEFINE(M_VMPMAP, "pmap", "PMAP L1");
218
219 vm_offset_t avail_end; /* PA of last available physical page */
220 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
221 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
222 vm_offset_t pmap_curmaxkvaddr;
223
224 extern void *end;
225 vm_offset_t kernel_vm_end = 0;
226
227 struct pmap kernel_pmap_store;
228 pmap_t kernel_pmap;
229
230 static pt_entry_t *csrc_pte, *cdst_pte;
231 static vm_offset_t csrcp, cdstp;
232 static struct mtx cmtx;
233
234 static void pmap_init_l1(struct l1_ttable *, pd_entry_t *);
235 /*
236 * These routines are called when the CPU type is identified to set up
237 * the PTE prototypes, cache modes, etc.
238 *
239 * The variables are always here, just in case LKMs need to reference
240 * them (though, they shouldn't).
241 */
242
243 pt_entry_t pte_l1_s_cache_mode;
244 pt_entry_t pte_l1_s_cache_mode_pt;
245 pt_entry_t pte_l1_s_cache_mask;
246
247 pt_entry_t pte_l2_l_cache_mode;
248 pt_entry_t pte_l2_l_cache_mode_pt;
249 pt_entry_t pte_l2_l_cache_mask;
250
251 pt_entry_t pte_l2_s_cache_mode;
252 pt_entry_t pte_l2_s_cache_mode_pt;
253 pt_entry_t pte_l2_s_cache_mask;
254
255 pt_entry_t pte_l2_s_prot_u;
256 pt_entry_t pte_l2_s_prot_w;
257 pt_entry_t pte_l2_s_prot_mask;
258
259 pt_entry_t pte_l1_s_proto;
260 pt_entry_t pte_l1_c_proto;
261 pt_entry_t pte_l2_s_proto;
262
263 void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
264 void (*pmap_zero_page_func)(vm_paddr_t, int, int);
265 /*
266 * Which pmap is currently 'live' in the cache
267 *
268 * XXXSCW: Fix for SMP ...
269 */
270 union pmap_cache_state *pmap_cache_state;
271
272 LIST_HEAD(pmaplist, pmap);
273 struct pmaplist allpmaps;
274
275 /* static pt_entry_t *msgbufmap;*/
276 struct msgbuf *msgbufp = 0;
277
278 extern void bcopy_page(vm_offset_t, vm_offset_t);
279 extern void bzero_page(vm_offset_t);
280
281 char *_tmppt;
282
283 /*
284 * Metadata for L1 translation tables.
285 */
286 struct l1_ttable {
287 /* Entry on the L1 Table list */
288 SLIST_ENTRY(l1_ttable) l1_link;
289
290 /* Entry on the L1 Least Recently Used list */
291 TAILQ_ENTRY(l1_ttable) l1_lru;
292
293 /* Track how many domains are allocated from this L1 */
294 volatile u_int l1_domain_use_count;
295
296 /*
297 * A free-list of domain numbers for this L1.
298 * We avoid using ffs() and a bitmap to track domains since ffs()
299 * is slow on ARM.
300 */
301 u_int8_t l1_domain_first;
302 u_int8_t l1_domain_free[PMAP_DOMAINS];
303
304 /* Physical address of this L1 page table */
305 vm_paddr_t l1_physaddr;
306
307 /* KVA of this L1 page table */
308 pd_entry_t *l1_kva;
309 };
310
311 /*
312 * Convert a virtual address into its L1 table index. That is, the
313 * index used to locate the L2 descriptor table pointer in an L1 table.
314 * This is basically used to index l1->l1_kva[].
315 *
316 * Each L2 descriptor table represents 1MB of VA space.
317 */
318 #define L1_IDX(va) (((vm_offset_t)(va)) >> L1_S_SHIFT)
319
320 /*
321 * L1 Page Tables are tracked using a Least Recently Used list.
322 * - New L1s are allocated from the HEAD.
323 * - Freed L1s are added to the TAIl.
324 * - Recently accessed L1s (where an 'access' is some change to one of
325 * the userland pmaps which owns this L1) are moved to the TAIL.
326 */
327 static TAILQ_HEAD(, l1_ttable) l1_lru_list;
328 /*
329 * A list of all L1 tables
330 */
331 static SLIST_HEAD(, l1_ttable) l1_list;
332 static struct mtx l1_lru_lock;
333
334 /*
335 * The l2_dtable tracks L2_BUCKET_SIZE worth of L1 slots.
336 *
337 * This is normally 16MB worth L2 page descriptors for any given pmap.
338 * Reference counts are maintained for L2 descriptors so they can be
339 * freed when empty.
340 */
341 struct l2_dtable {
342 /* The number of L2 page descriptors allocated to this l2_dtable */
343 u_int l2_occupancy;
344
345 /* List of L2 page descriptors */
346 struct l2_bucket {
347 pt_entry_t *l2b_kva; /* KVA of L2 Descriptor Table */
348 vm_paddr_t l2b_phys; /* Physical address of same */
349 u_short l2b_l1idx; /* This L2 table's L1 index */
350 u_short l2b_occupancy; /* How many active descriptors */
351 } l2_bucket[L2_BUCKET_SIZE];
352 };
353
354 /* pmap_kenter_internal flags */
355 #define KENTER_CACHE 0x1
356 #define KENTER_USER 0x2
357
358 /*
359 * Given an L1 table index, calculate the corresponding l2_dtable index
360 * and bucket index within the l2_dtable.
361 */
362 #define L2_IDX(l1idx) (((l1idx) >> L2_BUCKET_LOG2) & \
363 (L2_SIZE - 1))
364 #define L2_BUCKET(l1idx) ((l1idx) & (L2_BUCKET_SIZE - 1))
365
366 /*
367 * Given a virtual address, this macro returns the
368 * virtual address required to drop into the next L2 bucket.
369 */
370 #define L2_NEXT_BUCKET(va) (((va) & L1_S_FRAME) + L1_S_SIZE)
371
372 /*
373 * L2 allocation.
374 */
375 #define pmap_alloc_l2_dtable() \
376 (void*)uma_zalloc(l2table_zone, M_NOWAIT)
377 #define pmap_free_l2_dtable(l2) \
378 uma_zfree(l2table_zone, l2)
379
380 /*
381 * We try to map the page tables write-through, if possible. However, not
382 * all CPUs have a write-through cache mode, so on those we have to sync
383 * the cache when we frob page tables.
384 *
385 * We try to evaluate this at compile time, if possible. However, it's
386 * not always possible to do that, hence this run-time var.
387 */
388 int pmap_needs_pte_sync;
389
390 /*
391 * Macro to determine if a mapping might be resident in the
392 * instruction cache and/or TLB
393 */
394 #define PV_BEEN_EXECD(f) (((f) & (PVF_REF | PVF_EXEC)) == (PVF_REF | PVF_EXEC))
395
396 /*
397 * Macro to determine if a mapping might be resident in the
398 * data cache and/or TLB
399 */
400 #define PV_BEEN_REFD(f) (((f) & PVF_REF) != 0)
401
402 /*
403 * Data for the pv entry allocation mechanism
404 */
405 #define MINPV 2048
406
407 #ifndef PMAP_SHPGPERPROC
408 #define PMAP_SHPGPERPROC 200
409 #endif
410
411 #define pmap_is_current(pm) ((pm) == pmap_kernel() || \
412 curproc->p_vmspace->vm_map.pmap == (pm))
413 static uma_zone_t pvzone;
414 uma_zone_t l2zone;
415 static uma_zone_t l2table_zone;
416 static vm_offset_t pmap_kernel_l2dtable_kva;
417 static vm_offset_t pmap_kernel_l2ptp_kva;
418 static vm_paddr_t pmap_kernel_l2ptp_phys;
419 static struct vm_object pvzone_obj;
420 static struct vm_object l2zone_obj;
421 static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
422 int pmap_pagedaemon_waken = 0;
423
424 /*
425 * This list exists for the benefit of pmap_map_chunk(). It keeps track
426 * of the kernel L2 tables during bootstrap, so that pmap_map_chunk() can
427 * find them as necessary.
428 *
429 * Note that the data on this list MUST remain valid after initarm() returns,
430 * as pmap_bootstrap() uses it to contruct L2 table metadata.
431 */
432 SLIST_HEAD(, pv_addr) kernel_pt_list = SLIST_HEAD_INITIALIZER(kernel_pt_list);
433
434 static void
435 pmap_init_l1(struct l1_ttable *l1, pd_entry_t *l1pt)
436 {
437 int i;
438
439 l1->l1_kva = l1pt;
440 l1->l1_domain_use_count = 0;
441 l1->l1_domain_first = 0;
442
443 for (i = 0; i < PMAP_DOMAINS; i++)
444 l1->l1_domain_free[i] = i + 1;
445
446 /*
447 * Copy the kernel's L1 entries to each new L1.
448 */
449 if (l1pt != pmap_kernel()->pm_l1->l1_kva)
450 memcpy(l1pt, pmap_kernel()->pm_l1->l1_kva, L1_TABLE_SIZE);
451
452 if ((l1->l1_physaddr = pmap_extract(pmap_kernel(), (vm_offset_t)l1pt)) == 0)
453 panic("pmap_init_l1: can't get PA of L1 at %p", l1pt);
454 SLIST_INSERT_HEAD(&l1_list, l1, l1_link);
455 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
456 }
457
458 static vm_offset_t
459 kernel_pt_lookup(vm_paddr_t pa)
460 {
461 struct pv_addr *pv;
462
463 SLIST_FOREACH(pv, &kernel_pt_list, pv_list) {
464 #ifndef ARM32_NEW_VM_LAYOUT
465 if (pv->pv_pa == (pa & ~PAGE_MASK)) {
466 return (pv->pv_va | (pa & PAGE_MASK));
467 }
468 #else
469 if (pv->pv_pa == pa)
470 return (pv->pv_va);
471 #endif
472 }
473 return (0);
474 }
475
476 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
477 void
478 pmap_pte_init_generic(void)
479 {
480
481 pte_l1_s_cache_mode = L1_S_B|L1_S_C;
482 pte_l1_s_cache_mask = L1_S_CACHE_MASK_generic;
483
484 pte_l2_l_cache_mode = L2_B|L2_C;
485 pte_l2_l_cache_mask = L2_L_CACHE_MASK_generic;
486
487 pte_l2_s_cache_mode = L2_B|L2_C;
488 pte_l2_s_cache_mask = L2_S_CACHE_MASK_generic;
489
490 /*
491 * If we have a write-through cache, set B and C. If
492 * we have a write-back cache, then we assume setting
493 * only C will make those pages write-through.
494 */
495 if (cpufuncs.cf_dcache_wb_range == (void *) cpufunc_nullop) {
496 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
497 pte_l2_l_cache_mode_pt = L2_B|L2_C;
498 pte_l2_s_cache_mode_pt = L2_B|L2_C;
499 } else {
500 pte_l1_s_cache_mode_pt = L1_S_C;
501 pte_l2_l_cache_mode_pt = L2_C;
502 pte_l2_s_cache_mode_pt = L2_C;
503 }
504
505 pte_l2_s_prot_u = L2_S_PROT_U_generic;
506 pte_l2_s_prot_w = L2_S_PROT_W_generic;
507 pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
508
509 pte_l1_s_proto = L1_S_PROTO_generic;
510 pte_l1_c_proto = L1_C_PROTO_generic;
511 pte_l2_s_proto = L2_S_PROTO_generic;
512
513 pmap_copy_page_func = pmap_copy_page_generic;
514 pmap_zero_page_func = pmap_zero_page_generic;
515 }
516
517 #if defined(CPU_ARM8)
518 void
519 pmap_pte_init_arm8(void)
520 {
521
522 /*
523 * ARM8 is compatible with generic, but we need to use
524 * the page tables uncached.
525 */
526 pmap_pte_init_generic();
527
528 pte_l1_s_cache_mode_pt = 0;
529 pte_l2_l_cache_mode_pt = 0;
530 pte_l2_s_cache_mode_pt = 0;
531 }
532 #endif /* CPU_ARM8 */
533
534 #if defined(CPU_ARM9) && defined(ARM9_CACHE_WRITE_THROUGH)
535 void
536 pmap_pte_init_arm9(void)
537 {
538
539 /*
540 * ARM9 is compatible with generic, but we want to use
541 * write-through caching for now.
542 */
543 pmap_pte_init_generic();
544
545 pte_l1_s_cache_mode = L1_S_C;
546 pte_l2_l_cache_mode = L2_C;
547 pte_l2_s_cache_mode = L2_C;
548
549 pte_l1_s_cache_mode_pt = L1_S_C;
550 pte_l2_l_cache_mode_pt = L2_C;
551 pte_l2_s_cache_mode_pt = L2_C;
552 }
553 #endif /* CPU_ARM9 */
554 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
555
556 #if defined(CPU_ARM10)
557 void
558 pmap_pte_init_arm10(void)
559 {
560
561 /*
562 * ARM10 is compatible with generic, but we want to use
563 * write-through caching for now.
564 */
565 pmap_pte_init_generic();
566
567 pte_l1_s_cache_mode = L1_S_B | L1_S_C;
568 pte_l2_l_cache_mode = L2_B | L2_C;
569 pte_l2_s_cache_mode = L2_B | L2_C;
570
571 pte_l1_s_cache_mode_pt = L1_S_C;
572 pte_l2_l_cache_mode_pt = L2_C;
573 pte_l2_s_cache_mode_pt = L2_C;
574
575 }
576 #endif /* CPU_ARM10 */
577
578 #if ARM_MMU_SA1 == 1
579 void
580 pmap_pte_init_sa1(void)
581 {
582
583 /*
584 * The StrongARM SA-1 cache does not have a write-through
585 * mode. So, do the generic initialization, then reset
586 * the page table cache mode to B=1,C=1, and note that
587 * the PTEs need to be sync'd.
588 */
589 pmap_pte_init_generic();
590
591 pte_l1_s_cache_mode_pt = L1_S_B|L1_S_C;
592 pte_l2_l_cache_mode_pt = L2_B|L2_C;
593 pte_l2_s_cache_mode_pt = L2_B|L2_C;
594
595 pmap_needs_pte_sync = 1;
596 }
597 #endif /* ARM_MMU_SA1 == 1*/
598
599 #if ARM_MMU_XSCALE == 1
600 #if (ARM_NMMUS > 1)
601 static u_int xscale_use_minidata;
602 #endif
603
604 void
605 pmap_pte_init_xscale(void)
606 {
607 uint32_t auxctl;
608 int write_through = 0;
609
610 pte_l1_s_cache_mode = L1_S_B|L1_S_C|L1_S_XSCALE_P;
611 pte_l1_s_cache_mask = L1_S_CACHE_MASK_xscale;
612
613 pte_l2_l_cache_mode = L2_B|L2_C;
614 pte_l2_l_cache_mask = L2_L_CACHE_MASK_xscale;
615
616 pte_l2_s_cache_mode = L2_B|L2_C;
617 pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
618
619 pte_l1_s_cache_mode_pt = L1_S_C;
620 pte_l2_l_cache_mode_pt = L2_C;
621 pte_l2_s_cache_mode_pt = L2_C;
622 #ifdef XSCALE_CACHE_READ_WRITE_ALLOCATE
623 /*
624 * The XScale core has an enhanced mode where writes that
625 * miss the cache cause a cache line to be allocated. This
626 * is significantly faster than the traditional, write-through
627 * behavior of this case.
628 */
629 pte_l1_s_cache_mode |= L1_S_XSCALE_TEX(TEX_XSCALE_X);
630 pte_l2_l_cache_mode |= L2_XSCALE_L_TEX(TEX_XSCALE_X);
631 pte_l2_s_cache_mode |= L2_XSCALE_T_TEX(TEX_XSCALE_X);
632 #endif /* XSCALE_CACHE_READ_WRITE_ALLOCATE */
633 #ifdef XSCALE_CACHE_WRITE_THROUGH
634 /*
635 * Some versions of the XScale core have various bugs in
636 * their cache units, the work-around for which is to run
637 * the cache in write-through mode. Unfortunately, this
638 * has a major (negative) impact on performance. So, we
639 * go ahead and run fast-and-loose, in the hopes that we
640 * don't line up the planets in a way that will trip the
641 * bugs.
642 *
643 * However, we give you the option to be slow-but-correct.
644 */
645 write_through = 1;
646 #elif defined(XSCALE_CACHE_WRITE_BACK)
647 /* force write back cache mode */
648 write_through = 0;
649 #elif defined(CPU_XSCALE_PXA2X0)
650 /*
651 * Intel PXA2[15]0 processors are known to have a bug in
652 * write-back cache on revision 4 and earlier (stepping
653 * A[01] and B[012]). Fixed for C0 and later.
654 */
655 {
656 uint32_t id, type;
657
658 id = cpufunc_id();
659 type = id & ~(CPU_ID_XSCALE_COREREV_MASK|CPU_ID_REVISION_MASK);
660
661 if (type == CPU_ID_PXA250 || type == CPU_ID_PXA210) {
662 if ((id & CPU_ID_REVISION_MASK) < 5) {
663 /* write through for stepping A0-1 and B0-2 */
664 write_through = 1;
665 }
666 }
667 }
668 #endif /* XSCALE_CACHE_WRITE_THROUGH */
669
670 if (write_through) {
671 pte_l1_s_cache_mode = L1_S_C;
672 pte_l2_l_cache_mode = L2_C;
673 pte_l2_s_cache_mode = L2_C;
674 }
675
676 #if (ARM_NMMUS > 1)
677 xscale_use_minidata = 1;
678 #endif
679
680 pte_l2_s_prot_u = L2_S_PROT_U_xscale;
681 pte_l2_s_prot_w = L2_S_PROT_W_xscale;
682 pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
683
684 pte_l1_s_proto = L1_S_PROTO_xscale;
685 pte_l1_c_proto = L1_C_PROTO_xscale;
686 pte_l2_s_proto = L2_S_PROTO_xscale;
687
688 pmap_copy_page_func = pmap_copy_page_xscale;
689 pmap_zero_page_func = pmap_zero_page_xscale;
690
691 /*
692 * Disable ECC protection of page table access, for now.
693 */
694 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
695 auxctl &= ~XSCALE_AUXCTL_P;
696 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
697 }
698
699 /*
700 * xscale_setup_minidata:
701 *
702 * Set up the mini-data cache clean area. We require the
703 * caller to allocate the right amount of physically and
704 * virtually contiguous space.
705 */
706 extern vm_offset_t xscale_minidata_clean_addr;
707 extern vm_size_t xscale_minidata_clean_size; /* already initialized */
708 void
709 xscale_setup_minidata(vm_offset_t l1pt, vm_offset_t va, vm_paddr_t pa)
710 {
711 pd_entry_t *pde = (pd_entry_t *) l1pt;
712 pt_entry_t *pte;
713 vm_size_t size;
714 uint32_t auxctl;
715
716 xscale_minidata_clean_addr = va;
717
718 /* Round it to page size. */
719 size = (xscale_minidata_clean_size + L2_S_OFFSET) & L2_S_FRAME;
720
721 for (; size != 0;
722 va += L2_S_SIZE, pa += L2_S_SIZE, size -= L2_S_SIZE) {
723 #ifndef ARM32_NEW_VM_LAYOUT
724 pte = (pt_entry_t *)
725 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
726 #else
727 pte = (pt_entry_t *) kernel_pt_lookup(
728 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
729 #endif
730 if (pte == NULL)
731 panic("xscale_setup_minidata: can't find L2 table for "
732 "VA 0x%08x", (u_int32_t) va);
733 #ifndef ARM32_NEW_VM_LAYOUT
734 pte[(va >> PAGE_SHIFT) & 0x3ff] =
735 #else
736 pte[l2pte_index(va)] =
737 #endif
738 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
739 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X);
740 }
741
742 /*
743 * Configure the mini-data cache for write-back with
744 * read/write-allocate.
745 *
746 * NOTE: In order to reconfigure the mini-data cache, we must
747 * make sure it contains no valid data! In order to do that,
748 * we must issue a global data cache invalidate command!
749 *
750 * WE ASSUME WE ARE RUNNING UN-CACHED WHEN THIS ROUTINE IS CALLED!
751 * THIS IS VERY IMPORTANT!
752 */
753
754 /* Invalidate data and mini-data. */
755 __asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
756 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
757 auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
758 __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
759 }
760 #endif
761
762 /*
763 * Allocate an L1 translation table for the specified pmap.
764 * This is called at pmap creation time.
765 */
766 static void
767 pmap_alloc_l1(pmap_t pm)
768 {
769 struct l1_ttable *l1;
770 u_int8_t domain;
771
772 /*
773 * Remove the L1 at the head of the LRU list
774 */
775 mtx_lock(&l1_lru_lock);
776 l1 = TAILQ_FIRST(&l1_lru_list);
777 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
778
779 /*
780 * Pick the first available domain number, and update
781 * the link to the next number.
782 */
783 domain = l1->l1_domain_first;
784 l1->l1_domain_first = l1->l1_domain_free[domain];
785
786 /*
787 * If there are still free domain numbers in this L1,
788 * put it back on the TAIL of the LRU list.
789 */
790 if (++l1->l1_domain_use_count < PMAP_DOMAINS)
791 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
792
793 mtx_unlock(&l1_lru_lock);
794
795 /*
796 * Fix up the relevant bits in the pmap structure
797 */
798 pm->pm_l1 = l1;
799 pm->pm_domain = domain;
800 }
801
802 /*
803 * Free an L1 translation table.
804 * This is called at pmap destruction time.
805 */
806 static void
807 pmap_free_l1(pmap_t pm)
808 {
809 struct l1_ttable *l1 = pm->pm_l1;
810
811 mtx_lock(&l1_lru_lock);
812
813 /*
814 * If this L1 is currently on the LRU list, remove it.
815 */
816 if (l1->l1_domain_use_count < PMAP_DOMAINS)
817 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
818
819 /*
820 * Free up the domain number which was allocated to the pmap
821 */
822 l1->l1_domain_free[pm->pm_domain] = l1->l1_domain_first;
823 l1->l1_domain_first = pm->pm_domain;
824 l1->l1_domain_use_count--;
825
826 /*
827 * The L1 now must have at least 1 free domain, so add
828 * it back to the LRU list. If the use count is zero,
829 * put it at the head of the list, otherwise it goes
830 * to the tail.
831 */
832 if (l1->l1_domain_use_count == 0) {
833 TAILQ_INSERT_HEAD(&l1_lru_list, l1, l1_lru);
834 } else
835 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
836
837 mtx_unlock(&l1_lru_lock);
838 }
839
840 static PMAP_INLINE void
841 pmap_use_l1(pmap_t pm)
842 {
843 struct l1_ttable *l1;
844
845 /*
846 * Do nothing if we're in interrupt context.
847 * Access to an L1 by the kernel pmap must not affect
848 * the LRU list.
849 */
850 if (pm == pmap_kernel())
851 return;
852
853 l1 = pm->pm_l1;
854
855 /*
856 * If the L1 is not currently on the LRU list, just return
857 */
858 if (l1->l1_domain_use_count == PMAP_DOMAINS)
859 return;
860
861 mtx_lock(&l1_lru_lock);
862
863 /*
864 * Check the use count again, now that we've acquired the lock
865 */
866 if (l1->l1_domain_use_count == PMAP_DOMAINS) {
867 mtx_unlock(&l1_lru_lock);
868 return;
869 }
870
871 /*
872 * Move the L1 to the back of the LRU list
873 */
874 TAILQ_REMOVE(&l1_lru_list, l1, l1_lru);
875 TAILQ_INSERT_TAIL(&l1_lru_list, l1, l1_lru);
876
877 mtx_unlock(&l1_lru_lock);
878 }
879
880
881 /*
882 * Returns a pointer to the L2 bucket associated with the specified pmap
883 * and VA, or NULL if no L2 bucket exists for the address.
884 */
885 static PMAP_INLINE struct l2_bucket *
886 pmap_get_l2_bucket(pmap_t pm, vm_offset_t va)
887 {
888 struct l2_dtable *l2;
889 struct l2_bucket *l2b;
890 u_short l1idx;
891
892 l1idx = L1_IDX(va);
893
894 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL ||
895 (l2b = &l2->l2_bucket[L2_BUCKET(l1idx)])->l2b_kva == NULL)
896 return (NULL);
897
898 return (l2b);
899 }
900
901 /*
902 * Returns a pointer to the L2 bucket associated with the specified pmap
903 * and VA.
904 *
905 * If no L2 bucket exists, perform the necessary allocations to put an L2
906 * bucket/page table in place.
907 *
908 * Note that if a new L2 bucket/page was allocated, the caller *must*
909 * increment the bucket occupancy counter appropriately *before*
910 * releasing the pmap's lock to ensure no other thread or cpu deallocates
911 * the bucket/page in the meantime.
912 */
913 static struct l2_bucket *
914 pmap_alloc_l2_bucket(pmap_t pm, vm_offset_t va)
915 {
916 struct l2_dtable *l2;
917 struct l2_bucket *l2b;
918 u_short l1idx;
919
920 l1idx = L1_IDX(va);
921
922 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
923 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
924 /*
925 * No mapping at this address, as there is
926 * no entry in the L1 table.
927 * Need to allocate a new l2_dtable.
928 */
929 again_l2table:
930 vm_page_unlock_queues();
931 if ((l2 = pmap_alloc_l2_dtable()) == NULL) {
932 vm_page_lock_queues();
933 return (NULL);
934 }
935 vm_page_lock_queues();
936 if (pm->pm_l2[L2_IDX(l1idx)] != NULL) {
937 vm_page_unlock_queues();
938 uma_zfree(l2table_zone, l2);
939 vm_page_lock_queues();
940 l2 = pm->pm_l2[L2_IDX(l1idx)];
941 if (l2 == NULL)
942 goto again_l2table;
943 /*
944 * Someone already allocated the l2_dtable while
945 * we were doing the same.
946 */
947 } else {
948 bzero(l2, sizeof(*l2));
949 /*
950 * Link it into the parent pmap
951 */
952 pm->pm_l2[L2_IDX(l1idx)] = l2;
953 }
954 }
955
956 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
957
958 /*
959 * Fetch pointer to the L2 page table associated with the address.
960 */
961 if (l2b->l2b_kva == NULL) {
962 pt_entry_t *ptep;
963
964 /*
965 * No L2 page table has been allocated. Chances are, this
966 * is because we just allocated the l2_dtable, above.
967 */
968 again_ptep:
969 vm_page_unlock_queues();
970 ptep = (void*)uma_zalloc(l2zone, M_NOWAIT);
971 vm_page_lock_queues();
972 if (l2b->l2b_kva != 0) {
973 /* We lost the race. */
974 vm_page_unlock_queues();
975 uma_zfree(l2zone, ptep);
976 vm_page_lock_queues();
977 if (l2b->l2b_kva == 0)
978 goto again_ptep;
979 return (l2b);
980 }
981 l2b->l2b_phys = vtophys(ptep);
982 if (ptep == NULL) {
983 /*
984 * Oops, no more L2 page tables available at this
985 * time. We may need to deallocate the l2_dtable
986 * if we allocated a new one above.
987 */
988 if (l2->l2_occupancy == 0) {
989 pm->pm_l2[L2_IDX(l1idx)] = NULL;
990 pmap_free_l2_dtable(l2);
991 }
992 return (NULL);
993 }
994
995 l2->l2_occupancy++;
996 l2b->l2b_kva = ptep;
997 l2b->l2b_l1idx = l1idx;
998 }
999
1000 return (l2b);
1001 }
1002
1003 static PMAP_INLINE void
1004 #ifndef PMAP_INCLUDE_PTE_SYNC
1005 pmap_free_l2_ptp(pt_entry_t *l2)
1006 #else
1007 pmap_free_l2_ptp(boolean_t need_sync, pt_entry_t *l2)
1008 #endif
1009 {
1010 #ifdef PMAP_INCLUDE_PTE_SYNC
1011 /*
1012 * Note: With a write-back cache, we may need to sync this
1013 * L2 table before re-using it.
1014 * This is because it may have belonged to a non-current
1015 * pmap, in which case the cache syncs would have been
1016 * skipped when the pages were being unmapped. If the
1017 * L2 table were then to be immediately re-allocated to
1018 * the *current* pmap, it may well contain stale mappings
1019 * which have not yet been cleared by a cache write-back
1020 * and so would still be visible to the mmu.
1021 */
1022 if (need_sync)
1023 PTE_SYNC_RANGE(l2, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1024 #endif
1025 uma_zfree(l2zone, l2);
1026 }
1027 /*
1028 * One or more mappings in the specified L2 descriptor table have just been
1029 * invalidated.
1030 *
1031 * Garbage collect the metadata and descriptor table itself if necessary.
1032 *
1033 * The pmap lock must be acquired when this is called (not necessary
1034 * for the kernel pmap).
1035 */
1036 static void
1037 pmap_free_l2_bucket(pmap_t pm, struct l2_bucket *l2b, u_int count)
1038 {
1039 struct l2_dtable *l2;
1040 pd_entry_t *pl1pd, l1pd;
1041 pt_entry_t *ptep;
1042 u_short l1idx;
1043
1044
1045 /*
1046 * Update the bucket's reference count according to how many
1047 * PTEs the caller has just invalidated.
1048 */
1049 l2b->l2b_occupancy -= count;
1050
1051 /*
1052 * Note:
1053 *
1054 * Level 2 page tables allocated to the kernel pmap are never freed
1055 * as that would require checking all Level 1 page tables and
1056 * removing any references to the Level 2 page table. See also the
1057 * comment elsewhere about never freeing bootstrap L2 descriptors.
1058 *
1059 * We make do with just invalidating the mapping in the L2 table.
1060 *
1061 * This isn't really a big deal in practice and, in fact, leads
1062 * to a performance win over time as we don't need to continually
1063 * alloc/free.
1064 */
1065 if (l2b->l2b_occupancy > 0 || pm == pmap_kernel())
1066 return;
1067
1068 /*
1069 * There are no more valid mappings in this level 2 page table.
1070 * Go ahead and NULL-out the pointer in the bucket, then
1071 * free the page table.
1072 */
1073 l1idx = l2b->l2b_l1idx;
1074 ptep = l2b->l2b_kva;
1075 l2b->l2b_kva = NULL;
1076
1077 pl1pd = &pm->pm_l1->l1_kva[l1idx];
1078
1079 /*
1080 * If the L1 slot matches the pmap's domain
1081 * number, then invalidate it.
1082 */
1083 l1pd = *pl1pd & (L1_TYPE_MASK | L1_C_DOM_MASK);
1084 if (l1pd == (L1_C_DOM(pm->pm_domain) | L1_TYPE_C)) {
1085 *pl1pd = 0;
1086 PTE_SYNC(pl1pd);
1087 }
1088
1089 /*
1090 * Release the L2 descriptor table back to the pool cache.
1091 */
1092 #ifndef PMAP_INCLUDE_PTE_SYNC
1093 pmap_free_l2_ptp(ptep);
1094 #else
1095 pmap_free_l2_ptp(!pmap_is_current(pm), ptep);
1096 #endif
1097
1098 /*
1099 * Update the reference count in the associated l2_dtable
1100 */
1101 l2 = pm->pm_l2[L2_IDX(l1idx)];
1102 if (--l2->l2_occupancy > 0)
1103 return;
1104
1105 /*
1106 * There are no more valid mappings in any of the Level 1
1107 * slots managed by this l2_dtable. Go ahead and NULL-out
1108 * the pointer in the parent pmap and free the l2_dtable.
1109 */
1110 pm->pm_l2[L2_IDX(l1idx)] = NULL;
1111 pmap_free_l2_dtable(l2);
1112 }
1113
1114 /*
1115 * Pool cache constructors for L2 descriptor tables, metadata and pmap
1116 * structures.
1117 */
1118 static int
1119 pmap_l2ptp_ctor(void *mem, int size, void *arg, int flags)
1120 {
1121 #ifndef PMAP_INCLUDE_PTE_SYNC
1122 struct l2_bucket *l2b;
1123 pt_entry_t *ptep, pte;
1124 #ifdef ARM_USE_SMALL_ALLOC
1125 pd_entry_t *pde;
1126 #endif
1127 vm_offset_t va = (vm_offset_t)mem & ~PAGE_MASK;
1128
1129 /*
1130 * The mappings for these page tables were initially made using
1131 * pmap_kenter() by the pool subsystem. Therefore, the cache-
1132 * mode will not be right for page table mappings. To avoid
1133 * polluting the pmap_kenter() code with a special case for
1134 * page tables, we simply fix up the cache-mode here if it's not
1135 * correct.
1136 */
1137 #ifdef ARM_USE_SMALL_ALLOC
1138 pde = &kernel_pmap->pm_l1->l1_kva[L1_IDX(va)];
1139 if (!l1pte_section_p(*pde)) {
1140 #endif
1141 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
1142 ptep = &l2b->l2b_kva[l2pte_index(va)];
1143 pte = *ptep;
1144
1145 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
1146 /*
1147 * Page tables must have the cache-mode set to
1148 * Write-Thru.
1149 */
1150 *ptep = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
1151 PTE_SYNC(ptep);
1152 cpu_tlb_flushD_SE(va);
1153 cpu_cpwait();
1154 }
1155
1156 #ifdef ARM_USE_SMALL_ALLOC
1157 }
1158 #endif
1159 #endif
1160 memset(mem, 0, L2_TABLE_SIZE_REAL);
1161 PTE_SYNC_RANGE(mem, L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
1162 return (0);
1163 }
1164
1165 /*
1166 * A bunch of routines to conditionally flush the caches/TLB depending
1167 * on whether the specified pmap actually needs to be flushed at any
1168 * given time.
1169 */
1170 static PMAP_INLINE void
1171 pmap_tlb_flushID_SE(pmap_t pm, vm_offset_t va)
1172 {
1173
1174 if (pmap_is_current(pm))
1175 cpu_tlb_flushID_SE(va);
1176 }
1177
1178 static PMAP_INLINE void
1179 pmap_tlb_flushD_SE(pmap_t pm, vm_offset_t va)
1180 {
1181
1182 if (pmap_is_current(pm))
1183 cpu_tlb_flushD_SE(va);
1184 }
1185
1186 static PMAP_INLINE void
1187 pmap_tlb_flushID(pmap_t pm)
1188 {
1189
1190 if (pmap_is_current(pm))
1191 cpu_tlb_flushID();
1192 }
1193 static PMAP_INLINE void
1194 pmap_tlb_flushD(pmap_t pm)
1195 {
1196
1197 if (pmap_is_current(pm))
1198 cpu_tlb_flushD();
1199 }
1200
1201 static PMAP_INLINE void
1202 pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len)
1203 {
1204
1205 if (pmap_is_current(pm))
1206 cpu_idcache_wbinv_range(va, len);
1207 }
1208
1209 static PMAP_INLINE void
1210 pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len,
1211 boolean_t do_inv, boolean_t rd_only)
1212 {
1213
1214 if (pmap_is_current(pm)) {
1215 if (do_inv) {
1216 if (rd_only)
1217 cpu_dcache_inv_range(va, len);
1218 else
1219 cpu_dcache_wbinv_range(va, len);
1220 } else
1221 if (!rd_only)
1222 cpu_dcache_wb_range(va, len);
1223 }
1224 }
1225
1226 static PMAP_INLINE void
1227 pmap_idcache_wbinv_all(pmap_t pm)
1228 {
1229
1230 if (pmap_is_current(pm))
1231 cpu_idcache_wbinv_all();
1232 }
1233
1234 static PMAP_INLINE void
1235 pmap_dcache_wbinv_all(pmap_t pm)
1236 {
1237
1238 if (pmap_is_current(pm))
1239 cpu_dcache_wbinv_all();
1240 }
1241
1242 /*
1243 * this routine defines the region(s) of memory that should
1244 * not be tested for the modified bit.
1245 */
1246 static PMAP_INLINE int
1247 pmap_track_modified(vm_offset_t va)
1248 {
1249 if ((va < kmi.clean_sva) || (va >= kmi.clean_eva))
1250 return 1;
1251 else
1252 return 0;
1253 }
1254 /*
1255 * PTE_SYNC_CURRENT:
1256 *
1257 * Make sure the pte is written out to RAM.
1258 * We need to do this for one of two cases:
1259 * - We're dealing with the kernel pmap
1260 * - There is no pmap active in the cache/tlb.
1261 * - The specified pmap is 'active' in the cache/tlb.
1262 */
1263 #ifdef PMAP_INCLUDE_PTE_SYNC
1264 #define PTE_SYNC_CURRENT(pm, ptep) \
1265 do { \
1266 if (PMAP_NEEDS_PTE_SYNC && \
1267 pmap_is_current(pm)) \
1268 PTE_SYNC(ptep); \
1269 } while (/*CONSTCOND*/0)
1270 #else
1271 #define PTE_SYNC_CURRENT(pm, ptep) /* nothing */
1272 #endif
1273
1274 /*
1275 * Since we have a virtually indexed cache, we may need to inhibit caching if
1276 * there is more than one mapping and at least one of them is writable.
1277 * Since we purge the cache on every context switch, we only need to check for
1278 * other mappings within the same pmap, or kernel_pmap.
1279 * This function is also called when a page is unmapped, to possibly reenable
1280 * caching on any remaining mappings.
1281 *
1282 * The code implements the following logic, where:
1283 *
1284 * KW = # of kernel read/write pages
1285 * KR = # of kernel read only pages
1286 * UW = # of user read/write pages
1287 * UR = # of user read only pages
1288 *
1289 * KC = kernel mapping is cacheable
1290 * UC = user mapping is cacheable
1291 *
1292 * KW=0,KR=0 KW=0,KR>0 KW=1,KR=0 KW>1,KR>=0
1293 * +---------------------------------------------
1294 * UW=0,UR=0 | --- KC=1 KC=1 KC=0
1295 * UW=0,UR>0 | UC=1 KC=1,UC=1 KC=0,UC=0 KC=0,UC=0
1296 * UW=1,UR=0 | UC=1 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1297 * UW>1,UR>=0 | UC=0 KC=0,UC=0 KC=0,UC=0 KC=0,UC=0
1298 */
1299
1300 static const int pmap_vac_flags[4][4] = {
1301 {-1, 0, 0, PVF_KNC},
1302 {0, 0, PVF_NC, PVF_NC},
1303 {0, PVF_NC, PVF_NC, PVF_NC},
1304 {PVF_UNC, PVF_NC, PVF_NC, PVF_NC}
1305 };
1306
1307 static PMAP_INLINE int
1308 pmap_get_vac_flags(const struct vm_page *pg)
1309 {
1310 int kidx, uidx;
1311
1312 kidx = 0;
1313 if (pg->md.kro_mappings || pg->md.krw_mappings > 1)
1314 kidx |= 1;
1315 if (pg->md.krw_mappings)
1316 kidx |= 2;
1317
1318 uidx = 0;
1319 if (pg->md.uro_mappings || pg->md.urw_mappings > 1)
1320 uidx |= 1;
1321 if (pg->md.urw_mappings)
1322 uidx |= 2;
1323
1324 return (pmap_vac_flags[uidx][kidx]);
1325 }
1326
1327 static __inline void
1328 pmap_vac_me_harder(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1329 {
1330 int nattr;
1331
1332 nattr = pmap_get_vac_flags(pg);
1333
1334 if (nattr < 0) {
1335 pg->md.pvh_attrs &= ~PVF_NC;
1336 return;
1337 }
1338
1339 if (nattr == 0 && (pg->md.pvh_attrs & PVF_NC) == 0) {
1340 return;
1341 }
1342
1343 if (pm == pmap_kernel())
1344 pmap_vac_me_kpmap(pg, pm, va);
1345 else
1346 pmap_vac_me_user(pg, pm, va);
1347
1348 pg->md.pvh_attrs = (pg->md.pvh_attrs & ~PVF_NC) | nattr;
1349 }
1350
1351 static void
1352 pmap_vac_me_kpmap(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1353 {
1354 u_int u_cacheable, u_entries;
1355 struct pv_entry *pv;
1356 pmap_t last_pmap = pm;
1357
1358 /*
1359 * Pass one, see if there are both kernel and user pmaps for
1360 * this page. Calculate whether there are user-writable or
1361 * kernel-writable pages.
1362 */
1363 u_cacheable = 0;
1364 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1365 if (pv->pv_pmap != pm && (pv->pv_flags & PVF_NC) == 0)
1366 u_cacheable++;
1367 }
1368
1369 u_entries = pg->md.urw_mappings + pg->md.uro_mappings;
1370
1371 /*
1372 * We know we have just been updating a kernel entry, so if
1373 * all user pages are already cacheable, then there is nothing
1374 * further to do.
1375 */
1376 if (pg->md.k_mappings == 0 && u_cacheable == u_entries)
1377 return;
1378
1379 if (u_entries) {
1380 /*
1381 * Scan over the list again, for each entry, if it
1382 * might not be set correctly, call pmap_vac_me_user
1383 * to recalculate the settings.
1384 */
1385 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1386 /*
1387 * We know kernel mappings will get set
1388 * correctly in other calls. We also know
1389 * that if the pmap is the same as last_pmap
1390 * then we've just handled this entry.
1391 */
1392 if (pv->pv_pmap == pm || pv->pv_pmap == last_pmap)
1393 continue;
1394
1395 /*
1396 * If there are kernel entries and this page
1397 * is writable but non-cacheable, then we can
1398 * skip this entry also.
1399 */
1400 if (pg->md.k_mappings &&
1401 (pv->pv_flags & (PVF_NC | PVF_WRITE)) ==
1402 (PVF_NC | PVF_WRITE))
1403 continue;
1404
1405 /*
1406 * Similarly if there are no kernel-writable
1407 * entries and the page is already
1408 * read-only/cacheable.
1409 */
1410 if (pg->md.krw_mappings == 0 &&
1411 (pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0)
1412 continue;
1413
1414 /*
1415 * For some of the remaining cases, we know
1416 * that we must recalculate, but for others we
1417 * can't tell if they are correct or not, so
1418 * we recalculate anyway.
1419 */
1420 pmap_vac_me_user(pg, (last_pmap = pv->pv_pmap), 0);
1421 }
1422
1423 if (pg->md.k_mappings == 0)
1424 return;
1425 }
1426
1427 pmap_vac_me_user(pg, pm, va);
1428 }
1429
1430 static void
1431 pmap_vac_me_user(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1432 {
1433 pmap_t kpmap = pmap_kernel();
1434 struct pv_entry *pv, *npv;
1435 struct l2_bucket *l2b;
1436 pt_entry_t *ptep, pte;
1437 u_int entries = 0;
1438 u_int writable = 0;
1439 u_int cacheable_entries = 0;
1440 u_int kern_cacheable = 0;
1441 u_int other_writable = 0;
1442
1443 /*
1444 * Count mappings and writable mappings in this pmap.
1445 * Include kernel mappings as part of our own.
1446 * Keep a pointer to the first one.
1447 */
1448 npv = TAILQ_FIRST(&pg->md.pv_list);
1449 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1450 /* Count mappings in the same pmap */
1451 if (pm == pv->pv_pmap || kpmap == pv->pv_pmap) {
1452 if (entries++ == 0)
1453 npv = pv;
1454
1455 /* Cacheable mappings */
1456 if ((pv->pv_flags & PVF_NC) == 0) {
1457 cacheable_entries++;
1458 if (kpmap == pv->pv_pmap)
1459 kern_cacheable++;
1460 }
1461
1462 /* Writable mappings */
1463 if (pv->pv_flags & PVF_WRITE)
1464 ++writable;
1465 } else
1466 if (pv->pv_flags & PVF_WRITE)
1467 other_writable = 1;
1468 }
1469
1470 /*
1471 * Enable or disable caching as necessary.
1472 * Note: the first entry might be part of the kernel pmap,
1473 * so we can't assume this is indicative of the state of the
1474 * other (maybe non-kpmap) entries.
1475 */
1476 if ((entries > 1 && writable) ||
1477 (entries > 0 && pm == kpmap && other_writable)) {
1478 if (cacheable_entries == 0)
1479 return;
1480
1481 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1482 if ((pm != pv->pv_pmap && kpmap != pv->pv_pmap) ||
1483 (pv->pv_flags & PVF_NC))
1484 continue;
1485
1486 pv->pv_flags |= PVF_NC;
1487
1488 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1489 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1490 pte = *ptep & ~L2_S_CACHE_MASK;
1491
1492 if ((va != pv->pv_va || pm != pv->pv_pmap) &&
1493 l2pte_valid(pte)) {
1494 if (PV_BEEN_EXECD(pv->pv_flags)) {
1495 pmap_idcache_wbinv_range(pv->pv_pmap,
1496 pv->pv_va, PAGE_SIZE);
1497 pmap_tlb_flushID_SE(pv->pv_pmap,
1498 pv->pv_va);
1499 } else
1500 if (PV_BEEN_REFD(pv->pv_flags)) {
1501 pmap_dcache_wb_range(pv->pv_pmap,
1502 pv->pv_va, PAGE_SIZE, TRUE,
1503 (pv->pv_flags & PVF_WRITE) == 0);
1504 pmap_tlb_flushD_SE(pv->pv_pmap,
1505 pv->pv_va);
1506 }
1507 }
1508
1509 *ptep = pte;
1510 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1511 }
1512 cpu_cpwait();
1513 } else
1514 if (entries > cacheable_entries) {
1515 /*
1516 * Turn cacheing back on for some pages. If it is a kernel
1517 * page, only do so if there are no other writable pages.
1518 */
1519 for (pv = npv; pv; pv = TAILQ_NEXT(pv, pv_list)) {
1520 if (!(pv->pv_flags & PVF_NC) || (pm != pv->pv_pmap &&
1521 (kpmap != pv->pv_pmap || other_writable)))
1522 continue;
1523
1524 pv->pv_flags &= ~PVF_NC;
1525
1526 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
1527 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
1528 pte = (*ptep & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode;
1529
1530 if (l2pte_valid(pte)) {
1531 if (PV_BEEN_EXECD(pv->pv_flags)) {
1532 pmap_tlb_flushID_SE(pv->pv_pmap,
1533 pv->pv_va);
1534 } else
1535 if (PV_BEEN_REFD(pv->pv_flags)) {
1536 pmap_tlb_flushD_SE(pv->pv_pmap,
1537 pv->pv_va);
1538 }
1539 }
1540
1541 *ptep = pte;
1542 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
1543 }
1544 }
1545 }
1546
1547 /*
1548 * Modify pte bits for all ptes corresponding to the given physical address.
1549 * We use `maskbits' rather than `clearbits' because we're always passing
1550 * constants and the latter would require an extra inversion at run-time.
1551 */
1552 static int
1553 pmap_clearbit(struct vm_page *pg, u_int maskbits)
1554 {
1555 struct l2_bucket *l2b;
1556 struct pv_entry *pv;
1557 pt_entry_t *ptep, npte, opte;
1558 pmap_t pm;
1559 vm_offset_t va;
1560 u_int oflags;
1561 int count = 0;
1562 #if 0
1563 PMAP_HEAD_TO_MAP_LOCK();
1564 simple_lock(&pg->mdpage.pvh_slock);
1565 #endif
1566
1567 /*
1568 * Clear saved attributes (modify, reference)
1569 */
1570 pg->md.pvh_attrs &= ~(maskbits & (PVF_MOD | PVF_REF));
1571
1572 if (TAILQ_EMPTY(&pg->md.pv_list)) {
1573 #if 0
1574 simple_unlock(&pg->mdpage.pvh_slock);
1575 PMAP_HEAD_TO_MAP_UNLOCK();
1576 #endif
1577 return (0);
1578 }
1579
1580 /*
1581 * Loop over all current mappings setting/clearing as appropos
1582 */
1583 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list) {
1584 va = pv->pv_va;
1585 pm = pv->pv_pmap;
1586 oflags = pv->pv_flags;
1587 pv->pv_flags &= ~maskbits;
1588
1589 #if 0
1590 pmap_acquire_pmap_lock(pm);
1591 #endif
1592
1593 l2b = pmap_get_l2_bucket(pm, va);
1594
1595 ptep = &l2b->l2b_kva[l2pte_index(va)];
1596 npte = opte = *ptep;
1597
1598 if (maskbits & (PVF_WRITE|PVF_MOD) &&
1599 !pmap_track_modified(pv->pv_va)) {
1600 if ((pv->pv_flags & PVF_NC)) {
1601 /*
1602 * Entry is not cacheable:
1603 *
1604 * Don't turn caching on again if this is a
1605 * modified emulation. This would be
1606 * inconsitent with the settings created by
1607 * pmap_vac_me_harder(). Otherwise, it's safe
1608 * to re-enable cacheing.
1609 *
1610 * There's no need to call pmap_vac_me_harder()
1611 * here: all pages are losing their write
1612 * permission.
1613 */
1614 if (maskbits & PVF_WRITE) {
1615 npte |= pte_l2_s_cache_mode;
1616 pv->pv_flags &= ~PVF_NC;
1617 }
1618 } else
1619 if (opte & L2_S_PROT_W) {
1620 vm_page_dirty(pg);
1621 /*
1622 * Entry is writable/cacheable: check if pmap
1623 * is current if it is flush it, otherwise it
1624 * won't be in the cache
1625 */
1626 if (PV_BEEN_EXECD(oflags))
1627 pmap_idcache_wbinv_range(pm, pv->pv_va,
1628 PAGE_SIZE);
1629 else
1630 if (PV_BEEN_REFD(oflags))
1631 pmap_dcache_wb_range(pm, pv->pv_va,
1632 PAGE_SIZE,
1633 (maskbits & PVF_REF) ? TRUE : FALSE,
1634 FALSE);
1635 }
1636
1637 /* make the pte read only */
1638 npte &= ~L2_S_PROT_W;
1639
1640 if (maskbits & PVF_WRITE) {
1641 /*
1642 * Keep alias accounting up to date
1643 */
1644 if (pv->pv_pmap == pmap_kernel()) {
1645 if (oflags & PVF_WRITE) {
1646 pg->md.krw_mappings--;
1647 pg->md.kro_mappings++;
1648 }
1649 } else
1650 if (oflags & PVF_WRITE) {
1651 pg->md.urw_mappings--;
1652 pg->md.uro_mappings++;
1653 }
1654 }
1655 }
1656
1657 if (maskbits & PVF_REF && !pmap_track_modified(pv->pv_va)) {
1658 if ((pv->pv_flags & PVF_NC) == 0 &&
1659 (maskbits & (PVF_WRITE|PVF_MOD)) == 0) {
1660 /*
1661 * Check npte here; we may have already
1662 * done the wbinv above, and the validity
1663 * of the PTE is the same for opte and
1664 * npte.
1665 */
1666 if (npte & L2_S_PROT_W) {
1667 if (PV_BEEN_EXECD(oflags))
1668 pmap_idcache_wbinv_range(pm,
1669 pv->pv_va, PAGE_SIZE);
1670 else
1671 if (PV_BEEN_REFD(oflags))
1672 pmap_dcache_wb_range(pm,
1673 pv->pv_va, PAGE_SIZE,
1674 TRUE, FALSE);
1675 } else
1676 if ((npte & L2_TYPE_MASK) != L2_TYPE_INV) {
1677 /* XXXJRT need idcache_inv_range */
1678 if (PV_BEEN_EXECD(oflags))
1679 pmap_idcache_wbinv_range(pm,
1680 pv->pv_va, PAGE_SIZE);
1681 else
1682 if (PV_BEEN_REFD(oflags))
1683 pmap_dcache_wb_range(pm,
1684 pv->pv_va, PAGE_SIZE,
1685 TRUE, TRUE);
1686 }
1687 }
1688
1689 /*
1690 * Make the PTE invalid so that we will take a
1691 * page fault the next time the mapping is
1692 * referenced.
1693 */
1694 npte &= ~L2_TYPE_MASK;
1695 npte |= L2_TYPE_INV;
1696 }
1697
1698 if (npte != opte) {
1699 count++;
1700 *ptep = npte;
1701 PTE_SYNC(ptep);
1702 /* Flush the TLB entry if a current pmap. */
1703 if (PV_BEEN_EXECD(oflags))
1704 pmap_tlb_flushID_SE(pm, pv->pv_va);
1705 else
1706 if (PV_BEEN_REFD(oflags))
1707 pmap_tlb_flushD_SE(pm, pv->pv_va);
1708 }
1709
1710 #if 0
1711 pmap_release_pmap_lock(pm);
1712 #endif
1713
1714 }
1715
1716 #if 0
1717 simple_unlock(&pg->mdpage.pvh_slock);
1718 PMAP_HEAD_TO_MAP_UNLOCK();
1719 #endif
1720 if (maskbits & PVF_WRITE)
1721 vm_page_flag_clear(pg, PG_WRITEABLE);
1722 return (count);
1723 }
1724
1725 /*
1726 * main pv_entry manipulation functions:
1727 * pmap_enter_pv: enter a mapping onto a vm_page list
1728 * pmap_remove_pv: remove a mappiing from a vm_page list
1729 *
1730 * NOTE: pmap_enter_pv expects to lock the pvh itself
1731 * pmap_remove_pv expects te caller to lock the pvh before calling
1732 */
1733
1734 /*
1735 * pmap_enter_pv: enter a mapping onto a vm_page lst
1736 *
1737 * => caller should hold the proper lock on pmap_main_lock
1738 * => caller should have pmap locked
1739 * => we will gain the lock on the vm_page and allocate the new pv_entry
1740 * => caller should adjust ptp's wire_count before calling
1741 * => caller should not adjust pmap's wire_count
1742 */
1743 static void
1744 pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, pmap_t pm,
1745 vm_offset_t va, u_int flags)
1746 {
1747
1748
1749 pve->pv_pmap = pm;
1750 pve->pv_va = va;
1751 pve->pv_flags = flags;
1752
1753 #if 0
1754 mtx_lock(&pg->md.pvh_mtx);
1755 #endif
1756 TAILQ_INSERT_HEAD(&pg->md.pv_list, pve, pv_list);
1757 TAILQ_INSERT_HEAD(&pm->pm_pvlist, pve, pv_plist);
1758 pg->md.pvh_attrs |= flags & (PVF_REF | PVF_MOD);
1759 if (pm == pmap_kernel()) {
1760 if (flags & PVF_WRITE)
1761 pg->md.krw_mappings++;
1762 else
1763 pg->md.kro_mappings++;
1764 }
1765 if (flags & PVF_WRITE)
1766 pg->md.urw_mappings++;
1767 else
1768 pg->md.uro_mappings++;
1769 pg->md.pv_list_count++;
1770 #if 0
1771 mtx_unlock(&pg->md.pvh_mtx);
1772 #endif
1773 if (pve->pv_flags & PVF_WIRED)
1774 ++pm->pm_stats.wired_count;
1775 vm_page_flag_set(pg, PG_REFERENCED);
1776 }
1777
1778 /*
1779 *
1780 * pmap_find_pv: Find a pv entry
1781 *
1782 * => caller should hold lock on vm_page
1783 */
1784 static PMAP_INLINE struct pv_entry *
1785 pmap_find_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1786 {
1787 struct pv_entry *pv;
1788
1789 TAILQ_FOREACH(pv, &pg->md.pv_list, pv_list)
1790 if (pm == pv->pv_pmap && va == pv->pv_va)
1791 break;
1792 return (pv);
1793 }
1794
1795 /*
1796 * vector_page_setprot:
1797 *
1798 * Manipulate the protection of the vector page.
1799 */
1800 void
1801 vector_page_setprot(int prot)
1802 {
1803 struct l2_bucket *l2b;
1804 pt_entry_t *ptep;
1805
1806 l2b = pmap_get_l2_bucket(pmap_kernel(), vector_page);
1807
1808 ptep = &l2b->l2b_kva[l2pte_index(vector_page)];
1809
1810 *ptep = (*ptep & ~L1_S_PROT_MASK) | L2_S_PROT(PTE_KERNEL, prot);
1811 PTE_SYNC(ptep);
1812 cpu_tlb_flushD_SE(vector_page);
1813 cpu_cpwait();
1814 }
1815
1816 /*
1817 * pmap_remove_pv: try to remove a mapping from a pv_list
1818 *
1819 * => caller should hold proper lock on pmap_main_lock
1820 * => pmap should be locked
1821 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1822 * => caller should adjust ptp's wire_count and free PTP if needed
1823 * => caller should NOT adjust pmap's wire_count
1824 * => we return the removed pve
1825 */
1826
1827 static void
1828 pmap_nuke_pv(struct vm_page *pg, pmap_t pm, struct pv_entry *pve)
1829 {
1830
1831 TAILQ_REMOVE(&pg->md.pv_list, pve, pv_list);
1832 TAILQ_REMOVE(&pm->pm_pvlist, pve, pv_plist);
1833 if (pve->pv_flags & PVF_WIRED)
1834 --pm->pm_stats.wired_count;
1835 pg->md.pv_list_count--;
1836 if (pg->md.pvh_attrs & PVF_MOD)
1837 vm_page_dirty(pg);
1838 if (pm == pmap_kernel()) {
1839 if (pve->pv_flags & PVF_WRITE)
1840 pg->md.krw_mappings--;
1841 else
1842 pg->md.kro_mappings--;
1843 } else
1844 if (pve->pv_flags & PVF_WRITE)
1845 pg->md.urw_mappings--;
1846 else
1847 pg->md.uro_mappings--;
1848 if (TAILQ_FIRST(&pg->md.pv_list) == NULL ||
1849 (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0)) {
1850 pg->md.pvh_attrs &= ~PVF_MOD;
1851 if (TAILQ_FIRST(&pg->md.pv_list) == NULL)
1852 pg->md.pvh_attrs &= ~PVF_REF;
1853 vm_page_flag_clear(pg, PG_WRITEABLE);
1854 }
1855 if (TAILQ_FIRST(&pg->md.pv_list))
1856 vm_page_flag_set(pg, PG_REFERENCED);
1857 if (pve->pv_flags & PVF_WRITE)
1858 pmap_vac_me_harder(pg, pm, 0);
1859 }
1860
1861 static struct pv_entry *
1862 pmap_remove_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va)
1863 {
1864 struct pv_entry *pve;
1865
1866 pve = TAILQ_FIRST(&pg->md.pv_list);
1867
1868 while (pve) {
1869 if (pve->pv_pmap == pm && pve->pv_va == va) { /* match? */
1870 pmap_nuke_pv(pg, pm, pve);
1871 break;
1872 }
1873 pve = TAILQ_NEXT(pve, pv_list);
1874 }
1875
1876 return(pve); /* return removed pve */
1877 }
1878 /*
1879 *
1880 * pmap_modify_pv: Update pv flags
1881 *
1882 * => caller should hold lock on vm_page [so that attrs can be adjusted]
1883 * => caller should NOT adjust pmap's wire_count
1884 * => caller must call pmap_vac_me_harder() if writable status of a page
1885 * may have changed.
1886 * => we return the old flags
1887 *
1888 * Modify a physical-virtual mapping in the pv table
1889 */
1890 static u_int
1891 pmap_modify_pv(struct vm_page *pg, pmap_t pm, vm_offset_t va,
1892 u_int clr_mask, u_int set_mask)
1893 {
1894 struct pv_entry *npv;
1895 u_int flags, oflags;
1896
1897 if ((npv = pmap_find_pv(pg, pm, va)) == NULL)
1898 return (0);
1899
1900 /*
1901 * There is at least one VA mapping this page.
1902 */
1903
1904 if (clr_mask & (PVF_REF | PVF_MOD))
1905 pg->md.pvh_attrs |= set_mask & (PVF_REF | PVF_MOD);
1906
1907 oflags = npv->pv_flags;
1908 npv->pv_flags = flags = (oflags & ~clr_mask) | set_mask;
1909
1910 if ((flags ^ oflags) & PVF_WIRED) {
1911 if (flags & PVF_WIRED)
1912 ++pm->pm_stats.wired_count;
1913 else
1914 --pm->pm_stats.wired_count;
1915 }
1916
1917 if ((flags ^ oflags) & PVF_WRITE) {
1918 if (pm == pmap_kernel()) {
1919 if (flags & PVF_WRITE) {
1920 pg->md.krw_mappings++;
1921 pg->md.kro_mappings--;
1922 } else {
1923 pg->md.kro_mappings++;
1924 pg->md.krw_mappings--;
1925 }
1926 } else
1927 if (flags & PVF_WRITE) {
1928 pg->md.urw_mappings++;
1929 pg->md.uro_mappings--;
1930 } else {
1931 pg->md.uro_mappings++;
1932 pg->md.urw_mappings--;
1933 }
1934 if (pg->md.krw_mappings == 0 && pg->md.urw_mappings == 0) {
1935 pg->md.pvh_attrs &= ~PVF_MOD;
1936 vm_page_flag_clear(pg, PG_WRITEABLE);
1937 }
1938 pmap_vac_me_harder(pg, pm, 0);
1939 }
1940
1941 return (oflags);
1942 }
1943
1944 /* Function to set the debug level of the pmap code */
1945 #ifdef PMAP_DEBUG
1946 void
1947 pmap_debug(int level)
1948 {
1949 pmap_debug_level = level;
1950 dprintf("pmap_debug: level=%d\n", pmap_debug_level);
1951 }
1952 #endif /* PMAP_DEBUG */
1953
1954 void
1955 pmap_pinit0(struct pmap *pmap)
1956 {
1957 PDEBUG(1, printf("pmap_pinit0: pmap = %08x\n", (u_int32_t) pmap));
1958
1959 dprintf("pmap_pinit0: pmap = %08x, pm_pdir = %08x\n",
1960 (u_int32_t) pmap, (u_int32_t) pmap->pm_pdir);
1961 bcopy(kernel_pmap, pmap, sizeof(*pmap));
1962 }
1963
1964 /*
1965 * Initialize a vm_page's machine-dependent fields.
1966 */
1967 void
1968 pmap_page_init(vm_page_t m)
1969 {
1970
1971 TAILQ_INIT(&m->md.pv_list);
1972 m->md.pv_list_count = 0;
1973 }
1974
1975 /*
1976 * Initialize the pmap module.
1977 * Called by vm_init, to initialize any structures that the pmap
1978 * system needs to map virtual memory.
1979 */
1980 void
1981 pmap_init(void)
1982 {
1983
1984 PDEBUG(1, printf("pmap_init: phys_start = %08x\n"));
1985
1986 /*
1987 * init the pv free list
1988 */
1989 pvzone = uma_zcreate("PV ENTRY", sizeof (struct pv_entry), NULL, NULL,
1990 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1991 uma_prealloc(pvzone, MINPV);
1992 /*
1993 * Now it is safe to enable pv_table recording.
1994 */
1995 PDEBUG(1, printf("pmap_init: done!\n"));
1996
1997 }
1998
1999 int
2000 pmap_fault_fixup(pmap_t pm, vm_offset_t va, vm_prot_t ftype, int user)
2001 {
2002 struct l2_dtable *l2;
2003 struct l2_bucket *l2b;
2004 pd_entry_t *pl1pd, l1pd;
2005 pt_entry_t *ptep, pte;
2006 vm_paddr_t pa;
2007 u_int l1idx;
2008 int rv = 0;
2009
2010 #if 0
2011 PMAP_MAP_TO_HEAD_LOCK();
2012 pmap_acquire_pmap_lock(pm);
2013 #endif
2014 l1idx = L1_IDX(va);
2015
2016 /*
2017 * If there is no l2_dtable for this address, then the process
2018 * has no business accessing it.
2019 *
2020 * Note: This will catch userland processes trying to access
2021 * kernel addresses.
2022 */
2023 l2 = pm->pm_l2[L2_IDX(l1idx)];
2024 if (l2 == NULL)
2025 goto out;
2026
2027 /*
2028 * Likewise if there is no L2 descriptor table
2029 */
2030 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2031 if (l2b->l2b_kva == NULL)
2032 goto out;
2033
2034 /*
2035 * Check the PTE itself.
2036 */
2037 ptep = &l2b->l2b_kva[l2pte_index(va)];
2038 pte = *ptep;
2039 if (pte == 0)
2040 goto out;
2041
2042 /*
2043 * Catch a userland access to the vector page mapped at 0x0
2044 */
2045 if (user && (pte & L2_S_PROT_U) == 0)
2046 goto out;
2047 if (va == vector_page)
2048 goto out;
2049
2050 pa = l2pte_pa(pte);
2051
2052 if ((ftype & VM_PROT_WRITE) && (pte & L2_S_PROT_W) == 0) {
2053 /*
2054 * This looks like a good candidate for "page modified"
2055 * emulation...
2056 */
2057 struct pv_entry *pv;
2058 struct vm_page *pg;
2059
2060 /* Extract the physical address of the page */
2061 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2062 goto out;
2063 }
2064 /* Get the current flags for this page. */
2065
2066 pv = pmap_find_pv(pg, pm, va);
2067 if (pv == NULL) {
2068 goto out;
2069 }
2070
2071 /*
2072 * Do the flags say this page is writable? If not then it
2073 * is a genuine write fault. If yes then the write fault is
2074 * our fault as we did not reflect the write access in the
2075 * PTE. Now we know a write has occurred we can correct this
2076 * and also set the modified bit
2077 */
2078 if ((pv->pv_flags & PVF_WRITE) == 0) {
2079 goto out;
2080 }
2081
2082 if (pmap_track_modified(pv->pv_va)) {
2083 pg->md.pvh_attrs |= PVF_REF | PVF_MOD;
2084 vm_page_dirty(pg);
2085 }
2086 pv->pv_flags |= PVF_REF | PVF_MOD;
2087
2088 /*
2089 * Re-enable write permissions for the page. No need to call
2090 * pmap_vac_me_harder(), since this is just a
2091 * modified-emulation fault, and the PVF_WRITE bit isn't
2092 * changing. We've already set the cacheable bits based on
2093 * the assumption that we can write to this page.
2094 */
2095 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO | L2_S_PROT_W;
2096 PTE_SYNC(ptep);
2097 rv = 1;
2098 } else
2099 if ((pte & L2_TYPE_MASK) == L2_TYPE_INV) {
2100 /*
2101 * This looks like a good candidate for "page referenced"
2102 * emulation.
2103 */
2104 struct pv_entry *pv;
2105 struct vm_page *pg;
2106
2107 /* Extract the physical address of the page */
2108 vm_page_lock_queues();
2109 if ((pg = PHYS_TO_VM_PAGE(pa)) == NULL) {
2110 vm_page_unlock_queues();
2111 goto out;
2112 }
2113 /* Get the current flags for this page. */
2114
2115 pv = pmap_find_pv(pg, pm, va);
2116 if (pv == NULL) {
2117 vm_page_unlock_queues();
2118 goto out;
2119 }
2120
2121 pg->md.pvh_attrs |= PVF_REF;
2122 pv->pv_flags |= PVF_REF;
2123
2124
2125 *ptep = (pte & ~L2_TYPE_MASK) | L2_S_PROTO;
2126 PTE_SYNC(ptep);
2127 rv = 1;
2128 vm_page_unlock_queues();
2129 }
2130
2131 /*
2132 * We know there is a valid mapping here, so simply
2133 * fix up the L1 if necessary.
2134 */
2135 pl1pd = &pm->pm_l1->l1_kva[l1idx];
2136 l1pd = l2b->l2b_phys | L1_C_DOM(pm->pm_domain) | L1_C_PROTO;
2137 if (*pl1pd != l1pd) {
2138 *pl1pd = l1pd;
2139 PTE_SYNC(pl1pd);
2140 rv = 1;
2141 }
2142
2143 #ifdef CPU_SA110
2144 /*
2145 * There are bugs in the rev K SA110. This is a check for one
2146 * of them.
2147 */
2148 if (rv == 0 && curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
2149 curcpu()->ci_arm_cpurev < 3) {
2150 /* Always current pmap */
2151 if (l2pte_valid(pte)) {
2152 extern int kernel_debug;
2153 if (kernel_debug & 1) {
2154 struct proc *p = curlwp->l_proc;
2155 printf("prefetch_abort: page is already "
2156 "mapped - pte=%p *pte=%08x\n", ptep, pte);
2157 printf("prefetch_abort: pc=%08lx proc=%p "
2158 "process=%s\n", va, p, p->p_comm);
2159 printf("prefetch_abort: far=%08x fs=%x\n",
2160 cpu_faultaddress(), cpu_faultstatus());
2161 }
2162 #ifdef DDB
2163 if (kernel_debug & 2)
2164 Debugger();
2165 #endif
2166 rv = 1;
2167 }
2168 }
2169 #endif /* CPU_SA110 */
2170
2171 #ifdef DEBUG
2172 /*
2173 * If 'rv == 0' at this point, it generally indicates that there is a
2174 * stale TLB entry for the faulting address. This happens when two or
2175 * more processes are sharing an L1. Since we don't flush the TLB on
2176 * a context switch between such processes, we can take domain faults
2177 * for mappings which exist at the same VA in both processes. EVEN IF
2178 * WE'VE RECENTLY FIXED UP THE CORRESPONDING L1 in pmap_enter(), for
2179 * example.
2180 *
2181 * This is extremely likely to happen if pmap_enter() updated the L1
2182 * entry for a recently entered mapping. In this case, the TLB is
2183 * flushed for the new mapping, but there may still be TLB entries for
2184 * other mappings belonging to other processes in the 1MB range
2185 * covered by the L1 entry.
2186 *
2187 * Since 'rv == 0', we know that the L1 already contains the correct
2188 * value, so the fault must be due to a stale TLB entry.
2189 *
2190 * Since we always need to flush the TLB anyway in the case where we
2191 * fixed up the L1, or frobbed the L2 PTE, we effectively deal with
2192 * stale TLB entries dynamically.
2193 *
2194 * However, the above condition can ONLY happen if the current L1 is
2195 * being shared. If it happens when the L1 is unshared, it indicates
2196 * that other parts of the pmap are not doing their job WRT managing
2197 * the TLB.
2198 */
2199 if (rv == 0 && pm->pm_l1->l1_domain_use_count == 1) {
2200 extern int last_fault_code;
2201 printf("fixup: pm %p, va 0x%lx, ftype %d - nothing to do!\n",
2202 pm, va, ftype);
2203 printf("fixup: l2 %p, l2b %p, ptep %p, pl1pd %p\n",
2204 l2, l2b, ptep, pl1pd);
2205 printf("fixup: pte 0x%x, l1pd 0x%x, last code 0x%x\n",
2206 pte, l1pd, last_fault_code);
2207 #ifdef DDB
2208 Debugger();
2209 #endif
2210 }
2211 #endif
2212
2213 cpu_tlb_flushID_SE(va);
2214 cpu_cpwait();
2215
2216 rv = 1;
2217
2218 out:
2219 #if 0
2220 pmap_release_pmap_lock(pm);
2221 PMAP_MAP_TO_HEAD_UNLOCK();
2222 #endif
2223 return (rv);
2224 }
2225
2226 /*
2227 * Initialize the address space (zone) for the pv_entries. Set a
2228 * high water mark so that the system can recover from excessive
2229 * numbers of pv entries.
2230 */
2231 void
2232 pmap_init2()
2233 {
2234 int shpgperproc = PMAP_SHPGPERPROC;
2235 struct l2_bucket *l2b;
2236 struct l1_ttable *l1;
2237 pd_entry_t *pl1pt;
2238 pt_entry_t *ptep, pte;
2239 vm_offset_t va, eva;
2240 u_int loop, needed;
2241
2242 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
2243
2244 pv_entry_max = shpgperproc * maxproc + vm_page_array_size;
2245 pv_entry_high_water = 9 * (pv_entry_max / 10);
2246 l2zone = uma_zcreate("L2 Table", L2_TABLE_SIZE_REAL, pmap_l2ptp_ctor,
2247 NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
2248 uma_prealloc(l2zone, 4096);
2249 l2table_zone = uma_zcreate("L2 Table", sizeof(struct l2_dtable),
2250 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
2251 UMA_ZONE_VM | UMA_ZONE_NOFREE);
2252 uma_prealloc(l2table_zone, 1024);
2253
2254 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
2255 uma_zone_set_obj(l2zone, &l2zone_obj, pv_entry_max);
2256
2257 needed = (maxproc / PMAP_DOMAINS) + ((maxproc % PMAP_DOMAINS) ? 1 : 0);
2258 needed -= 1;
2259 l1 = malloc(sizeof(*l1) * needed, M_VMPMAP, M_WAITOK);
2260
2261 for (loop = 0; loop < needed; loop++, l1++) {
2262 /* Allocate a L1 page table */
2263 va = (vm_offset_t)contigmalloc(L1_TABLE_SIZE, M_VMPMAP, 0, 0x0,
2264 0xffffffff, L1_TABLE_SIZE, 0);
2265
2266 if (va == 0)
2267 panic("Cannot allocate L1 KVM");
2268
2269 eva = va + L1_TABLE_SIZE;
2270 pl1pt = (pd_entry_t *)va;
2271
2272 while (va < eva) {
2273 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2274 ptep = &l2b->l2b_kva[l2pte_index(va)];
2275 pte = *ptep;
2276 pte = (pte & ~L2_S_CACHE_MASK) | pte_l2_s_cache_mode_pt;
2277 *ptep = pte;
2278 PTE_SYNC(ptep);
2279 cpu_tlb_flushD_SE(va);
2280
2281 va += PAGE_SIZE;
2282 }
2283 pmap_init_l1(l1, pl1pt);
2284 }
2285
2286
2287 #ifdef DEBUG
2288 printf("pmap_postinit: Allocated %d static L1 descriptor tables\n",
2289 needed);
2290 #endif
2291 }
2292
2293 /*
2294 * This is used to stuff certain critical values into the PCB where they
2295 * can be accessed quickly from cpu_switch() et al.
2296 */
2297 void
2298 pmap_set_pcb_pagedir(pmap_t pm, struct pcb *pcb)
2299 {
2300 struct l2_bucket *l2b;
2301
2302 pcb->pcb_pagedir = pm->pm_l1->l1_physaddr;
2303 pcb->pcb_dacr = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) |
2304 (DOMAIN_CLIENT << (pm->pm_domain * 2));
2305
2306 if (vector_page < KERNBASE) {
2307 pcb->pcb_pl1vec = &pm->pm_l1->l1_kva[L1_IDX(vector_page)];
2308 l2b = pmap_get_l2_bucket(pm, vector_page);
2309 pcb->pcb_l1vec = l2b->l2b_phys | L1_C_PROTO |
2310 L1_C_DOM(pm->pm_domain) | L1_C_DOM(PMAP_DOMAIN_KERNEL);
2311 } else
2312 pcb->pcb_pl1vec = NULL;
2313 }
2314
2315 void
2316 pmap_activate(struct thread *td)
2317 {
2318 pmap_t pm;
2319 struct pcb *pcb;
2320 int s;
2321
2322 pm = vmspace_pmap(td->td_proc->p_vmspace);
2323 pcb = td->td_pcb;
2324
2325 critical_enter();
2326 pmap_set_pcb_pagedir(pm, pcb);
2327
2328 if (td == curthread) {
2329 u_int cur_dacr, cur_ttb;
2330
2331 __asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
2332 __asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
2333
2334 cur_ttb &= ~(L1_TABLE_SIZE - 1);
2335
2336 if (cur_ttb == (u_int)pcb->pcb_pagedir &&
2337 cur_dacr == pcb->pcb_dacr) {
2338 /*
2339 * No need to switch address spaces.
2340 */
2341 critical_exit();
2342 return;
2343 }
2344
2345
2346 /*
2347 * We MUST, I repeat, MUST fix up the L1 entry corresponding
2348 * to 'vector_page' in the incoming L1 table before switching
2349 * to it otherwise subsequent interrupts/exceptions (including
2350 * domain faults!) will jump into hyperspace.
2351 */
2352 if (pcb->pcb_pl1vec) {
2353
2354 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2355 /*
2356 * Don't need to PTE_SYNC() at this point since
2357 * cpu_setttb() is about to flush both the cache
2358 * and the TLB.
2359 */
2360 }
2361
2362 cpu_domains(pcb->pcb_dacr);
2363 cpu_setttb(pcb->pcb_pagedir);
2364
2365 splx(s);
2366 }
2367 critical_exit();
2368 }
2369
2370 static int
2371 pmap_set_pt_cache_mode(pd_entry_t *kl1, vm_offset_t va)
2372 {
2373 pd_entry_t *pdep, pde;
2374 pt_entry_t *ptep, pte;
2375 vm_offset_t pa;
2376 int rv = 0;
2377
2378 /*
2379 * Make sure the descriptor itself has the correct cache mode
2380 */
2381 pdep = &kl1[L1_IDX(va)];
2382 pde = *pdep;
2383
2384 if (l1pte_section_p(pde)) {
2385 if ((pde & L1_S_CACHE_MASK) != pte_l1_s_cache_mode_pt) {
2386 *pdep = (pde & ~L1_S_CACHE_MASK) |
2387 pte_l1_s_cache_mode_pt;
2388 PTE_SYNC(pdep);
2389 cpu_dcache_wbinv_range((vm_offset_t)pdep,
2390 sizeof(*pdep));
2391 rv = 1;
2392 }
2393 } else {
2394 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2395 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2396 if (ptep == NULL)
2397 panic("pmap_bootstrap: No L2 for L2 @ va %p\n", ptep);
2398
2399 ptep = &ptep[l2pte_index(va)];
2400 pte = *ptep;
2401 if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
2402 *ptep = (pte & ~L2_S_CACHE_MASK) |
2403 pte_l2_s_cache_mode_pt;
2404 PTE_SYNC(ptep);
2405 cpu_dcache_wbinv_range((vm_offset_t)ptep,
2406 sizeof(*ptep));
2407 rv = 1;
2408 }
2409 }
2410
2411 return (rv);
2412 }
2413
2414 static void
2415 pmap_alloc_specials(vm_offset_t *availp, int pages, vm_offset_t *vap,
2416 pt_entry_t **ptep)
2417 {
2418 vm_offset_t va = *availp;
2419 struct l2_bucket *l2b;
2420
2421 if (ptep) {
2422 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2423 if (l2b == NULL)
2424 panic("pmap_alloc_specials: no l2b for 0x%x", va);
2425
2426 *ptep = &l2b->l2b_kva[l2pte_index(va)];
2427 }
2428
2429 *vap = va;
2430 *availp = va + (PAGE_SIZE * pages);
2431 }
2432
2433 /*
2434 * Bootstrap the system enough to run with virtual memory.
2435 *
2436 * On the arm this is called after mapping has already been enabled
2437 * and just syncs the pmap module with what has already been done.
2438 * [We can't call it easily with mapping off since the kernel is not
2439 * mapped with PA == VA, hence we would have to relocate every address
2440 * from the linked base (virtual) address "KERNBASE" to the actual
2441 * (physical) address starting relative to 0]
2442 */
2443 #define PMAP_STATIC_L2_SIZE 16
2444 #ifdef ARM_USE_SMALL_ALLOC
2445 extern struct mtx smallalloc_mtx;
2446 extern vm_offset_t alloc_curaddr;
2447 extern vm_offset_t alloc_firstaddr;
2448 #endif
2449
2450 void
2451 pmap_bootstrap(vm_offset_t firstaddr, vm_offset_t lastaddr, struct pv_addr *l1pt)
2452 {
2453 static struct l1_ttable static_l1;
2454 static struct l2_dtable static_l2[PMAP_STATIC_L2_SIZE];
2455 struct l1_ttable *l1 = &static_l1;
2456 struct l2_dtable *l2;
2457 struct l2_bucket *l2b;
2458 pd_entry_t pde;
2459 pd_entry_t *kernel_l1pt = (pd_entry_t *)l1pt->pv_va;
2460 pt_entry_t *ptep;
2461 vm_paddr_t pa;
2462 vm_offset_t va;
2463 vm_size_t size;
2464 int l1idx, l2idx, l2next = 0;
2465
2466 PDEBUG(1, printf("firstaddr = %08x, loadaddr = %08x\n",
2467 firstaddr, loadaddr));
2468
2469 virtual_avail = firstaddr;
2470 kernel_pmap = &kernel_pmap_store;
2471 kernel_pmap->pm_l1 = l1;
2472
2473 /*
2474 * Scan the L1 translation table created by initarm() and create
2475 * the required metadata for all valid mappings found in it.
2476 */
2477 for (l1idx = 0; l1idx < (L1_TABLE_SIZE / sizeof(pd_entry_t)); l1idx++) {
2478 pde = kernel_l1pt[l1idx];
2479
2480 /*
2481 * We're only interested in Coarse mappings.
2482 * pmap_extract() can deal with section mappings without
2483 * recourse to checking L2 metadata.
2484 */
2485 if ((pde & L1_TYPE_MASK) != L1_TYPE_C)
2486 continue;
2487
2488 /*
2489 * Lookup the KVA of this L2 descriptor table
2490 */
2491 pa = (vm_paddr_t)(pde & L1_C_ADDR_MASK);
2492 ptep = (pt_entry_t *)kernel_pt_lookup(pa);
2493
2494 if (ptep == NULL) {
2495 panic("pmap_bootstrap: No L2 for va 0x%x, pa 0x%lx",
2496 (u_int)l1idx << L1_S_SHIFT, (long unsigned int)pa);
2497 }
2498
2499 /*
2500 * Fetch the associated L2 metadata structure.
2501 * Allocate a new one if necessary.
2502 */
2503 if ((l2 = kernel_pmap->pm_l2[L2_IDX(l1idx)]) == NULL) {
2504 if (l2next == PMAP_STATIC_L2_SIZE)
2505 panic("pmap_bootstrap: out of static L2s");
2506 kernel_pmap->pm_l2[L2_IDX(l1idx)] = l2 =
2507 &static_l2[l2next++];
2508 }
2509
2510 /*
2511 * One more L1 slot tracked...
2512 */
2513 l2->l2_occupancy++;
2514
2515 /*
2516 * Fill in the details of the L2 descriptor in the
2517 * appropriate bucket.
2518 */
2519 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2520 l2b->l2b_kva = ptep;
2521 l2b->l2b_phys = pa;
2522 l2b->l2b_l1idx = l1idx;
2523
2524 /*
2525 * Establish an initial occupancy count for this descriptor
2526 */
2527 for (l2idx = 0;
2528 l2idx < (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t));
2529 l2idx++) {
2530 if ((ptep[l2idx] & L2_TYPE_MASK) != L2_TYPE_INV) {
2531 l2b->l2b_occupancy++;
2532 }
2533 }
2534
2535 /*
2536 * Make sure the descriptor itself has the correct cache mode.
2537 * If not, fix it, but whine about the problem. Port-meisters
2538 * should consider this a clue to fix up their initarm()
2539 * function. :)
2540 */
2541 if (pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)ptep)) {
2542 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2543 "L2 pte @ %p\n", ptep);
2544 }
2545 }
2546
2547
2548 /*
2549 * Ensure the primary (kernel) L1 has the correct cache mode for
2550 * a page table. Bitch if it is not correctly set.
2551 */
2552 for (va = (vm_offset_t)kernel_l1pt;
2553 va < ((vm_offset_t)kernel_l1pt + L1_TABLE_SIZE); va += PAGE_SIZE) {
2554 if (pmap_set_pt_cache_mode(kernel_l1pt, va))
2555 printf("pmap_bootstrap: WARNING! wrong cache mode for "
2556 "primary L1 @ 0x%x\n", va);
2557 }
2558
2559 cpu_dcache_wbinv_all();
2560 cpu_tlb_flushID();
2561 cpu_cpwait();
2562
2563 kernel_pmap->pm_active = -1;
2564 kernel_pmap->pm_domain = PMAP_DOMAIN_KERNEL;
2565 LIST_INIT(&allpmaps);
2566 TAILQ_INIT(&kernel_pmap->pm_pvlist);
2567 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
2568
2569 /*
2570 * Reserve some special page table entries/VA space for temporary
2571 * mapping of pages.
2572 */
2573 #define SYSMAP(c, p, v, n) \
2574 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
2575
2576 pmap_alloc_specials(&virtual_avail, 1, &csrcp, &csrc_pte);
2577 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)csrc_pte);
2578 pmap_alloc_specials(&virtual_avail, 1, &cdstp, &cdst_pte);
2579 pmap_set_pt_cache_mode(kernel_l1pt, (vm_offset_t)cdst_pte);
2580 size = ((lastaddr - pmap_curmaxkvaddr) + L1_S_OFFSET) / L1_S_SIZE;
2581 pmap_alloc_specials(&virtual_avail,
2582 round_page(size * L2_TABLE_SIZE_REAL) / PAGE_SIZE,
2583 &pmap_kernel_l2ptp_kva, NULL);
2584
2585 size = (size + (L2_BUCKET_SIZE - 1)) / L2_BUCKET_SIZE;
2586 pmap_alloc_specials(&virtual_avail,
2587 round_page(size * sizeof(struct l2_dtable)) / PAGE_SIZE,
2588 &pmap_kernel_l2dtable_kva, NULL);
2589
2590 pmap_alloc_specials(&virtual_avail,
2591 1, (vm_offset_t*)&_tmppt, NULL);
2592 SLIST_INIT(&l1_list);
2593 TAILQ_INIT(&l1_lru_list);
2594 mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF);
2595 pmap_init_l1(l1, kernel_l1pt);
2596 cpu_dcache_wbinv_all();
2597
2598 virtual_avail = round_page(virtual_avail);
2599 virtual_end = lastaddr;
2600 kernel_vm_end = pmap_curmaxkvaddr;
2601 arm_nocache_startaddr = lastaddr;
2602 mtx_init(&cmtx, "TMP mappins mtx", NULL, MTX_DEF);
2603 #ifdef ARM_USE_SMALL_ALLOC
2604 mtx_init(&smallalloc_mtx, "Small alloc page list", NULL, MTX_DEF);
2605 alloc_firstaddr = alloc_curaddr = arm_nocache_startaddr +
2606 ARM_NOCACHE_KVA_SIZE;
2607 #endif
2608 }
2609
2610 /***************************************************
2611 * Pmap allocation/deallocation routines.
2612 ***************************************************/
2613
2614 /*
2615 * Release any resources held by the given physical map.
2616 * Called when a pmap initialized by pmap_pinit is being released.
2617 * Should only be called if the map contains no valid mappings.
2618 */
2619 void
2620 pmap_release(pmap_t pmap)
2621 {
2622 struct pcb *pcb;
2623
2624 pmap_idcache_wbinv_all(pmap);
2625 pmap_tlb_flushID(pmap);
2626 cpu_cpwait();
2627 LIST_REMOVE(pmap, pm_list);
2628 if (vector_page < KERNBASE) {
2629 struct pcb *curpcb = PCPU_GET(curpcb);
2630 pcb = thread0.td_pcb;
2631 if (pmap_is_current(pmap)) {
2632 /*
2633 * Frob the L1 entry corresponding to the vector
2634 * page so that it contains the kernel pmap's domain
2635 * number. This will ensure pmap_remove() does not
2636 * pull the current vector page out from under us.
2637 */
2638 critical_enter();
2639 *pcb->pcb_pl1vec = pcb->pcb_l1vec;
2640 cpu_domains(pcb->pcb_dacr);
2641 cpu_setttb(pcb->pcb_pagedir);
2642 critical_exit();
2643 }
2644 pmap_remove(pmap, vector_page, vector_page + PAGE_SIZE);
2645 /*
2646 * Make sure cpu_switch(), et al, DTRT. This is safe to do
2647 * since this process has no remaining mappings of its own.
2648 */
2649 curpcb->pcb_pl1vec = pcb->pcb_pl1vec;
2650 curpcb->pcb_l1vec = pcb->pcb_l1vec;
2651 curpcb->pcb_dacr = pcb->pcb_dacr;
2652 curpcb->pcb_pagedir = pcb->pcb_pagedir;
2653
2654 }
2655 pmap_free_l1(pmap);
2656
2657 dprintf("pmap_release()\n");
2658 }
2659
2660
2661
2662 /*
2663 * Helper function for pmap_grow_l2_bucket()
2664 */
2665 static __inline int
2666 pmap_grow_map(vm_offset_t va, pt_entry_t cache_mode, vm_paddr_t *pap)
2667 {
2668 struct l2_bucket *l2b;
2669 pt_entry_t *ptep;
2670 vm_paddr_t pa;
2671 struct vm_page *pg;
2672
2673 pg = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
2674 if (pg == NULL)
2675 return (1);
2676 pa = VM_PAGE_TO_PHYS(pg);
2677
2678 if (pap)
2679 *pap = pa;
2680
2681 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2682
2683 ptep = &l2b->l2b_kva[l2pte_index(va)];
2684 *ptep = L2_S_PROTO | pa | cache_mode |
2685 L2_S_PROT(PTE_KERNEL, VM_PROT_READ | VM_PROT_WRITE);
2686 PTE_SYNC(ptep);
2687 return (0);
2688 }
2689
2690 /*
2691 * This is the same as pmap_alloc_l2_bucket(), except that it is only
2692 * used by pmap_growkernel().
2693 */
2694 static __inline struct l2_bucket *
2695 pmap_grow_l2_bucket(pmap_t pm, vm_offset_t va)
2696 {
2697 struct l2_dtable *l2;
2698 struct l2_bucket *l2b;
2699 struct l1_ttable *l1;
2700 pd_entry_t *pl1pd;
2701 u_short l1idx;
2702 vm_offset_t nva;
2703
2704 l1idx = L1_IDX(va);
2705
2706 if ((l2 = pm->pm_l2[L2_IDX(l1idx)]) == NULL) {
2707 /*
2708 * No mapping at this address, as there is
2709 * no entry in the L1 table.
2710 * Need to allocate a new l2_dtable.
2711 */
2712 nva = pmap_kernel_l2dtable_kva;
2713 if ((nva & PAGE_MASK) == 0) {
2714 /*
2715 * Need to allocate a backing page
2716 */
2717 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2718 return (NULL);
2719 }
2720
2721 l2 = (struct l2_dtable *)nva;
2722 nva += sizeof(struct l2_dtable);
2723
2724 if ((nva & PAGE_MASK) < (pmap_kernel_l2dtable_kva &
2725 PAGE_MASK)) {
2726 /*
2727 * The new l2_dtable straddles a page boundary.
2728 * Map in another page to cover it.
2729 */
2730 if (pmap_grow_map(nva, pte_l2_s_cache_mode, NULL))
2731 return (NULL);
2732 }
2733
2734 pmap_kernel_l2dtable_kva = nva;
2735
2736 /*
2737 * Link it into the parent pmap
2738 */
2739 pm->pm_l2[L2_IDX(l1idx)] = l2;
2740 memset(l2, 0, sizeof(*l2));
2741 }
2742
2743 l2b = &l2->l2_bucket[L2_BUCKET(l1idx)];
2744
2745 /*
2746 * Fetch pointer to the L2 page table associated with the address.
2747 */
2748 if (l2b->l2b_kva == NULL) {
2749 pt_entry_t *ptep;
2750
2751 /*
2752 * No L2 page table has been allocated. Chances are, this
2753 * is because we just allocated the l2_dtable, above.
2754 */
2755 nva = pmap_kernel_l2ptp_kva;
2756 ptep = (pt_entry_t *)nva;
2757 if ((nva & PAGE_MASK) == 0) {
2758 /*
2759 * Need to allocate a backing page
2760 */
2761 if (pmap_grow_map(nva, pte_l2_s_cache_mode_pt,
2762 &pmap_kernel_l2ptp_phys))
2763 return (NULL);
2764 PTE_SYNC_RANGE(ptep, PAGE_SIZE / sizeof(pt_entry_t));
2765 }
2766
2767 memset(ptep, 0, L2_TABLE_SIZE_REAL);
2768 l2->l2_occupancy++;
2769 l2b->l2b_kva = ptep;
2770 l2b->l2b_l1idx = l1idx;
2771 l2b->l2b_phys = pmap_kernel_l2ptp_phys;
2772
2773 pmap_kernel_l2ptp_kva += L2_TABLE_SIZE_REAL;
2774 pmap_kernel_l2ptp_phys += L2_TABLE_SIZE_REAL;
2775 }
2776
2777 /* Distribute new L1 entry to all other L1s */
2778 SLIST_FOREACH(l1, &l1_list, l1_link) {
2779 pl1pd = &l1->l1_kva[L1_IDX(va)];
2780 *pl1pd = l2b->l2b_phys | L1_C_DOM(PMAP_DOMAIN_KERNEL) |
2781 L1_C_PROTO;
2782 PTE_SYNC(pl1pd);
2783 }
2784
2785 return (l2b);
2786 }
2787
2788
2789 /*
2790 * grow the number of kernel page table entries, if needed
2791 */
2792 void
2793 pmap_growkernel(vm_offset_t addr)
2794 {
2795 pmap_t kpm = pmap_kernel();
2796 int s;
2797
2798 if (addr <= pmap_curmaxkvaddr)
2799 return; /* we are OK */
2800
2801 /*
2802 * whoops! we need to add kernel PTPs
2803 */
2804
2805 s = splhigh(); /* to be safe */
2806
2807 /* Map 1MB at a time */
2808 for (; pmap_curmaxkvaddr < addr; pmap_curmaxkvaddr += L1_S_SIZE)
2809 pmap_grow_l2_bucket(kpm, pmap_curmaxkvaddr);
2810
2811 /*
2812 * flush out the cache, expensive but growkernel will happen so
2813 * rarely
2814 */
2815 cpu_dcache_wbinv_all();
2816 cpu_tlb_flushD();
2817 cpu_cpwait();
2818 kernel_vm_end = pmap_curmaxkvaddr;
2819
2820 }
2821
2822
2823 /*
2824 * pmap_page_protect:
2825 *
2826 * Lower the permission for all mappings to a given page.
2827 */
2828 void
2829 pmap_page_protect(vm_page_t m, vm_prot_t prot)
2830 {
2831 switch(prot) {
2832 case VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE:
2833 case VM_PROT_READ|VM_PROT_WRITE:
2834 return;
2835
2836 case VM_PROT_READ:
2837 case VM_PROT_READ|VM_PROT_EXECUTE:
2838 pmap_clearbit(m, PVF_WRITE);
2839 break;
2840
2841 default:
2842 pmap_remove_all(m);
2843 break;
2844 }
2845
2846 }
2847
2848
2849 /*
2850 * Remove all pages from specified address space
2851 * this aids process exit speeds. Also, this code
2852 * is special cased for current process only, but
2853 * can have the more generic (and slightly slower)
2854 * mode enabled. This is much faster than pmap_remove
2855 * in the case of running down an entire address space.
2856 */
2857 void
2858 pmap_remove_pages(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2859 {
2860 struct pv_entry *pv, *npv;
2861 struct l2_bucket *l2b = NULL;
2862 vm_page_t m;
2863 pt_entry_t *pt;
2864
2865 vm_page_lock_queues();
2866 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) {
2867 if (pv->pv_va >= eva || pv->pv_va < sva) {
2868 npv = TAILQ_NEXT(pv, pv_plist);
2869 continue;
2870 }
2871 if (pv->pv_flags & PVF_WIRED) {
2872 /* The page is wired, cannot remove it now. */
2873 npv = TAILQ_NEXT(pv, pv_plist);
2874 continue;
2875 }
2876 pmap->pm_stats.resident_count--;
2877 l2b = pmap_get_l2_bucket(pmap, pv->pv_va);
2878 KASSERT(l2b != NULL, ("No L2 bucket in pmap_remove_pages"));
2879 pt = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
2880 m = PHYS_TO_VM_PAGE(*pt & L2_ADDR_MASK);
2881 *pt = 0;
2882 PTE_SYNC(pt);
2883 npv = TAILQ_NEXT(pv, pv_plist);
2884 pmap_nuke_pv(m, pmap, pv);
2885 pmap_free_pv_entry(pv);
2886 }
2887 vm_page_unlock_queues();
2888 cpu_idcache_wbinv_all();
2889 cpu_tlb_flushID();
2890 cpu_cpwait();
2891 }
2892
2893
2894 /***************************************************
2895 * Low level mapping routines.....
2896 ***************************************************/
2897
2898 /* Map a section into the KVA. */
2899
2900 void
2901 pmap_kenter_section(vm_offset_t va, vm_offset_t pa, int flags)
2902 {
2903 pd_entry_t pd = L1_S_PROTO | pa | L1_S_PROT(PTE_KERNEL,
2904 VM_PROT_READ|VM_PROT_WRITE) | L1_S_DOM(PMAP_DOMAIN_KERNEL);
2905 struct l1_ttable *l1;
2906
2907 KASSERT(((va | pa) & L1_S_OFFSET) == 0,
2908 ("Not a valid section mapping"));
2909 if (flags & SECTION_CACHE)
2910 pd |= pte_l1_s_cache_mode;
2911 else if (flags & SECTION_PT)
2912 pd |= pte_l1_s_cache_mode_pt;
2913 SLIST_FOREACH(l1, &l1_list, l1_link) {
2914 l1->l1_kva[L1_IDX(va)] = pd;
2915 PTE_SYNC(&l1->l1_kva[L1_IDX(va)]);
2916 }
2917 }
2918
2919 /*
2920 * add a wired page to the kva
2921 * note that in order for the mapping to take effect -- you
2922 * should do a invltlb after doing the pmap_kenter...
2923 */
2924 static PMAP_INLINE void
2925 pmap_kenter_internal(vm_offset_t va, vm_offset_t pa, int flags)
2926 {
2927 struct l2_bucket *l2b;
2928 pt_entry_t *pte;
2929 pt_entry_t opte;
2930 PDEBUG(1, printf("pmap_kenter: va = %08x, pa = %08x\n",
2931 (uint32_t) va, (uint32_t) pa));
2932
2933
2934 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2935 if (l2b == NULL)
2936 l2b = pmap_grow_l2_bucket(pmap_kernel(), va);
2937 KASSERT(l2b != NULL, ("No L2 Bucket"));
2938 pte = &l2b->l2b_kva[l2pte_index(va)];
2939 opte = *pte;
2940 PDEBUG(1, printf("pmap_kenter: pte = %08x, opte = %08x, npte = %08x\n",
2941 (uint32_t) pte, opte, *pte));
2942 if (l2pte_valid(opte)) {
2943 cpu_dcache_wbinv_range(va, PAGE_SIZE);
2944 cpu_tlb_flushD_SE(va);
2945 cpu_cpwait();
2946 } else {
2947 if (opte == 0)
2948 l2b->l2b_occupancy++;
2949 }
2950 *pte = L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL,
2951 VM_PROT_READ | VM_PROT_WRITE);
2952 if (flags & KENTER_CACHE)
2953 *pte |= pte_l2_s_cache_mode;
2954 if (flags & KENTER_USER)
2955 *pte |= L2_S_PROT_U;
2956 PTE_SYNC(pte);
2957 }
2958
2959 void
2960 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
2961 {
2962 pmap_kenter_internal(va, pa, KENTER_CACHE);
2963 }
2964
2965 void
2966 pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa)
2967 {
2968 pmap_kenter_internal(va, pa, 0);
2969 }
2970
2971 void
2972 pmap_kenter_user(vm_offset_t va, vm_paddr_t pa)
2973 {
2974
2975 pmap_kenter_internal(va, pa, KENTER_CACHE|KENTER_USER);
2976 /*
2977 * Call pmap_fault_fixup now, to make sure we'll have no exception
2978 * at the first use of the new address, or bad things will happen,
2979 * as we use one of these addresses in the exception handlers.
2980 */
2981 pmap_fault_fixup(pmap_kernel(), va, VM_PROT_READ|VM_PROT_WRITE, 1);
2982 }
2983
2984 /*
2985 * remove a page rom the kernel pagetables
2986 */
2987 PMAP_INLINE void
2988 pmap_kremove(vm_offset_t va)
2989 {
2990 struct l2_bucket *l2b;
2991 pt_entry_t *pte, opte;
2992
2993 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
2994 if (!l2b)
2995 return;
2996 KASSERT(l2b != NULL, ("No L2 Bucket"));
2997 pte = &l2b->l2b_kva[l2pte_index(va)];
2998 opte = *pte;
2999 if (l2pte_valid(opte)) {
3000 cpu_dcache_wbinv_range(va, PAGE_SIZE);
3001 cpu_tlb_flushD_SE(va);
3002 cpu_cpwait();
3003 *pte = 0;
3004 }
3005 }
3006
3007
3008 /*
3009 * Used to map a range of physical addresses into kernel
3010 * virtual address space.
3011 *
3012 * The value passed in '*virt' is a suggested virtual address for
3013 * the mapping. Architectures which can support a direct-mapped
3014 * physical to virtual region can return the appropriate address
3015 * within that region, leaving '*virt' unchanged. Other
3016 * architectures should map the pages starting at '*virt' and
3017 * update '*virt' with the first usable address after the mapped
3018 * region.
3019 */
3020 vm_offset_t
3021 pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
3022 {
3023 vm_offset_t sva = *virt;
3024 vm_offset_t va = sva;
3025
3026 PDEBUG(1, printf("pmap_map: virt = %08x, start = %08x, end = %08x, "
3027 "prot = %d\n", (uint32_t) *virt, (uint32_t) start, (uint32_t) end,
3028 prot));
3029
3030 while (start < end) {
3031 pmap_kenter(va, start);
3032 va += PAGE_SIZE;
3033 start += PAGE_SIZE;
3034 }
3035 *virt = va;
3036 return (sva);
3037 }
3038
3039 static void
3040 pmap_wb_page(vm_page_t m, boolean_t do_inv)
3041 {
3042 struct pv_entry *pv;
3043
3044 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list)
3045 pmap_dcache_wb_range(pv->pv_pmap, pv->pv_va, PAGE_SIZE, do_inv,
3046 (pv->pv_flags & PVF_WRITE) == 0);
3047 }
3048
3049 /*
3050 * Add a list of wired pages to the kva
3051 * this routine is only used for temporary
3052 * kernel mappings that do not need to have
3053 * page modification or references recorded.
3054 * Note that old mappings are simply written
3055 * over. The page *must* be wired.
3056 */
3057 void
3058 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
3059 {
3060 int i;
3061
3062 for (i = 0; i < count; i++) {
3063 pmap_wb_page(m[i], TRUE);
3064 pmap_kenter_internal(va, VM_PAGE_TO_PHYS(m[i]),
3065 KENTER_CACHE);
3066 va += PAGE_SIZE;
3067 }
3068 }
3069
3070
3071 /*
3072 * this routine jerks page mappings from the
3073 * kernel -- it is meant only for temporary mappings.
3074 */
3075 void
3076 pmap_qremove(vm_offset_t va, int count)
3077 {
3078 vm_paddr_t pa;
3079 int i;
3080
3081 for (i = 0; i < count; i++) {
3082 pa = vtophys(va);
3083 if (pa) {
3084 pmap_wb_page(PHYS_TO_VM_PAGE(pa), TRUE);
3085 pmap_kremove(va);
3086 }
3087 va += PAGE_SIZE;
3088 }
3089 }
3090
3091
3092 /*
3093 * pmap_object_init_pt preloads the ptes for a given object
3094 * into the specified pmap. This eliminates the blast of soft
3095 * faults on process startup and immediately after an mmap.
3096 */
3097 void
3098 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3099 vm_pindex_t pindex, vm_size_t size)
3100 {
3101
3102 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3103 KASSERT(object->type == OBJT_DEVICE,
3104 ("pmap_object_init_pt: non-device object"));
3105 }
3106
3107
3108 /*
3109 * pmap_is_prefaultable:
3110 *
3111 * Return whether or not the specified virtual address is elgible
3112 * for prefault.
3113 */
3114 boolean_t
3115 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3116 {
3117 pd_entry_t *pde;
3118 pt_entry_t *pte;
3119
3120 if (!pmap_get_pde_pte(pmap, addr, &pde, &pte))
3121 return (FALSE);
3122 KASSERT(pte != NULL, ("Valid mapping but no pte ?"));
3123 if (*pte == 0)
3124 return (TRUE);
3125 return (FALSE);
3126 }
3127
3128 /*
3129 * Fetch pointers to the PDE/PTE for the given pmap/VA pair.
3130 * Returns TRUE if the mapping exists, else FALSE.
3131 *
3132 * NOTE: This function is only used by a couple of arm-specific modules.
3133 * It is not safe to take any pmap locks here, since we could be right
3134 * in the middle of debugging the pmap anyway...
3135 *
3136 * It is possible for this routine to return FALSE even though a valid
3137 * mapping does exist. This is because we don't lock, so the metadata
3138 * state may be inconsistent.
3139 *
3140 * NOTE: We can return a NULL *ptp in the case where the L1 pde is
3141 * a "section" mapping.
3142 */
3143 boolean_t
3144 pmap_get_pde_pte(pmap_t pm, vm_offset_t va, pd_entry_t **pdp, pt_entry_t **ptp)
3145 {
3146 struct l2_dtable *l2;
3147 pd_entry_t *pl1pd, l1pd;
3148 pt_entry_t *ptep;
3149 u_short l1idx;
3150
3151 if (pm->pm_l1 == NULL)
3152 return (FALSE);
3153
3154 l1idx = L1_IDX(va);
3155 *pdp = pl1pd = &pm->pm_l1->l1_kva[l1idx];
3156 l1pd = *pl1pd;
3157
3158 if (l1pte_section_p(l1pd)) {
3159 *ptp = NULL;
3160 return (TRUE);
3161 }
3162
3163 if (pm->pm_l2 == NULL)
3164 return (FALSE);
3165
3166 l2 = pm->pm_l2[L2_IDX(l1idx)];
3167
3168 if (l2 == NULL ||
3169 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3170 return (FALSE);
3171 }
3172
3173 *ptp = &ptep[l2pte_index(va)];
3174 return (TRUE);
3175 }
3176
3177 /*
3178 * Routine: pmap_remove_all
3179 * Function:
3180 * Removes this physical page from
3181 * all physical maps in which it resides.
3182 * Reflects back modify bits to the pager.
3183 *
3184 * Notes:
3185 * Original versions of this routine were very
3186 * inefficient because they iteratively called
3187 * pmap_remove (slow...)
3188 */
3189 void
3190 pmap_remove_all(vm_page_t m)
3191 {
3192 pv_entry_t pv;
3193 pt_entry_t *ptep, pte;
3194 struct l2_bucket *l2b;
3195 boolean_t flush = FALSE;
3196 pmap_t curpm;
3197 int flags = 0;
3198
3199 #if defined(PMAP_DEBUG)
3200 /*
3201 * XXX this makes pmap_page_protect(NONE) illegal for non-managed
3202 * pages!
3203 */
3204 if (m->flags & PG_FICTITIOUS) {
3205 panic("pmap_page_protect: illegal for unmanaged page, va: 0x%x", VM_PAGE_TO_PHYS(m));
3206 }
3207 #endif
3208
3209 if (TAILQ_EMPTY(&m->md.pv_list))
3210 return;
3211 curpm = vmspace_pmap(curproc->p_vmspace);
3212 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3213 if (flush == FALSE && (pv->pv_pmap == curpm ||
3214 pv->pv_pmap == pmap_kernel()))
3215 flush = TRUE;
3216 l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
3217 KASSERT(l2b != NULL, ("No l2 bucket"));
3218 ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
3219 pte = *ptep;
3220 *ptep = 0;
3221 PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
3222 pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
3223 if (pv->pv_flags & PVF_WIRED)
3224 pv->pv_pmap->pm_stats.wired_count--;
3225 pv->pv_pmap->pm_stats.resident_count--;
3226 flags |= pv->pv_flags;
3227 pmap_nuke_pv(m, pv->pv_pmap, pv);
3228 pmap_free_pv_entry(pv);
3229 }
3230
3231 if (flush) {
3232 if (PV_BEEN_EXECD(flags))
3233 pmap_tlb_flushID(curpm);
3234 else
3235 pmap_tlb_flushD(curpm);
3236 }
3237 }
3238
3239
3240 /*
3241 * Set the physical protection on the
3242 * specified range of this map as requested.
3243 */
3244 void
3245 pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3246 {
3247 struct l2_bucket *l2b;
3248 pt_entry_t *ptep, pte;
3249 vm_offset_t next_bucket;
3250 u_int flags;
3251 int flush;
3252
3253 if ((prot & VM_PROT_READ) == 0) {
3254 mtx_lock(&Giant);
3255 pmap_remove(pm, sva, eva);
3256 mtx_unlock(&Giant);
3257 return;
3258 }
3259
3260 if (prot & VM_PROT_WRITE) {
3261 /*
3262 * If this is a read->write transition, just ignore it and let
3263 * vm_fault() take care of it later.
3264 */
3265 return;
3266 }
3267
3268 mtx_lock(&Giant);
3269
3270 /*
3271 * OK, at this point, we know we're doing write-protect operation.
3272 * If the pmap is active, write-back the range.
3273 */
3274 pmap_dcache_wb_range(pm, sva, eva - sva, FALSE, FALSE);
3275
3276 flush = ((eva - sva) >= (PAGE_SIZE * 4)) ? 0 : -1;
3277 flags = 0;
3278
3279 vm_page_lock_queues();
3280 while (sva < eva) {
3281 next_bucket = L2_NEXT_BUCKET(sva);
3282 if (next_bucket > eva)
3283 next_bucket = eva;
3284
3285 l2b = pmap_get_l2_bucket(pm, sva);
3286 if (l2b == NULL) {
3287 sva = next_bucket;
3288 continue;
3289 }
3290
3291 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3292
3293 while (sva < next_bucket) {
3294 if ((pte = *ptep) != 0 && (pte & L2_S_PROT_W) != 0) {
3295 struct vm_page *pg;
3296 u_int f;
3297
3298 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3299 pte &= ~L2_S_PROT_W;
3300 *ptep = pte;
3301 PTE_SYNC(ptep);
3302
3303 if (pg != NULL) {
3304 f = pmap_modify_pv(pg, pm, sva,
3305 PVF_WRITE, 0);
3306 pmap_vac_me_harder(pg, pm, sva);
3307 if (pmap_track_modified(sva))
3308 vm_page_dirty(pg);
3309 } else
3310 f = PVF_REF | PVF_EXEC;
3311
3312 if (flush >= 0) {
3313 flush++;
3314 flags |= f;
3315 } else
3316 if (PV_BEEN_EXECD(f))
3317 pmap_tlb_flushID_SE(pm, sva);
3318 else
3319 if (PV_BEEN_REFD(f))
3320 pmap_tlb_flushD_SE(pm, sva);
3321 }
3322
3323 sva += PAGE_SIZE;
3324 ptep++;
3325 }
3326 }
3327
3328
3329 if (flush) {
3330 if (PV_BEEN_EXECD(flags))
3331 pmap_tlb_flushID(pm);
3332 else
3333 if (PV_BEEN_REFD(flags))
3334 pmap_tlb_flushD(pm);
3335 }
3336 vm_page_unlock_queues();
3337
3338 mtx_unlock(&Giant);
3339 }
3340
3341
3342 /*
3343 * Insert the given physical page (p) at
3344 * the specified virtual address (v) in the
3345 * target physical map with the protection requested.
3346 *
3347 * If specified, the page will be wired down, meaning
3348 * that the related pte can not be reclaimed.
3349 *
3350 * NB: This is the only routine which MAY NOT lazy-evaluate
3351 * or lose information. That is, this routine must actually
3352 * insert this page into the given map NOW.
3353 */
3354
3355 void
3356 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3357 boolean_t wired)
3358 {
3359 struct l2_bucket *l2b = NULL;
3360 struct vm_page *opg;
3361 struct pv_entry *pve = NULL;
3362 pt_entry_t *ptep, npte, opte;
3363 u_int nflags;
3364 u_int oflags;
3365 vm_paddr_t pa;
3366
3367 vm_page_lock_queues();
3368 if (va == vector_page) {
3369 pa = systempage.pv_pa;
3370 m = NULL;
3371 } else
3372 pa = VM_PAGE_TO_PHYS(m);
3373 nflags = 0;
3374 if (prot & VM_PROT_WRITE)
3375 nflags |= PVF_WRITE;
3376 if (prot & VM_PROT_EXECUTE)
3377 nflags |= PVF_EXEC;
3378 if (wired)
3379 nflags |= PVF_WIRED;
3380 PDEBUG(1, printf("pmap_enter: pmap = %08x, va = %08x, m = %08x, prot = %x, "
3381 "wired = %x\n", (uint32_t) pmap, va, (uint32_t) m, prot, wired));
3382
3383 if (pmap == pmap_kernel()) {
3384 l2b = pmap_get_l2_bucket(pmap, va);
3385 if (l2b == NULL)
3386 l2b = pmap_grow_l2_bucket(pmap, va);
3387 } else
3388 l2b = pmap_alloc_l2_bucket(pmap, va);
3389 KASSERT(l2b != NULL,
3390 ("pmap_enter: failed to allocate l2 bucket"));
3391 ptep = &l2b->l2b_kva[l2pte_index(va)];
3392
3393 opte = *ptep;
3394 npte = pa;
3395 oflags = 0;
3396 if (opte) {
3397 /*
3398 * There is already a mapping at this address.
3399 * If the physical address is different, lookup the
3400 * vm_page.
3401 */
3402 if (l2pte_pa(opte) != pa)
3403 opg = PHYS_TO_VM_PAGE(l2pte_pa(opte));
3404 else
3405 opg = m;
3406 } else
3407 opg = NULL;
3408
3409 if ((prot & (VM_PROT_ALL)) ||
3410 (!m || m->md.pvh_attrs & PVF_REF)) {
3411 /*
3412 * - The access type indicates that we don't need
3413 * to do referenced emulation.
3414 * OR
3415 * - The physical page has already been referenced
3416 * so no need to re-do referenced emulation here.
3417 */
3418 npte |= L2_S_PROTO;
3419
3420 nflags |= PVF_REF;
3421
3422 if (m && ((prot & VM_PROT_WRITE) != 0 ||
3423 (m->md.pvh_attrs & PVF_MOD))) {
3424 /*
3425 * This is a writable mapping, and the
3426 * page's mod state indicates it has
3427 * already been modified. Make it
3428 * writable from the outset.
3429 */
3430 nflags |= PVF_MOD;
3431 if (!(m->md.pvh_attrs & PVF_MOD) &&
3432 pmap_track_modified(va))
3433 vm_page_dirty(m);
3434 }
3435 if (m && opte)
3436 vm_page_flag_set(m, PG_REFERENCED);
3437 } else {
3438 /*
3439 * Need to do page referenced emulation.
3440 */
3441 npte |= L2_TYPE_INV;
3442 }
3443
3444 if (prot & VM_PROT_WRITE)
3445 npte |= L2_S_PROT_W;
3446 npte |= pte_l2_s_cache_mode;
3447 if (m && m == opg) {
3448 /*
3449 * We're changing the attrs of an existing mapping.
3450 */
3451 #if 0
3452 simple_lock(&pg->mdpage.pvh_slock);
3453 #endif
3454 oflags = pmap_modify_pv(m, pmap, va,
3455 PVF_WRITE | PVF_EXEC | PVF_WIRED |
3456 PVF_MOD | PVF_REF, nflags);
3457 #if 0
3458 simple_unlock(&pg->mdpage.pvh_slock);
3459 #endif
3460
3461 /*
3462 * We may need to flush the cache if we're
3463 * doing rw-ro...
3464 */
3465 if (pmap_is_current(pmap) &&
3466 (oflags & PVF_NC) == 0 &&
3467 (opte & L2_S_PROT_W) != 0 &&
3468 (prot & VM_PROT_WRITE) == 0)
3469 cpu_dcache_wb_range(va, PAGE_SIZE);
3470 } else {
3471 /*
3472 * New mapping, or changing the backing page
3473 * of an existing mapping.
3474 */
3475 if (opg) {
3476 /*
3477 * Replacing an existing mapping with a new one.
3478 * It is part of our managed memory so we
3479 * must remove it from the PV list
3480 */
3481 #if 0
3482 simple_lock(&opg->mdpage.pvh_slock);
3483 #endif
3484 pve = pmap_remove_pv(opg, pmap, va);
3485 if (m && (m->flags & (PG_UNMANAGED | PG_FICTITIOUS)) &&
3486 pve)
3487 pmap_free_pv_entry(pve);
3488 else if (!pve &&
3489 !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3490 pve = pmap_get_pv_entry();
3491 KASSERT(pve != NULL, ("No pv"));
3492 #if 0
3493 simple_unlock(&opg->mdpage.pvh_slock);
3494 #endif
3495 oflags = pve->pv_flags;
3496
3497 /*
3498 * If the old mapping was valid (ref/mod
3499 * emulation creates 'invalid' mappings
3500 * initially) then make sure to frob
3501 * the cache.
3502 */
3503 if ((oflags & PVF_NC) == 0 &&
3504 l2pte_valid(opte)) {
3505 if (PV_BEEN_EXECD(oflags)) {
3506 pmap_idcache_wbinv_range(pmap, va,
3507 PAGE_SIZE);
3508 } else
3509 if (PV_BEEN_REFD(oflags)) {
3510 pmap_dcache_wb_range(pmap, va,
3511 PAGE_SIZE, TRUE,
3512 (oflags & PVF_WRITE) == 0);
3513 }
3514 }
3515 } else if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3516 if ((pve = pmap_get_pv_entry()) == NULL) {
3517 panic("pmap_enter: no pv entries");
3518 }
3519 if (m && !(m->flags & (PG_UNMANAGED | PG_FICTITIOUS)))
3520 pmap_enter_pv(m, pve, pmap, va, nflags);
3521 }
3522 /*
3523 * Make sure userland mappings get the right permissions
3524 */
3525 if (pmap != pmap_kernel() && va != vector_page) {
3526 npte |= L2_S_PROT_U;
3527 }
3528
3529 /*
3530 * Keep the stats up to date
3531 */
3532 if (opte == 0) {
3533 l2b->l2b_occupancy++;
3534 pmap->pm_stats.resident_count++;
3535 }
3536
3537
3538 /*
3539 * If this is just a wiring change, the two PTEs will be
3540 * identical, so there's no need to update the page table.
3541 */
3542 if (npte != opte) {
3543 boolean_t is_cached = pmap_is_current(pmap);
3544
3545 *ptep = npte;
3546 if (is_cached) {
3547 /*
3548 * We only need to frob the cache/tlb if this pmap
3549 * is current
3550 */
3551 PTE_SYNC(ptep);
3552 if (L1_IDX(va) != L1_IDX(vector_page) &&
3553 l2pte_valid(npte)) {
3554 /*
3555 * This mapping is likely to be accessed as
3556 * soon as we return to userland. Fix up the
3557 * L1 entry to avoid taking another
3558 * page/domain fault.
3559 */
3560 pd_entry_t *pl1pd, l1pd;
3561
3562 pl1pd = &pmap->pm_l1->l1_kva[L1_IDX(va)];
3563 l1pd = l2b->l2b_phys | L1_C_DOM(pmap->pm_domain) |
3564 L1_C_PROTO;
3565 if (*pl1pd != l1pd) {
3566 *pl1pd = l1pd;
3567 PTE_SYNC(pl1pd);
3568 }
3569 }
3570 }
3571
3572 if (PV_BEEN_EXECD(oflags))
3573 pmap_tlb_flushID_SE(pmap, va);
3574 else if (PV_BEEN_REFD(oflags))
3575 pmap_tlb_flushD_SE(pmap, va);
3576
3577
3578 if (m)
3579 pmap_vac_me_harder(m, pmap, va);
3580 }
3581 vm_page_unlock_queues();
3582 }
3583
3584 /*
3585 * this code makes some *MAJOR* assumptions:
3586 * 1. Current pmap & pmap exists.
3587 * 2. Not wired.
3588 * 3. Read access.
3589 * 4. No page table pages.
3590 * but is *MUCH* faster than pmap_enter...
3591 */
3592
3593 vm_page_t
3594 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3595 vm_page_t mpte)
3596 {
3597
3598 vm_page_busy(m);
3599 vm_page_unlock_queues();
3600 VM_OBJECT_UNLOCK(m->object);
3601 mtx_lock(&Giant);
3602 pmap_enter(pmap, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
3603 pmap_idcache_wbinv_all(pmap);
3604 mtx_unlock(&Giant);
3605 VM_OBJECT_LOCK(m->object);
3606 vm_page_lock_queues();
3607 vm_page_wakeup(m);
3608 return (NULL);
3609 }
3610
3611 /*
3612 * Routine: pmap_change_wiring
3613 * Function: Change the wiring attribute for a map/virtual-address
3614 * pair.
3615 * In/out conditions:
3616 * The mapping must already exist in the pmap.
3617 */
3618 void
3619 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3620 {
3621 struct l2_bucket *l2b;
3622 pt_entry_t *ptep, pte;
3623 vm_page_t pg;
3624
3625 l2b = pmap_get_l2_bucket(pmap, va);
3626 KASSERT(l2b, ("No l2b bucket in pmap_change_wiring"));
3627 ptep = &l2b->l2b_kva[l2pte_index(va)];
3628 pte = *ptep;
3629 pg = PHYS_TO_VM_PAGE(l2pte_pa(pte));
3630 if (pg)
3631 pmap_modify_pv(pg, pmap, va, PVF_WIRED, wired);
3632 }
3633
3634
3635 /*
3636 * Copy the range specified by src_addr/len
3637 * from the source map to the range dst_addr/len
3638 * in the destination map.
3639 *
3640 * This routine is only advisory and need not do anything.
3641 */
3642 void
3643 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
3644 vm_size_t len, vm_offset_t src_addr)
3645 {
3646 }
3647
3648
3649 /*
3650 * Routine: pmap_extract
3651 * Function:
3652 * Extract the physical page address associated
3653 * with the given map/virtual_address pair.
3654 */
3655 vm_paddr_t
3656 pmap_extract(pmap_t pm, vm_offset_t va)
3657 {
3658 struct l2_dtable *l2;
3659 pd_entry_t *pl1pd, l1pd;
3660 pt_entry_t *ptep, pte;
3661 vm_paddr_t pa;
3662 u_int l1idx;
3663 l1idx = L1_IDX(va);
3664 pl1pd = &pm->pm_l1->l1_kva[l1idx];
3665 l1pd = *pl1pd;
3666
3667 if (l1pte_section_p(l1pd)) {
3668 /*
3669 * These should only happen for pmap_kernel()
3670 */
3671 KASSERT(pm == pmap_kernel(), ("huh"));
3672 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3673 } else {
3674 /*
3675 * Note that we can't rely on the validity of the L1
3676 * descriptor as an indication that a mapping exists.
3677 * We have to look it up in the L2 dtable.
3678 */
3679 l2 = pm->pm_l2[L2_IDX(l1idx)];
3680
3681 if (l2 == NULL ||
3682 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3683 return (0);
3684 }
3685
3686 ptep = &ptep[l2pte_index(va)];
3687 pte = *ptep;
3688
3689 if (pte == 0)
3690 return (0);
3691
3692 switch (pte & L2_TYPE_MASK) {
3693 case L2_TYPE_L:
3694 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3695 break;
3696
3697 default:
3698 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3699 break;
3700 }
3701 }
3702
3703 return (pa);
3704 }
3705
3706 /*
3707 * Atomically extract and hold the physical page with the given
3708 * pmap and virtual address pair if that mapping permits the given
3709 * protection.
3710 *
3711 */
3712 vm_page_t
3713 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3714 {
3715 struct l2_dtable *l2;
3716 pd_entry_t *pl1pd, l1pd;
3717 pt_entry_t *ptep, pte;
3718 vm_paddr_t pa;
3719 vm_page_t m = NULL;
3720 u_int l1idx;
3721 l1idx = L1_IDX(va);
3722 pl1pd = &pmap->pm_l1->l1_kva[l1idx];
3723 l1pd = *pl1pd;
3724
3725 vm_page_lock_queues();
3726 if (l1pte_section_p(l1pd)) {
3727 /*
3728 * These should only happen for pmap_kernel()
3729 */
3730 KASSERT(pmap == pmap_kernel(), ("huh"));
3731 pa = (l1pd & L1_S_FRAME) | (va & L1_S_OFFSET);
3732 if (l1pd & L1_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3733 m = PHYS_TO_VM_PAGE(pa);
3734 vm_page_hold(m);
3735 }
3736
3737 } else {
3738 /*
3739 * Note that we can't rely on the validity of the L1
3740 * descriptor as an indication that a mapping exists.
3741 * We have to look it up in the L2 dtable.
3742 */
3743 l2 = pmap->pm_l2[L2_IDX(l1idx)];
3744
3745 if (l2 == NULL ||
3746 (ptep = l2->l2_bucket[L2_BUCKET(l1idx)].l2b_kva) == NULL) {
3747 return (NULL);
3748 }
3749
3750 ptep = &ptep[l2pte_index(va)];
3751 pte = *ptep;
3752
3753 if (pte == 0)
3754 return (NULL);
3755
3756 if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
3757 switch (pte & L2_TYPE_MASK) {
3758 case L2_TYPE_L:
3759 pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
3760 break;
3761
3762 default:
3763 pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
3764 break;
3765 }
3766 m = PHYS_TO_VM_PAGE(pa);
3767 vm_page_hold(m);
3768 }
3769 }
3770
3771 vm_page_unlock_queues();
3772 return (m);
3773 }
3774
3775 /*
3776 * Initialize a preallocated and zeroed pmap structure,
3777 * such as one in a vmspace structure.
3778 */
3779
3780 void
3781 pmap_pinit(pmap_t pmap)
3782 {
3783 PDEBUG(1, printf("pmap_pinit: pmap = %08x\n", (uint32_t) pmap));
3784
3785 pmap_alloc_l1(pmap);
3786 bzero(pmap->pm_l2, sizeof(pmap->pm_l2));
3787
3788 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
3789 pmap->pm_count = 1;
3790 pmap->pm_active = 0;
3791
3792 TAILQ_INIT(&pmap->pm_pvlist);
3793 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3794 pmap->pm_stats.resident_count = 1;
3795 if (vector_page < KERNBASE) {
3796 pmap_enter(pmap, vector_page, PHYS_TO_VM_PAGE(systempage.pv_pa),
3797 VM_PROT_READ, 1);
3798 }
3799 }
3800
3801
3802 /***************************************************
3803 * page management routines.
3804 ***************************************************/
3805
3806
3807 static void
3808 pmap_free_pv_entry(pv_entry_t pv)
3809 {
3810 pv_entry_count--;
3811 uma_zfree(pvzone, pv);
3812 }
3813
3814
3815 /*
3816 * get a new pv_entry, allocating a block from the system
3817 * when needed.
3818 * the memory allocation is performed bypassing the malloc code
3819 * because of the possibility of allocations at interrupt time.
3820 */
3821 static pv_entry_t
3822 pmap_get_pv_entry(void)
3823 {
3824 pv_entry_t ret_value;
3825
3826 pv_entry_count++;
3827 if (pv_entry_high_water &&
3828 (pv_entry_count > pv_entry_high_water) &&
3829 (pmap_pagedaemon_waken == 0)) {
3830 pmap_pagedaemon_waken = 1;
3831 wakeup (&vm_pages_needed);
3832 }
3833 ret_value = uma_zalloc(pvzone, M_NOWAIT);
3834 return ret_value;
3835 }
3836
3837
3838 /*
3839 * Remove the given range of addresses from the specified map.
3840 *
3841 * It is assumed that the start and end are properly
3842 * rounded to the page size.
3843 */
3844 #define PMAP_REMOVE_CLEAN_LIST_SIZE 3
3845 void
3846 pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva)
3847 {
3848 struct l2_bucket *l2b;
3849 vm_offset_t next_bucket;
3850 pt_entry_t *ptep;
3851 u_int cleanlist_idx, total, cnt;
3852 struct {
3853 vm_offset_t va;
3854 pt_entry_t *pte;
3855 } cleanlist[PMAP_REMOVE_CLEAN_LIST_SIZE];
3856 u_int mappings, is_exec, is_refd;
3857 int flushall = 0;
3858
3859
3860 /*
3861 * we lock in the pmap => pv_head direction
3862 */
3863 #if 0
3864 PMAP_MAP_TO_HEAD_LOCK();
3865 pmap_acquire_pmap_lock(pm);
3866 #endif
3867
3868 vm_page_lock_queues();
3869 if (!pmap_is_current(pm)) {
3870 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
3871 } else
3872 cleanlist_idx = 0;
3873
3874 total = 0;
3875 while (sva < eva) {
3876 /*
3877 * Do one L2 bucket's worth at a time.
3878 */
3879 next_bucket = L2_NEXT_BUCKET(sva);
3880 if (next_bucket > eva)
3881 next_bucket = eva;
3882
3883 l2b = pmap_get_l2_bucket(pm, sva);
3884 if (l2b == NULL) {
3885 sva = next_bucket;
3886 continue;
3887 }
3888
3889 ptep = &l2b->l2b_kva[l2pte_index(sva)];
3890 mappings = 0;
3891
3892 while (sva < next_bucket) {
3893 struct vm_page *pg;
3894 pt_entry_t pte;
3895 vm_paddr_t pa;
3896
3897 pte = *ptep;
3898
3899 if (pte == 0) {
3900 /*
3901 * Nothing here, move along
3902 */
3903 sva += PAGE_SIZE;
3904 ptep++;
3905 continue;
3906 }
3907
3908 pm->pm_stats.resident_count--;
3909 pa = l2pte_pa(pte);
3910 is_exec = 0;
3911 is_refd = 1;
3912
3913 /*
3914 * Update flags. In a number of circumstances,
3915 * we could cluster a lot of these and do a
3916 * number of sequential pages in one go.
3917 */
3918 if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
3919 struct pv_entry *pve;
3920 #if 0
3921 simple_lock(&pg->mdpage.pvh_slock);
3922 #endif
3923 pve = pmap_remove_pv(pg, pm, sva);
3924 if (pve) {
3925 #if 0
3926 simple_unlock(&pg->mdpage.pvh_slock);
3927 #endif
3928 is_exec =
3929 PV_BEEN_EXECD(pve->pv_flags);
3930 is_refd =
3931 PV_BEEN_REFD(pve->pv_flags);
3932 pmap_free_pv_entry(pve);
3933 }
3934 }
3935
3936 if (!l2pte_valid(pte)) {
3937 *ptep = 0;
3938 PTE_SYNC_CURRENT(pm, ptep);
3939 sva += PAGE_SIZE;
3940 ptep++;
3941 mappings++;
3942 continue;
3943 }
3944
3945 if (cleanlist_idx < PMAP_REMOVE_CLEAN_LIST_SIZE) {
3946 /* Add to the clean list. */
3947 cleanlist[cleanlist_idx].pte = ptep;
3948 cleanlist[cleanlist_idx].va =
3949 sva | (is_exec & 1);
3950 cleanlist_idx++;
3951 } else
3952 if (cleanlist_idx == PMAP_REMOVE_CLEAN_LIST_SIZE) {
3953 /* Nuke everything if needed. */
3954 pmap_idcache_wbinv_all(pm);
3955 pmap_tlb_flushID(pm);
3956
3957 /*
3958 * Roll back the previous PTE list,
3959 * and zero out the current PTE.
3960 */
3961 for (cnt = 0;
3962 cnt < PMAP_REMOVE_CLEAN_LIST_SIZE; cnt++) {
3963 *cleanlist[cnt].pte = 0;
3964 }
3965 *ptep = 0;
3966 PTE_SYNC(ptep);
3967 cleanlist_idx++;
3968 flushall = 1;
3969 } else {
3970 *ptep = 0;
3971 PTE_SYNC(ptep);
3972 if (is_exec)
3973 pmap_tlb_flushID_SE(pm, sva);
3974 else
3975 if (is_refd)
3976 pmap_tlb_flushD_SE(pm, sva);
3977 }
3978
3979 sva += PAGE_SIZE;
3980 ptep++;
3981 mappings++;
3982 }
3983
3984 /*
3985 * Deal with any left overs
3986 */
3987 if (cleanlist_idx <= PMAP_REMOVE_CLEAN_LIST_SIZE) {
3988 total += cleanlist_idx;
3989 for (cnt = 0; cnt < cleanlist_idx; cnt++) {
3990 vm_offset_t clva =
3991 cleanlist[cnt].va & ~1;
3992 if (cleanlist[cnt].va & 1) {
3993 pmap_idcache_wbinv_range(pm,
3994 clva, PAGE_SIZE);
3995 pmap_tlb_flushID_SE(pm, clva);
3996 } else {
3997 pmap_dcache_wb_range(pm,
3998 clva, PAGE_SIZE, TRUE,
3999 FALSE);
4000 pmap_tlb_flushD_SE(pm, clva);
4001 }
4002 *cleanlist[cnt].pte = 0;
4003 PTE_SYNC_CURRENT(pm, cleanlist[cnt].pte);
4004 }
4005
4006 if (total <= PMAP_REMOVE_CLEAN_LIST_SIZE)
4007 cleanlist_idx = 0;
4008 else {
4009 /*
4010 * We are removing so much entries it's just
4011 * easier to flush the whole cache.
4012 */
4013 cleanlist_idx = PMAP_REMOVE_CLEAN_LIST_SIZE + 1;
4014 pmap_idcache_wbinv_all(pm);
4015 flushall = 1;
4016 }
4017 }
4018
4019 pmap_free_l2_bucket(pm, l2b, mappings);
4020 }
4021
4022 vm_page_unlock_queues();
4023 if (flushall)
4024 cpu_tlb_flushID();
4025 #if 0
4026 pmap_release_pmap_lock(pm);
4027 PMAP_MAP_TO_HEAD_UNLOCK();
4028 #endif
4029 }
4030
4031
4032
4033
4034 /*
4035 * pmap_zero_page()
4036 *
4037 * Zero a given physical page by mapping it at a page hook point.
4038 * In doing the zero page op, the page we zero is mapped cachable, as with
4039 * StrongARM accesses to non-cached pages are non-burst making writing
4040 * _any_ bulk data very slow.
4041 */
4042 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4043 void
4044 pmap_zero_page_generic(vm_paddr_t phys, int off, int size)
4045 {
4046 #ifdef DEBUG
4047 struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
4048
4049 if (pg->md.pvh_list != NULL)
4050 panic("pmap_zero_page: page has mappings");
4051 #endif
4052
4053
4054 mtx_lock(&cmtx);
4055 /*
4056 * Hook in the page, zero it, and purge the cache for that
4057 * zeroed page. Invalidate the TLB as needed.
4058 */
4059 *cdst_pte = L2_S_PROTO | phys |
4060 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4061 PTE_SYNC(cdst_pte);
4062 cpu_tlb_flushD_SE(cdstp);
4063 cpu_cpwait();
4064 if (off || size != PAGE_SIZE)
4065 bzero((void *)(cdstp + off), size);
4066 else
4067 bzero_page(cdstp);
4068 mtx_unlock(&cmtx);
4069 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4070 }
4071 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4072
4073 #if ARM_MMU_XSCALE == 1
4074 void
4075 pmap_zero_page_xscale(vm_paddr_t phys, int off, int size)
4076 {
4077
4078 mtx_lock(&cmtx);
4079 /*
4080 * Hook in the page, zero it, and purge the cache for that
4081 * zeroed page. Invalidate the TLB as needed.
4082 */
4083 *cdst_pte = L2_S_PROTO | phys |
4084 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4085 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4086 PTE_SYNC(cdst_pte);
4087 cpu_tlb_flushD_SE(cdstp);
4088 cpu_cpwait();
4089 if (off || size != PAGE_SIZE)
4090 bzero((void *)(cdstp + off), size);
4091 else
4092 bzero_page(cdstp);
4093 mtx_unlock(&cmtx);
4094 xscale_cache_clean_minidata();
4095 }
4096
4097 /*
4098 * Change the PTEs for the specified kernel mappings such that they
4099 * will use the mini data cache instead of the main data cache.
4100 */
4101 void
4102 pmap_use_minicache(vm_offset_t va, vm_size_t size)
4103 {
4104 struct l2_bucket *l2b;
4105 pt_entry_t *ptep, *sptep, pte;
4106 vm_offset_t next_bucket, eva;
4107
4108 #if (ARM_NMMUS > 1)
4109 if (xscale_use_minidata == 0)
4110 return;
4111 #endif
4112
4113 eva = va + size;
4114
4115 while (va < eva) {
4116 next_bucket = L2_NEXT_BUCKET(va);
4117 if (next_bucket > eva)
4118 next_bucket = eva;
4119
4120 l2b = pmap_get_l2_bucket(pmap_kernel(), va);
4121
4122 sptep = ptep = &l2b->l2b_kva[l2pte_index(va)];
4123
4124 while (va < next_bucket) {
4125 pte = *ptep;
4126 if (!l2pte_minidata(pte)) {
4127 cpu_dcache_wbinv_range(va, PAGE_SIZE);
4128 cpu_tlb_flushD_SE(va);
4129 *ptep = pte & ~L2_B;
4130 }
4131 ptep++;
4132 va += PAGE_SIZE;
4133 }
4134 PTE_SYNC_RANGE(sptep, (u_int)(ptep - sptep));
4135 }
4136 cpu_cpwait();
4137 }
4138 #endif /* ARM_MMU_XSCALE == 1 */
4139
4140 /*
4141 * pmap_zero_page zeros the specified hardware page by mapping
4142 * the page into KVM and using bzero to clear its contents.
4143 */
4144 void
4145 pmap_zero_page(vm_page_t m)
4146 {
4147 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), 0, PAGE_SIZE);
4148 }
4149
4150
4151 /*
4152 * pmap_zero_page_area zeros the specified hardware page by mapping
4153 * the page into KVM and using bzero to clear its contents.
4154 *
4155 * off and size may not cover an area beyond a single hardware page.
4156 */
4157 void
4158 pmap_zero_page_area(vm_page_t m, int off, int size)
4159 {
4160
4161 pmap_zero_page_func(VM_PAGE_TO_PHYS(m), off, size);
4162 }
4163
4164
4165 /*
4166 * pmap_zero_page_idle zeros the specified hardware page by mapping
4167 * the page into KVM and using bzero to clear its contents. This
4168 * is intended to be called from the vm_pagezero process only and
4169 * outside of Giant.
4170 */
4171 void
4172 pmap_zero_page_idle(vm_page_t m)
4173 {
4174
4175 pmap_zero_page(m);
4176 }
4177
4178 /*
4179 * pmap_clean_page()
4180 *
4181 * This is a local function used to work out the best strategy to clean
4182 * a single page referenced by its entry in the PV table. It's used by
4183 * pmap_copy_page, pmap_zero page and maybe some others later on.
4184 *
4185 * Its policy is effectively:
4186 * o If there are no mappings, we don't bother doing anything with the cache.
4187 * o If there is one mapping, we clean just that page.
4188 * o If there are multiple mappings, we clean the entire cache.
4189 *
4190 * So that some functions can be further optimised, it returns 0 if it didn't
4191 * clean the entire cache, or 1 if it did.
4192 *
4193 * XXX One bug in this routine is that if the pv_entry has a single page
4194 * mapped at 0x00000000 a whole cache clean will be performed rather than
4195 * just the 1 page. Since this should not occur in everyday use and if it does
4196 * it will just result in not the most efficient clean for the page.
4197 */
4198 static int
4199 pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
4200 {
4201 pmap_t pm, pm_to_clean = NULL;
4202 struct pv_entry *npv;
4203 u_int cache_needs_cleaning = 0;
4204 u_int flags = 0;
4205 vm_offset_t page_to_clean = 0;
4206
4207 if (pv == NULL) {
4208 /* nothing mapped in so nothing to flush */
4209 return (0);
4210 }
4211
4212 /*
4213 * Since we flush the cache each time we change to a different
4214 * user vmspace, we only need to flush the page if it is in the
4215 * current pmap.
4216 */
4217 if (curthread)
4218 pm = vmspace_pmap(curproc->p_vmspace);
4219 else
4220 pm = pmap_kernel();
4221
4222 for (npv = pv; npv; npv = TAILQ_NEXT(npv, pv_list)) {
4223 if (npv->pv_pmap == pmap_kernel() || npv->pv_pmap == pm) {
4224 flags |= npv->pv_flags;
4225 /*
4226 * The page is mapped non-cacheable in
4227 * this map. No need to flush the cache.
4228 */
4229 if (npv->pv_flags & PVF_NC) {
4230 #ifdef DIAGNOSTIC
4231 if (cache_needs_cleaning)
4232 panic("pmap_clean_page: "
4233 "cache inconsistency");
4234 #endif
4235 break;
4236 } else if (is_src && (npv->pv_flags & PVF_WRITE) == 0)
4237 continue;
4238 if (cache_needs_cleaning) {
4239 page_to_clean = 0;
4240 break;
4241 } else {
4242 page_to_clean = npv->pv_va;
4243 pm_to_clean = npv->pv_pmap;
4244 }
4245 cache_needs_cleaning = 1;
4246 }
4247 }
4248 if (page_to_clean) {
4249 if (PV_BEEN_EXECD(flags))
4250 pmap_idcache_wbinv_range(pm_to_clean, page_to_clean,
4251 PAGE_SIZE);
4252 else
4253 pmap_dcache_wb_range(pm_to_clean, page_to_clean,
4254 PAGE_SIZE, !is_src, (flags & PVF_WRITE) == 0);
4255 } else if (cache_needs_cleaning) {
4256 if (PV_BEEN_EXECD(flags))
4257 pmap_idcache_wbinv_all(pm);
4258 else
4259 pmap_dcache_wbinv_all(pm);
4260 return (1);
4261 }
4262 return (0);
4263 }
4264
4265 /*
4266 * pmap_copy_page copies the specified (machine independent)
4267 * page by mapping the page into virtual memory and using
4268 * bcopy to copy the page, one machine dependent page at a
4269 * time.
4270 */
4271
4272 /*
4273 * pmap_copy_page()
4274 *
4275 * Copy one physical page into another, by mapping the pages into
4276 * hook points. The same comment regarding cachability as in
4277 * pmap_zero_page also applies here.
4278 */
4279 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
4280 void
4281 pmap_copy_page_generic(vm_paddr_t src, vm_paddr_t dst)
4282 {
4283 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4284 #ifdef DEBUG
4285 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4286
4287 if (dst_pg->md.pvh_list != NULL)
4288 panic("pmap_copy_page: dst page has mappings");
4289 #endif
4290
4291
4292 /*
4293 * Clean the source page. Hold the source page's lock for
4294 * the duration of the copy so that no other mappings can
4295 * be created while we have a potentially aliased mapping.
4296 */
4297 #if 0
4298 mtx_lock(&src_pg->md.pvh_mtx);
4299 #endif
4300 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4301
4302 /*
4303 * Map the pages into the page hook points, copy them, and purge
4304 * the cache for the appropriate page. Invalidate the TLB
4305 * as required.
4306 */
4307 mtx_lock(&cmtx);
4308 *csrc_pte = L2_S_PROTO | src |
4309 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
4310 PTE_SYNC(csrc_pte);
4311 *cdst_pte = L2_S_PROTO | dst |
4312 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) | pte_l2_s_cache_mode;
4313 PTE_SYNC(cdst_pte);
4314 cpu_tlb_flushD_SE(csrcp);
4315 cpu_tlb_flushD_SE(cdstp);
4316 cpu_cpwait();
4317 bcopy_page(csrcp, cdstp);
4318 mtx_unlock(&cmtx);
4319 cpu_dcache_inv_range(csrcp, PAGE_SIZE);
4320 #if 0
4321 mtx_lock(&src_pg->md.pvh_mtx);
4322 #endif
4323 cpu_dcache_wbinv_range(cdstp, PAGE_SIZE);
4324 }
4325 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
4326
4327 #if ARM_MMU_XSCALE == 1
4328 void
4329 pmap_copy_page_xscale(vm_paddr_t src, vm_paddr_t dst)
4330 {
4331 struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
4332 #ifdef DEBUG
4333 struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
4334
4335 if (dst_pg->md.pvh_list != NULL)
4336 panic("pmap_copy_page: dst page has mappings");
4337 #endif
4338
4339
4340 /*
4341 * Clean the source page. Hold the source page's lock for
4342 * the duration of the copy so that no other mappings can
4343 * be created while we have a potentially aliased mapping.
4344 */
4345 (void) pmap_clean_page(TAILQ_FIRST(&src_pg->md.pv_list), TRUE);
4346
4347 /*
4348 * Map the pages into the page hook points, copy them, and purge
4349 * the cache for the appropriate page. Invalidate the TLB
4350 * as required.
4351 */
4352 mtx_lock(&cmtx);
4353 *csrc_pte = L2_S_PROTO | src |
4354 L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
4355 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4356 PTE_SYNC(csrc_pte);
4357 *cdst_pte = L2_S_PROTO | dst |
4358 L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
4359 L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
4360 PTE_SYNC(cdst_pte);
4361 cpu_tlb_flushD_SE(csrcp);
4362 cpu_tlb_flushD_SE(cdstp);
4363 cpu_cpwait();
4364 bcopy_page(csrcp, cdstp);
4365 mtx_unlock(&cmtx);
4366 xscale_cache_clean_minidata();
4367 }
4368 #endif /* ARM_MMU_XSCALE == 1 */
4369
4370 void
4371 pmap_copy_page(vm_page_t src, vm_page_t dst)
4372 {
4373 cpu_dcache_wbinv_all();
4374 pmap_copy_page_func(VM_PAGE_TO_PHYS(src), VM_PAGE_TO_PHYS(dst));
4375 }
4376
4377
4378
4379
4380 /*
4381 * this routine returns true if a physical page resides
4382 * in the given pmap.
4383 */
4384 boolean_t
4385 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4386 {
4387 pv_entry_t pv;
4388 int loops = 0;
4389 int s;
4390
4391 if (m->flags & PG_FICTITIOUS)
4392 return (FALSE);
4393
4394 s = splvm();
4395
4396 /*
4397 * Not found, check current mappings returning immediately
4398 */
4399 for (pv = TAILQ_FIRST(&m->md.pv_list);
4400 pv;
4401 pv = TAILQ_NEXT(pv, pv_list)) {
4402 if (pv->pv_pmap == pmap) {
4403 splx(s);
4404 return (TRUE);
4405 }
4406 loops++;
4407 if (loops >= 16)
4408 break;
4409 }
4410 splx(s);
4411 return (FALSE);
4412 }
4413
4414
4415 /*
4416 * pmap_ts_referenced:
4417 *
4418 * Return the count of reference bits for a page, clearing all of them.
4419 */
4420 int
4421 pmap_ts_referenced(vm_page_t m)
4422 {
4423 return (pmap_clearbit(m, PVF_REF));
4424 }
4425
4426
4427 boolean_t
4428 pmap_is_modified(vm_page_t m)
4429 {
4430
4431 if (m->md.pvh_attrs & PVF_MOD)
4432 return (TRUE);
4433
4434 return(FALSE);
4435 }
4436
4437
4438 /*
4439 * Clear the modify bits on the specified physical page.
4440 */
4441 void
4442 pmap_clear_modify(vm_page_t m)
4443 {
4444
4445 if (m->md.pvh_attrs & PVF_MOD)
4446 pmap_clearbit(m, PVF_MOD);
4447 }
4448
4449
4450 /*
4451 * pmap_clear_reference:
4452 *
4453 * Clear the reference bit on the specified physical page.
4454 */
4455 void
4456 pmap_clear_reference(vm_page_t m)
4457 {
4458
4459 if (m->md.pvh_attrs & PVF_REF)
4460 pmap_clearbit(m, PVF_REF);
4461 }
4462
4463
4464 /*
4465 * perform the pmap work for mincore
4466 */
4467 int
4468 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4469 {
4470 printf("pmap_mincore()\n");
4471
4472 return (0);
4473 }
4474
4475
4476 vm_offset_t
4477 pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size)
4478 {
4479
4480 return(addr);
4481 }
4482
4483
4484 /*
4485 * Map a set of physical memory pages into the kernel virtual
4486 * address space. Return a pointer to where it is mapped. This
4487 * routine is intended to be used for mapping device memory,
4488 * NOT real memory.
4489 */
4490 void *
4491 pmap_mapdev(vm_offset_t pa, vm_size_t size)
4492 {
4493 vm_offset_t va, tmpva, offset;
4494
4495 offset = pa & PAGE_MASK;
4496 size = roundup(size, PAGE_SIZE);
4497
4498 GIANT_REQUIRED;
4499
4500 va = kmem_alloc_nofault(kernel_map, size);
4501 if (!va)
4502 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4503 for (tmpva = va; size > 0;) {
4504 pmap_kenter_internal(tmpva, pa, 0);
4505 size -= PAGE_SIZE;
4506 tmpva += PAGE_SIZE;
4507 pa += PAGE_SIZE;
4508 }
4509
4510 return ((void *)(va + offset));
4511 }
4512
4513 #define BOOTSTRAP_DEBUG
4514
4515 /*
4516 * pmap_map_section:
4517 *
4518 * Create a single section mapping.
4519 */
4520 void
4521 pmap_map_section(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4522 int prot, int cache)
4523 {
4524 pd_entry_t *pde = (pd_entry_t *) l1pt;
4525 pd_entry_t fl;
4526
4527 KASSERT(((va | pa) & L1_S_OFFSET) == 0, ("ouin2"));
4528
4529 switch (cache) {
4530 case PTE_NOCACHE:
4531 default:
4532 fl = 0;
4533 break;
4534
4535 case PTE_CACHE:
4536 fl = pte_l1_s_cache_mode;
4537 break;
4538
4539 case PTE_PAGETABLE:
4540 fl = pte_l1_s_cache_mode_pt;
4541 break;
4542 }
4543
4544 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4545 L1_S_PROT(PTE_KERNEL, prot) | fl | L1_S_DOM(PMAP_DOMAIN_KERNEL);
4546 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4547
4548 }
4549
4550 /*
4551 * pmap_link_l2pt:
4552 *
4553 * Link the L2 page table specified by "pa" into the L1
4554 * page table at the slot for "va".
4555 */
4556 void
4557 pmap_link_l2pt(vm_offset_t l1pt, vm_offset_t va, struct pv_addr *l2pv)
4558 {
4559 pd_entry_t *pde = (pd_entry_t *) l1pt, proto;
4560 u_int slot = va >> L1_S_SHIFT;
4561
4562 #ifndef ARM32_NEW_VM_LAYOUT
4563 KASSERT((va & ((L1_S_SIZE * 4) - 1)) == 0, ("blah"));
4564 KASSERT((l2pv->pv_pa & PAGE_MASK) == 0, ("ouin"));
4565 #endif
4566
4567 proto = L1_S_DOM(PMAP_DOMAIN_KERNEL) | L1_C_PROTO;
4568
4569 pde[slot + 0] = proto | (l2pv->pv_pa + 0x000);
4570 #ifdef ARM32_NEW_VM_LAYOUT
4571 PTE_SYNC(&pde[slot]);
4572 #else
4573 pde[slot + 1] = proto | (l2pv->pv_pa + 0x400);
4574 pde[slot + 2] = proto | (l2pv->pv_pa + 0x800);
4575 pde[slot + 3] = proto | (l2pv->pv_pa + 0xc00);
4576 PTE_SYNC_RANGE(&pde[slot + 0], 4);
4577 #endif
4578
4579 SLIST_INSERT_HEAD(&kernel_pt_list, l2pv, pv_list);
4580
4581
4582 }
4583
4584 /*
4585 * pmap_map_entry
4586 *
4587 * Create a single page mapping.
4588 */
4589 void
4590 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
4591 int cache)
4592 {
4593 pd_entry_t *pde = (pd_entry_t *) l1pt;
4594 pt_entry_t fl;
4595 pt_entry_t *pte;
4596
4597 KASSERT(((va | pa) & PAGE_MASK) == 0, ("ouin"));
4598
4599 switch (cache) {
4600 case PTE_NOCACHE:
4601 default:
4602 fl = 0;
4603 break;
4604
4605 case PTE_CACHE:
4606 fl = pte_l2_s_cache_mode;
4607 break;
4608
4609 case PTE_PAGETABLE:
4610 fl = pte_l2_s_cache_mode_pt;
4611 break;
4612 }
4613
4614 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4615 panic("pmap_map_entry: no L2 table for VA 0x%08x", va);
4616
4617 #ifndef ARM32_NEW_VM_LAYOUT
4618 pte = (pt_entry_t *)
4619 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
4620 #else
4621 pte = (pt_entry_t *) kernel_pt_lookup(pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4622 #endif
4623
4624 if (pte == NULL)
4625 panic("pmap_map_entry: can't find L2 table for VA 0x%08x", va);
4626
4627 #ifndef ARM32_NEW_VM_LAYOUT
4628 pte[(va >> PAGE_SHIFT) & 0x3ff] =
4629 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4630 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]);
4631 #else
4632 pte[l2pte_index(va)] =
4633 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | fl;
4634 PTE_SYNC(&pte[l2pte_index(va)]);
4635 #endif
4636 }
4637
4638 /*
4639 * pmap_map_chunk:
4640 *
4641 * Map a chunk of memory using the most efficient mappings
4642 * possible (section. large page, small page) into the
4643 * provided L1 and L2 tables at the specified virtual address.
4644 */
4645 vm_size_t
4646 pmap_map_chunk(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa,
4647 vm_size_t size, int prot, int cache)
4648 {
4649 pd_entry_t *pde = (pd_entry_t *) l1pt;
4650 pt_entry_t *pte, f1, f2s, f2l;
4651 vm_size_t resid;
4652 int i;
4653
4654 resid = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4655
4656 if (l1pt == 0)
4657 panic("pmap_map_chunk: no L1 table provided");
4658
4659 #ifdef VERBOSE_INIT_ARM
4660 printf("pmap_map_chunk: pa=0x%lx va=0x%lx size=0x%lx resid=0x%lx "
4661 "prot=0x%x cache=%d\n", pa, va, size, resid, prot, cache);
4662 #endif
4663
4664 switch (cache) {
4665 case PTE_NOCACHE:
4666 default:
4667 f1 = 0;
4668 f2l = 0;
4669 f2s = 0;
4670 break;
4671
4672 case PTE_CACHE:
4673 f1 = pte_l1_s_cache_mode;
4674 f2l = pte_l2_l_cache_mode;
4675 f2s = pte_l2_s_cache_mode;
4676 break;
4677
4678 case PTE_PAGETABLE:
4679 f1 = pte_l1_s_cache_mode_pt;
4680 f2l = pte_l2_l_cache_mode_pt;
4681 f2s = pte_l2_s_cache_mode_pt;
4682 break;
4683 }
4684
4685 size = resid;
4686
4687 while (resid > 0) {
4688 /* See if we can use a section mapping. */
4689 if (L1_S_MAPPABLE_P(va, pa, resid)) {
4690 #ifdef VERBOSE_INIT_ARM
4691 printf("S");
4692 #endif
4693 pde[va >> L1_S_SHIFT] = L1_S_PROTO | pa |
4694 L1_S_PROT(PTE_KERNEL, prot) | f1 |
4695 L1_S_DOM(PMAP_DOMAIN_KERNEL);
4696 PTE_SYNC(&pde[va >> L1_S_SHIFT]);
4697 va += L1_S_SIZE;
4698 pa += L1_S_SIZE;
4699 resid -= L1_S_SIZE;
4700 continue;
4701 }
4702
4703 /*
4704 * Ok, we're going to use an L2 table. Make sure
4705 * one is actually in the corresponding L1 slot
4706 * for the current VA.
4707 */
4708 if ((pde[va >> L1_S_SHIFT] & L1_TYPE_MASK) != L1_TYPE_C)
4709 panic("pmap_map_chunk: no L2 table for VA 0x%08x", va);
4710
4711 #ifndef ARM32_NEW_VM_LAYOUT
4712 pte = (pt_entry_t *)
4713 kernel_pt_lookup(pde[va >> L1_S_SHIFT] & L2_S_FRAME);
4714 #else
4715 pte = (pt_entry_t *) kernel_pt_lookup(
4716 pde[L1_IDX(va)] & L1_C_ADDR_MASK);
4717 #endif
4718 if (pte == NULL)
4719 panic("pmap_map_chunk: can't find L2 table for VA"
4720 "0x%08x", va);
4721 /* See if we can use a L2 large page mapping. */
4722 if (L2_L_MAPPABLE_P(va, pa, resid)) {
4723 #ifdef VERBOSE_INIT_ARM
4724 printf("L");
4725 #endif
4726 for (i = 0; i < 16; i++) {
4727 #ifndef ARM32_NEW_VM_LAYOUT
4728 pte[((va >> PAGE_SHIFT) & 0x3f0) + i] =
4729 L2_L_PROTO | pa |
4730 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4731 PTE_SYNC(&pte[((va >> PAGE_SHIFT) & 0x3f0) + i]);
4732 #else
4733 pte[l2pte_index(va) + i] =
4734 L2_L_PROTO | pa |
4735 L2_L_PROT(PTE_KERNEL, prot) | f2l;
4736 PTE_SYNC(&pte[l2pte_index(va) + i]);
4737 #endif
4738 }
4739 va += L2_L_SIZE;
4740 pa += L2_L_SIZE;
4741 resid -= L2_L_SIZE;
4742 continue;
4743 }
4744
4745 /* Use a small page mapping. */
4746 #ifdef VERBOSE_INIT_ARM
4747 printf("P");
4748 #endif
4749 #ifndef ARM32_NEW_VM_LAYOUT
4750 pte[(va >> PAGE_SHIFT) & 0x3ff] =
4751 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4752 PTE_SYNC(&pte[(va >> PAGE_SHIFT) & 0x3ff]);
4753 #else
4754 pte[l2pte_index(va)] =
4755 L2_S_PROTO | pa | L2_S_PROT(PTE_KERNEL, prot) | f2s;
4756 PTE_SYNC(&pte[l2pte_index(va)]);
4757 #endif
4758 va += PAGE_SIZE;
4759 pa += PAGE_SIZE;
4760 resid -= PAGE_SIZE;
4761 }
4762 #ifdef VERBOSE_INIT_ARM
4763 printf("\n");
4764 #endif
4765 return (size);
4766
4767 }
4768
4769 /********************** Static device map routines ***************************/
4770
4771 static const struct pmap_devmap *pmap_devmap_table;
4772
4773 /*
4774 * Register the devmap table. This is provided in case early console
4775 * initialization needs to register mappings created by bootstrap code
4776 * before pmap_devmap_bootstrap() is called.
4777 */
4778 void
4779 pmap_devmap_register(const struct pmap_devmap *table)
4780 {
4781
4782 pmap_devmap_table = table;
4783 }
4784
4785 /*
4786 * Map all of the static regions in the devmap table, and remember
4787 * the devmap table so other parts of the kernel can look up entries
4788 * later.
4789 */
4790 void
4791 pmap_devmap_bootstrap(vm_offset_t l1pt, const struct pmap_devmap *table)
4792 {
4793 int i;
4794
4795 pmap_devmap_table = table;
4796
4797 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4798 #ifdef VERBOSE_INIT_ARM
4799 printf("devmap: %08lx -> %08lx @ %08lx\n",
4800 pmap_devmap_table[i].pd_pa,
4801 pmap_devmap_table[i].pd_pa +
4802 pmap_devmap_table[i].pd_size - 1,
4803 pmap_devmap_table[i].pd_va);
4804 #endif
4805 pmap_map_chunk(l1pt, pmap_devmap_table[i].pd_va,
4806 pmap_devmap_table[i].pd_pa,
4807 pmap_devmap_table[i].pd_size,
4808 pmap_devmap_table[i].pd_prot,
4809 pmap_devmap_table[i].pd_cache);
4810 }
4811 }
4812
4813 const struct pmap_devmap *
4814 pmap_devmap_find_pa(vm_paddr_t pa, vm_size_t size)
4815 {
4816 int i;
4817
4818 if (pmap_devmap_table == NULL)
4819 return (NULL);
4820
4821 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4822 if (pa >= pmap_devmap_table[i].pd_pa &&
4823 pa + size <= pmap_devmap_table[i].pd_pa +
4824 pmap_devmap_table[i].pd_size)
4825 return (&pmap_devmap_table[i]);
4826 }
4827
4828 return (NULL);
4829 }
4830
4831 const struct pmap_devmap *
4832 pmap_devmap_find_va(vm_offset_t va, vm_size_t size)
4833 {
4834 int i;
4835
4836 if (pmap_devmap_table == NULL)
4837 return (NULL);
4838
4839 for (i = 0; pmap_devmap_table[i].pd_size != 0; i++) {
4840 if (va >= pmap_devmap_table[i].pd_va &&
4841 va + size <= pmap_devmap_table[i].pd_va +
4842 pmap_devmap_table[i].pd_size)
4843 return (&pmap_devmap_table[i]);
4844 }
4845
4846 return (NULL);
4847 }
4848
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