FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/swtch.S
1 /* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */
2
3 /*-
4 * Copyright 2003 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37 /*-
38 * Copyright (c) 1994-1998 Mark Brinicombe.
39 * Copyright (c) 1994 Brini.
40 * All rights reserved.
41 *
42 * This code is derived from software written for Brini by Mark Brinicombe
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
46 * are met:
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. All advertising materials mentioning features or use of this software
53 * must display the following acknowledgement:
54 * This product includes software developed by Brini.
55 * 4. The name of the company nor the name of the author may be used to
56 * endorse or promote products derived from this software without specific
57 * prior written permission.
58 *
59 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
60 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
61 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
62 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
63 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
64 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
65 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * SUCH DAMAGE.
70 *
71 * RiscBSD kernel project
72 *
73 * cpuswitch.S
74 *
75 * cpu switching functions
76 *
77 * Created : 15/10/94
78 *
79 */
80
81 #include "assym.s"
82
83 #include <machine/asm.h>
84 #include <machine/asmacros.h>
85 #include <machine/armreg.h>
86 __FBSDID("$FreeBSD: releng/7.3/sys/arm/arm/swtch.S 180881 2008-07-28 15:52:53Z thompsa $");
87
88
89 /*
90 * New experimental definitions of IRQdisable and IRQenable
91 * These keep FIQ's enabled since FIQ's are special.
92 */
93
94 #define DOMAIN_CLIENT 0x01
95 #define IRQdisable \
96 mrs r14, cpsr ; \
97 orr r14, r14, #(I32_bit) ; \
98 msr cpsr_c, r14 ; \
99
100 #define IRQenable \
101 mrs r14, cpsr ; \
102 bic r14, r14, #(I32_bit) ; \
103 msr cpsr_c, r14 ; \
104
105 /*
106 * These are used for switching the translation table/DACR.
107 * Since the vector page can be invalid for a short time, we must
108 * disable both regular IRQs *and* FIQs.
109 *
110 * XXX: This is not necessary if the vector table is relocated.
111 */
112 #define IRQdisableALL \
113 mrs r14, cpsr ; \
114 orr r14, r14, #(I32_bit | F32_bit) ; \
115 msr cpsr_c, r14
116
117 #define IRQenableALL \
118 mrs r14, cpsr ; \
119 bic r14, r14, #(I32_bit | F32_bit) ; \
120 msr cpsr_c, r14
121
122 .Lcurpcb:
123 .word _C_LABEL(__pcpu) + PC_CURPCB
124 .Lcpufuncs:
125 .word _C_LABEL(cpufuncs)
126 .Lblock_userspace_access:
127 .word _C_LABEL(block_userspace_access)
128 .Lcpu_do_powersave:
129 .word _C_LABEL(cpu_do_powersave)
130 .Lblocked_lock:
131 .word _C_LABEL(blocked_lock)
132 ENTRY(cpu_throw)
133 mov r5, r1
134
135 /*
136 * r5 = newtd
137 */
138
139 ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */
140
141 /* Switch to lwp0 context */
142
143 ldr r9, .Lcpufuncs
144 mov lr, pc
145 ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
146 ldr r0, [r7, #(PCB_PL1VEC)]
147 ldr r1, [r7, #(PCB_DACR)]
148 /*
149 * r0 = Pointer to L1 slot for vector_page (or NULL)
150 * r1 = lwp0's DACR
151 * r5 = lwp0
152 * r6 = exit func
153 * r7 = lwp0's PCB
154 * r9 = cpufuncs
155 */
156
157 /*
158 * Ensure the vector table is accessible by fixing up lwp0's L1
159 */
160 cmp r0, #0 /* No need to fixup vector table? */
161 ldrne r3, [r0] /* But if yes, fetch current value */
162 ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */
163 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
164 cmpne r3, r2 /* Stuffing the same value? */
165 strne r2, [r0] /* Store if not. */
166
167 #ifdef PMAP_INCLUDE_PTE_SYNC
168 /*
169 * Need to sync the cache to make sure that last store is
170 * visible to the MMU.
171 */
172 movne r1, #4
173 movne lr, pc
174 ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
175 #endif /* PMAP_INCLUDE_PTE_SYNC */
176
177 /*
178 * Note: We don't do the same optimisation as cpu_switch() with
179 * respect to avoiding flushing the TLB if we're switching to
180 * the same L1 since this process' VM space may be about to go
181 * away, so we don't want *any* turds left in the TLB.
182 */
183
184 /* Switch the memory to the new process */
185 ldr r0, [r7, #(PCB_PAGEDIR)]
186 mov lr, pc
187 ldr pc, [r9, #CF_CONTEXT_SWITCH]
188
189 /* Restore all the save registers */
190 #ifndef _ARM_ARCH_5E
191 add r1, r7, #PCB_R8
192 ldmia r1, {r8-r13}
193 #else
194 ldr r8, [r7, #(PCB_R8)]
195 ldr r9, [r7, #(PCB_R9)]
196 ldr r10, [r7, #(PCB_R10)]
197 ldr r11, [r7, #(PCB_R11)]
198 ldr r12, [r7, #(PCB_R12)]
199 ldr r13, [r7, #(PCB_SP)]
200 #endif
201
202 /* We have a new curthread now so make a note it */
203 ldr r6, .Lcurthread
204 str r5, [r6]
205
206 /* Set the new tp */
207 ldr r6, [r5, #(TD_MD + MD_TP)]
208 mov r5, #ARM_TP_ADDRESS
209 strt r6, [r5]
210
211 /* Hook in a new pcb */
212 ldr r6, .Lcurpcb
213 str r7, [r6]
214
215 ldmfd sp!, {r4-r7, pc}
216
217 ENTRY(cpu_switch)
218 stmfd sp!, {r4-r7, lr}
219 mov r6, r2 /* Save the mutex */
220
221 .Lswitch_resume:
222 /* rem: r0 = old lwp */
223 /* rem: interrupts are disabled */
224
225 #ifdef MULTIPROCESSOR
226 /* XXX use curcpu() */
227 ldr r2, .Lcpu_info_store
228 str r2, [r6, #(L_CPU)]
229 #endif
230
231 /* Process is now on a processor. */
232
233 /* We have a new curthread now so make a note it */
234 ldr r7, .Lcurthread
235 str r1, [r7]
236
237 /* Hook in a new pcb */
238 ldr r7, .Lcurpcb
239 ldr r2, [r1, #TD_PCB]
240 str r2, [r7]
241
242 /* rem: r1 = new process */
243 /* rem: interrupts are enabled */
244
245 /* Stage two : Save old context */
246
247 /* Get the user structure for the old thread. */
248 ldr r2, [r0, #(TD_PCB)]
249 mov r4, r0 /* Save the old thread. */
250
251 /* Save all the registers in the old thread's pcb */
252 #ifndef _ARM_ARCH_5E
253 add r7, r2, #(PCB_R8)
254 stmia r7, {r8-r13}
255 #else
256 strd r8, [r2, #(PCB_R8)]
257 strd r10, [r2, #(PCB_R10)]
258 strd r12, [r2, #(PCB_R12)]
259 #endif
260
261 /*
262 * NOTE: We can now use r8-r13 until it is time to restore
263 * them for the new process.
264 */
265 /* Store the old tp */
266 mov r3, #ARM_TP_ADDRESS
267 ldrt r9, [r3]
268 str r9, [r0, #(TD_MD + MD_TP)]
269
270 /* Set the new tp */
271 ldr r9, [r1, #(TD_MD + MD_TP)]
272 strt r9, [r3]
273
274 /* Get the user structure for the new process in r9 */
275 ldr r9, [r1, #(TD_PCB)]
276
277 /* r1 now free! */
278
279 mrs r3, cpsr
280 /*
281 * We can do that, since
282 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
283 */
284 orr r8, r3, #(PSR_UND32_MODE)
285 msr cpsr_c, r8
286
287 str sp, [r2, #(PCB_UND_SP)]
288
289 msr cpsr_c, r3 /* Restore the old mode */
290 /* rem: r8 = old PCB */
291 /* rem: r9 = new PCB */
292 /* rem: interrupts are enabled */
293
294 /* What else needs to be saved Only FPA stuff when that is supported */
295
296 /* Third phase : restore saved context */
297
298 /* rem: r8 = old PCB */
299 /* rem: r9 = new PCB */
300 /* rem: interrupts are enabled */
301
302 ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */
303 mov r2, #DOMAIN_CLIENT
304 cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */
305 beq .Lcs_context_switched /* Yup. Don't flush cache */
306 mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */
307 /*
308 * Get the new L1 table pointer into r11. If we're switching to
309 * an LWP with the same address space as the outgoing one, we can
310 * skip the cache purge and the TTB load.
311 *
312 * To avoid data dep stalls that would happen anyway, we try
313 * and get some useful work done in the mean time.
314 */
315 mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */
316 ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */
317
318
319 teq r10, r11 /* Same L1? */
320 cmpeq r0, r5 /* Same DACR? */
321 beq .Lcs_context_switched /* yes! */
322
323 /*
324 * Definately need to flush the cache.
325 */
326
327 ldr r1, .Lcpufuncs
328 mov lr, pc
329 ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
330 .Lcs_cache_purge_skipped:
331 /* rem: r6 = lock */
332 /* rem: r9 = new PCB */
333 /* rem: r10 = old L1 */
334 /* rem: r11 = new L1 */
335
336 mov r2, #0x00000000
337 ldr r7, [r9, #(PCB_PL1VEC)]
338
339 /*
340 * Ensure the vector table is accessible by fixing up the L1
341 */
342 cmp r7, #0 /* No need to fixup vector table? */
343 ldrne r2, [r7] /* But if yes, fetch current value */
344 ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */
345 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
346 cmpne r2, r0 /* Stuffing the same value? */
347 #ifndef PMAP_INCLUDE_PTE_SYNC
348 strne r0, [r7] /* Nope, update it */
349 #else
350 beq .Lcs_same_vector
351 str r0, [r7] /* Otherwise, update it */
352
353 /*
354 * Need to sync the cache to make sure that last store is
355 * visible to the MMU.
356 */
357 ldr r2, .Lcpufuncs
358 mov r0, r7
359 mov r1, #4
360 mov lr, pc
361 ldr pc, [r2, #CF_DCACHE_WB_RANGE]
362
363 .Lcs_same_vector:
364 #endif /* PMAP_INCLUDE_PTE_SYNC */
365
366 cmp r10, r11 /* Switching to the same L1? */
367 ldr r10, .Lcpufuncs
368 beq .Lcs_same_l1 /* Yup. */
369 /*
370 * Do a full context switch, including full TLB flush.
371 */
372 mov r0, r11
373 mov lr, pc
374 ldr pc, [r10, #CF_CONTEXT_SWITCH]
375
376 b .Lcs_context_switched
377
378 /*
379 * We're switching to a different process in the same L1.
380 * In this situation, we only need to flush the TLB for the
381 * vector_page mapping, and even then only if r7 is non-NULL.
382 */
383 .Lcs_same_l1:
384 cmp r7, #0
385 movne r0, #0 /* We *know* vector_page's VA is 0x0 */
386 movne lr, pc
387 ldrne pc, [r10, #CF_TLB_FLUSHID_SE]
388 /*
389 * We can do that, since
390 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
391 */
392
393 .Lcs_context_switched:
394
395 /* Release the old thread */
396 str r6, [r4, #TD_LOCK]
397 ldr r6, .Lblocked_lock
398 ldr r3, .Lcurthread
399 ldr r3, [r3]
400
401 1:
402 ldr r4, [r3, #TD_LOCK]
403 cmp r4, r6
404 beq 1b
405
406 /* XXXSCW: Safe to re-enable FIQs here */
407
408 /* rem: r9 = new PCB */
409
410 mrs r3, cpsr
411 /*
412 * We can do that, since
413 * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE
414 */
415 orr r2, r3, #(PSR_UND32_MODE)
416 msr cpsr_c, r2
417
418 ldr sp, [r9, #(PCB_UND_SP)]
419
420 msr cpsr_c, r3 /* Restore the old mode */
421 /* Restore all the save registers */
422 #ifndef _ARM_ARCH_5E
423 add r7, r9, #PCB_R8
424 ldmia r7, {r8-r13}
425 sub r7, r7, #PCB_R8 /* restore PCB pointer */
426 #else
427 mov r7, r9
428 ldr r8, [r7, #(PCB_R8)]
429 ldr r9, [r7, #(PCB_R9)]
430 ldr r10, [r7, #(PCB_R10)]
431 ldr r11, [r7, #(PCB_R11)]
432 ldr r12, [r7, #(PCB_R12)]
433 ldr r13, [r7, #(PCB_SP)]
434 #endif
435
436 /* rem: r6 = lock */
437 /* rem: r7 = new pcb */
438
439 #ifdef ARMFPE
440 add r0, r7, #(USER_SIZE) & 0x00ff
441 add r0, r0, #(USER_SIZE) & 0xff00
442 bl _C_LABEL(arm_fpe_core_changecontext)
443 #endif
444
445 /* rem: r5 = new lwp's proc */
446 /* rem: r6 = lock */
447 /* rem: r7 = new PCB */
448
449 .Lswitch_return:
450
451 /*
452 * Pull the registers that got pushed when either savectx() or
453 * cpu_switch() was called and return.
454 */
455 ldmfd sp!, {r4-r7, pc}
456 #ifdef DIAGNOSTIC
457 .Lswitch_bogons:
458 adr r0, .Lswitch_panic_str
459 bl _C_LABEL(panic)
460 1: nop
461 b 1b
462
463 .Lswitch_panic_str:
464 .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n"
465 #endif
466 ENTRY(savectx)
467 stmfd sp!, {r4-r7, lr}
468 /*
469 * r0 = pcb
470 */
471 /* Store all the registers in the process's pcb */
472 add r2, r0, #(PCB_R8)
473 stmia r2, {r8-r13}
474 ldmfd sp!, {r4-r7, pc}
475
476 ENTRY(fork_trampoline)
477 mov r1, r5
478 mov r2, sp
479 mov r0, r4
480 mov fp, #0
481 bl _C_LABEL(fork_exit)
482 /* Kill irq"s */
483 mrs r0, cpsr
484 orr r0, r0, #(I32_bit|F32_bit)
485 msr cpsr_c, r0
486 DO_AST
487 PULLFRAME
488
489 movs pc, lr /* Exit */
490
491 AST_LOCALS
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