The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/sys_machdep.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 1990 The Regents of the University of California.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of the University nor the names of its contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  *      from: @(#)sys_machdep.c 5.5 (Berkeley) 1/19/91
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD$");
   36 
   37 #include "opt_capsicum.h"
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/capsicum.h>
   42 #include <sys/proc.h>
   43 #include <sys/sysproto.h>
   44 #include <sys/syscall.h>
   45 #include <sys/sysent.h>
   46 #include <vm/vm.h>
   47 #include <vm/vm_extern.h>
   48 
   49 #include <machine/cpu.h>
   50 #include <machine/sysarch.h>
   51 #include <machine/machdep.h>
   52 #include <machine/vmparam.h>
   53 
   54 #ifndef _SYS_SYSPROTO_H_
   55 struct sysarch_args {
   56         int op;
   57         char *parms;
   58 };
   59 #endif
   60 
   61 /* Prototypes */
   62 static int arm32_sync_icache (struct thread *, void *);
   63 static int arm32_drain_writebuf(struct thread *, void *);
   64 
   65 #if __ARM_ARCH >= 6
   66 static int
   67 sync_icache(uintptr_t addr, size_t len)
   68 {
   69         size_t size;
   70         vm_offset_t rv;
   71 
   72         /*
   73          * Align starting address to even number because value of "1"
   74          * is used as return value for success.
   75          */
   76         len += addr & 1;
   77         addr &= ~1;
   78 
   79         /* Break whole range to pages. */
   80         do {
   81                 size = PAGE_SIZE - (addr & PAGE_MASK);
   82                 size = min(size, len);
   83                 rv = dcache_wb_pou_checked(addr, size);
   84                 if (rv == 1) /* see dcache_wb_pou_checked() */
   85                         rv = icache_inv_pou_checked(addr, size);
   86                 if (rv != 1) {
   87                         if (!useracc((void *)addr, size, VM_PROT_READ)) {
   88                                 /* Invalid access */
   89                                 return (rv);
   90                         }
   91                         /* Valid but unmapped page - skip it. */
   92                 }
   93                 len -= size;
   94                 addr += size;
   95         } while (len > 0);
   96 
   97         /* Invalidate branch predictor buffer. */
   98         bpb_inv_all();
   99         return (1);
  100 }
  101 #endif
  102 
  103 static int
  104 arm32_sync_icache(struct thread *td, void *args)
  105 {
  106         struct arm_sync_icache_args ua;
  107         int error;
  108         ksiginfo_t ksi;
  109 #if __ARM_ARCH >= 6
  110         vm_offset_t rv;
  111 #endif
  112 
  113         if ((error = copyin(args, &ua, sizeof(ua))) != 0)
  114                 return (error);
  115 
  116         if  (ua.len == 0) {
  117                 td->td_retval[0] = 0;
  118                 return (0);
  119         }
  120 
  121         /*
  122          * Validate arguments. Address and length are unsigned,
  123          * so we can use wrapped overflow check.
  124          */
  125         if (((ua.addr + ua.len) < ua.addr) ||
  126             ((ua.addr + ua.len) > VM_MAXUSER_ADDRESS)) {
  127                 ksiginfo_init_trap(&ksi);
  128                 ksi.ksi_signo = SIGSEGV;
  129                 ksi.ksi_code = SEGV_ACCERR;
  130                 ksi.ksi_addr = (void *)max(ua.addr, VM_MAXUSER_ADDRESS);
  131                 trapsignal(td, &ksi);
  132                 return (EINVAL);
  133         }
  134 
  135 #if __ARM_ARCH >= 6
  136         rv = sync_icache(ua.addr, ua.len);
  137         if (rv != 1) {
  138                 ksiginfo_init_trap(&ksi);
  139                 ksi.ksi_signo = SIGSEGV;
  140                 ksi.ksi_code = SEGV_MAPERR;
  141                 ksi.ksi_addr = (void *)rv;
  142                 trapsignal(td, &ksi);
  143                 return (EINVAL);
  144         }
  145 #else
  146         cpu_icache_sync_range(ua.addr, ua.len);
  147 #endif
  148 
  149         td->td_retval[0] = 0;
  150         return (0);
  151 }
  152 
  153 static int
  154 arm32_drain_writebuf(struct thread *td, void *args)
  155 {
  156         /* No args. */
  157 
  158 #if __ARM_ARCH < 6
  159         cpu_drain_writebuf();
  160 #else
  161         dsb();
  162         cpu_l2cache_drain_writebuf();
  163 #endif
  164         td->td_retval[0] = 0;
  165         return (0);
  166 }
  167 
  168 static int
  169 arm32_set_tp(struct thread *td, void *args)
  170 {
  171 
  172 #if __ARM_ARCH >= 6
  173         set_tls(args);
  174 #else
  175         td->td_md.md_tp = (register_t)args;
  176         *(register_t *)ARM_TP_ADDRESS = (register_t)args;
  177 #endif
  178         return (0);
  179 }
  180 
  181 static int
  182 arm32_get_tp(struct thread *td, void *args)
  183 {
  184 
  185 #if __ARM_ARCH >= 6
  186         td->td_retval[0] = (register_t)get_tls();
  187 #else
  188         td->td_retval[0] = *(register_t *)ARM_TP_ADDRESS;
  189 #endif
  190         return (0);
  191 }
  192 
  193 int
  194 sysarch(struct thread *td, struct sysarch_args *uap)
  195 {
  196         int error;
  197 
  198 #ifdef CAPABILITY_MODE
  199         /*
  200          * When adding new operations, add a new case statement here to
  201          * explicitly indicate whether or not the operation is safe to
  202          * perform in capability mode.
  203          */
  204         if (IN_CAPABILITY_MODE(td)) {
  205                 switch (uap->op) {
  206                 case ARM_SYNC_ICACHE:
  207                 case ARM_DRAIN_WRITEBUF:
  208                 case ARM_SET_TP:
  209                 case ARM_GET_TP:
  210                 case ARM_GET_VFPSTATE:
  211                         break;
  212 
  213                 default:
  214 #ifdef KTRACE
  215                         if (KTRPOINT(td, KTR_CAPFAIL))
  216                                 ktrcapfail(CAPFAIL_SYSCALL, NULL, NULL);
  217 #endif
  218                         return (ECAPMODE);
  219                 }
  220         }
  221 #endif
  222 
  223         switch (uap->op) {
  224         case ARM_SYNC_ICACHE:
  225                 error = arm32_sync_icache(td, uap->parms);
  226                 break;
  227         case ARM_DRAIN_WRITEBUF:
  228                 error = arm32_drain_writebuf(td, uap->parms);
  229                 break;
  230         case ARM_SET_TP:
  231                 error = arm32_set_tp(td, uap->parms);
  232                 break;
  233         case ARM_GET_TP:
  234                 error = arm32_get_tp(td, uap->parms);
  235                 break;
  236         case ARM_GET_VFPSTATE:
  237                 error = arm_get_vfpstate(td, uap->parms);
  238                 break;
  239         default:
  240                 error = EINVAL;
  241                 break;
  242         }
  243         return (error);
  244 }

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