The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/sys_machdep.c

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    1 /*-
    2  * Copyright (c) 1990 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by the University of
   16  *      California, Berkeley and its contributors.
   17  * 4. Neither the name of the University nor the names of its contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  *      from: @(#)sys_machdep.c 5.5 (Berkeley) 1/19/91
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD: releng/8.1/sys/arm/arm/sys_machdep.c 166695 2007-02-14 01:25:41Z kevlo $");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/proc.h>
   42 #include <sys/sysproto.h>
   43 #include <sys/syscall.h>
   44 #include <sys/sysent.h>
   45 
   46 #include <machine/sysarch.h>
   47 
   48 #ifndef _SYS_SYSPROTO_H_
   49 struct sysarch_args {
   50         int op;
   51         char *parms;
   52 };
   53 #endif
   54 
   55 /* Prototypes */
   56 static int arm32_sync_icache (struct thread *, void *);
   57 static int arm32_drain_writebuf(struct thread *, void *);
   58 
   59 static int
   60 arm32_sync_icache(struct thread *td, void *args)
   61 {
   62         struct arm_sync_icache_args ua;
   63         int error;
   64 
   65         if ((error = copyin(args, &ua, sizeof(ua))) != 0)
   66                 return (error);
   67 
   68         cpu_icache_sync_range(ua.addr, ua.len);
   69 
   70         td->td_retval[0] = 0;
   71         return (0);
   72 }
   73 
   74 static int
   75 arm32_drain_writebuf(struct thread *td, void *args)
   76 {
   77         /* No args. */
   78 
   79         td->td_retval[0] = 0;
   80         cpu_drain_writebuf();
   81         return (0);
   82 }
   83 
   84 static int
   85 arm32_set_tp(struct thread *td, void *args)
   86 {
   87 
   88         td->td_md.md_tp = args;
   89         return (0);
   90 }
   91 
   92 static int
   93 arm32_get_tp(struct thread *td, void *args)
   94 {
   95 
   96         td->td_retval[0] = (uint32_t)td->td_md.md_tp;
   97         return (0);
   98 }
   99 
  100 int
  101 sysarch(td, uap)
  102         struct thread *td;
  103         register struct sysarch_args *uap;
  104 {
  105         int error;
  106 
  107         switch (uap->op) {
  108         case ARM_SYNC_ICACHE : 
  109                 error = arm32_sync_icache(td, uap->parms);
  110                 break;
  111         case ARM_DRAIN_WRITEBUF : 
  112                 error = arm32_drain_writebuf(td, uap->parms);
  113                 break;
  114         case ARM_SET_TP:
  115                 error = arm32_set_tp(td, uap->parms);
  116                 break;
  117         case ARM_GET_TP:
  118                 error = arm32_get_tp(td, uap->parms);
  119                 break;
  120         default:
  121                 error = EINVAL;
  122                 break;
  123         }
  124         return (error);
  125 }

Cache object: 138a23846a3aedf001707e5de2a99d8d


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