The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91.c

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    1 /*-
    2  * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  */
   24 
   25 #include <sys/cdefs.h>
   26 __FBSDID("$FreeBSD: releng/6.3/sys/arm/at91/at91.c 166998 2007-02-25 23:09:51Z cognet $");
   27 
   28 #include <sys/param.h>
   29 #include <sys/systm.h>
   30 #include <sys/bus.h>
   31 #include <sys/kernel.h>
   32 #include <sys/malloc.h>
   33 #include <sys/module.h>
   34 
   35 #include <vm/vm.h>
   36 #include <vm/vm_kern.h>
   37 #include <vm/pmap.h>
   38 #include <vm/vm_page.h>
   39 #include <vm/vm_extern.h>
   40 
   41 #define _ARM32_BUS_DMA_PRIVATE
   42 #include <machine/bus.h>
   43 #include <machine/intr.h>
   44 
   45 #include <arm/at91/at91rm92reg.h>
   46 #include <arm/at91/at91var.h>
   47 
   48 static struct at91_softc *at91_softc;
   49 
   50 static int
   51 at91_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
   52     bus_space_handle_t *bshp)
   53 {
   54         vm_paddr_t pa, endpa;
   55 
   56         pa = trunc_page(bpa);
   57         if (pa >= 0xfff00000) {
   58                 *bshp = pa - 0xf0000000 + 0xd0000000;
   59                 return (0);
   60         }
   61         if (pa >= 0xdff00000)
   62                 return (0);
   63         endpa = round_page(bpa + size);
   64 
   65         *bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa);
   66                        
   67         return (0);
   68 }
   69 
   70 static void
   71 at91_bs_unmap(void *t, bus_space_handle_t h, bus_size_t size)
   72 {
   73         vm_offset_t va, endva;
   74 
   75         va = trunc_page((vm_offset_t)t);
   76         endva = va + round_page(size);
   77 
   78         /* Free the kernel virtual mapping. */
   79         kmem_free(kernel_map, va, endva - va);
   80 }
   81 
   82 static int
   83 at91_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
   84     bus_size_t size, bus_space_handle_t *nbshp)
   85 {
   86 
   87         *nbshp = bsh + offset;
   88         return (0);
   89 }
   90 
   91 static void
   92 at91_barrier(void *t, bus_space_handle_t bsh, bus_size_t size, bus_size_t b, 
   93     int a)
   94 {
   95 }
   96 
   97 bs_protos(generic);
   98 bs_protos(generic_armv4);
   99 
  100 struct bus_space at91_bs_tag = {
  101         /* cookie */
  102         (void *) 0,
  103 
  104         /* mapping/unmapping */
  105         at91_bs_map,
  106         at91_bs_unmap,
  107         at91_bs_subregion,
  108 
  109         /* allocation/deallocation */
  110         NULL,
  111         NULL,
  112 
  113         /* barrier */
  114         at91_barrier,
  115 
  116         /* read (single) */
  117         generic_bs_r_1,
  118         generic_armv4_bs_r_2,
  119         generic_bs_r_4,
  120         NULL,
  121 
  122         /* read multiple */
  123         generic_bs_rm_1,
  124         generic_armv4_bs_rm_2,
  125         generic_bs_rm_4,
  126         NULL,
  127 
  128         /* read region */
  129         generic_bs_rr_1,
  130         generic_armv4_bs_rr_2,
  131         generic_bs_rr_4,
  132         NULL,
  133 
  134         /* write (single) */
  135         generic_bs_w_1,
  136         generic_armv4_bs_w_2,
  137         generic_bs_w_4,
  138         NULL,
  139 
  140         /* write multiple */
  141         generic_bs_wm_1,
  142         generic_armv4_bs_wm_2,
  143         generic_bs_wm_4,
  144         NULL,
  145 
  146         /* write region */
  147         NULL,
  148         generic_armv4_bs_wr_2,
  149         generic_bs_wr_4,
  150         NULL,
  151 
  152         /* set multiple */
  153         NULL,
  154         NULL,
  155         NULL,
  156         NULL,
  157 
  158         /* set region */
  159         NULL,
  160         generic_armv4_bs_sr_2,
  161         generic_bs_sr_4,
  162         NULL,
  163 
  164         /* copy */
  165         NULL,
  166         generic_armv4_bs_c_2,
  167         NULL,
  168         NULL,
  169 };
  170 
  171 static int
  172 at91_probe(device_t dev)
  173 {
  174         device_set_desc(dev, "AT91RM9200 device bus");
  175         return (0);
  176 }
  177 
  178 static void
  179 at91_identify(driver_t *drv, device_t parent)
  180 {
  181         
  182         BUS_ADD_CHILD(parent, 0, "atmelarm", 0);
  183 }
  184 
  185 struct arm32_dma_range *
  186 bus_dma_get_range(void)
  187 {
  188 
  189         return (NULL);
  190 }
  191 
  192 int
  193 bus_dma_get_range_nb(void)
  194 {
  195         return (0);
  196 }
  197 
  198 extern void irq_entry(void);
  199 
  200 static void
  201 at91_add_child(device_t dev, int prio, const char *name, int unit,
  202     bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2)
  203 {
  204         device_t kid;
  205         struct at91_ivar *ivar;
  206 
  207         kid = device_add_child_ordered(dev, prio, name, unit);
  208         if (kid == NULL) {
  209             printf("Can't add child %s%d ordered\n", name, unit);
  210             return;
  211         }
  212         ivar = malloc(sizeof(*ivar), M_DEVBUF, M_WAITOK | M_ZERO);
  213         if (ivar == NULL) {
  214                 device_delete_child(dev, kid);
  215                 printf("Can't add alloc ivar\n");
  216                 return;
  217         }
  218         device_set_ivars(kid, ivar);
  219         resource_list_init(&ivar->resources);
  220         if (irq0 != -1)
  221                 bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
  222         if (irq1 != 0)
  223                 bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
  224         if (irq2 != 0)
  225                 bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
  226         if (addr != 0)
  227                 bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
  228 }
  229 
  230 struct cpu_devs
  231 {
  232         const char *name;
  233         int unit;
  234         bus_addr_t mem_base;
  235         bus_size_t mem_len;
  236         int irq0;
  237         int irq1;
  238         int irq2;
  239 };
  240 
  241 struct cpu_devs at91rm9200_devs[] =
  242 {
  243         // All the "system" devices
  244         {
  245                 "at91_st", 0,
  246                 AT91RM92_BASE + AT91RM92_ST_BASE, AT91RM92_ST_SIZE,
  247                 AT91RM92_IRQ_SYSTEM
  248         },
  249         {
  250                 "at91_pio", 0,
  251                 AT91RM92_BASE + AT91RM92_PIOA_BASE, AT91RM92_PIO_SIZE,
  252                 AT91RM92_IRQ_SYSTEM
  253         },
  254         {
  255                 "at91_pio", 1,
  256                 AT91RM92_BASE + AT91RM92_PIOB_BASE, AT91RM92_PIO_SIZE,
  257                 AT91RM92_IRQ_SYSTEM
  258         },
  259         {
  260                 "at91_pio", 2,
  261                 AT91RM92_BASE + AT91RM92_PIOC_BASE, AT91RM92_PIO_SIZE,
  262                 AT91RM92_IRQ_SYSTEM
  263         },
  264         {
  265                 "at91_pio", 3,
  266                 AT91RM92_BASE + AT91RM92_PIOD_BASE, AT91RM92_PIO_SIZE,
  267                 AT91RM92_IRQ_SYSTEM
  268         },
  269         {
  270                 "at91_pmc", 0,
  271                 AT91RM92_BASE + AT91RM92_PMC_BASE, AT91RM92_PMC_SIZE,
  272                 AT91RM92_IRQ_SYSTEM
  273         },
  274         {
  275                 "at91_aic", 0,
  276                 AT91RM92_BASE + AT91RM92_AIC_BASE, AT91RM92_AIC_SIZE,
  277                 0       // Interrupt controller has no interrupts!
  278         },
  279         {
  280                 "at91_rtc", 0,
  281                 AT91RM92_BASE + AT91RM92_RTC_BASE, AT91RM92_RTC_SIZE,
  282                 AT91RM92_IRQ_SYSTEM
  283         },
  284         {
  285                 "at91_mc", 0,
  286                 AT91RM92_BASE + AT91RM92_MC_BASE, AT91RM92_MC_SIZE,
  287                 AT91RM92_IRQ_SYSTEM
  288         },
  289 
  290         // All other devices
  291         {
  292                 "at91_tc", 0,
  293                 AT91RM92_BASE + AT91RM92_TC0_BASE, AT91RM92_TC_SIZE,
  294                 AT91RM92_IRQ_TC0, AT91RM92_IRQ_TC1, AT91RM92_IRQ_TC2
  295         },
  296         {
  297                 "at91_tc", 1,
  298                 AT91RM92_BASE + AT91RM92_TC1_BASE, AT91RM92_TC_SIZE,
  299                 AT91RM92_IRQ_TC3, AT91RM92_IRQ_TC4, AT91RM92_IRQ_TC5
  300         },
  301         {
  302                 "at91_udp", 0,
  303                 AT91RM92_BASE + AT91RM92_UDP_BASE, AT91RM92_UDP_SIZE,
  304                 AT91RM92_IRQ_UDP
  305         },
  306         {
  307                 "at91_mci", 0,
  308                 AT91RM92_BASE + AT91RM92_MCI_BASE, AT91RM92_MCI_SIZE,
  309                 AT91RM92_IRQ_MCI
  310         },
  311         {
  312                 "at91_twi", 0,
  313                 AT91RM92_BASE + AT91RM92_TWI_BASE, AT91RM92_TWI_SIZE,
  314                 AT91RM92_IRQ_TWI
  315         },
  316         {
  317                 "ate", 0,
  318                 AT91RM92_BASE + AT91RM92_EMAC_BASE, AT91RM92_EMAC_SIZE,
  319                 AT91RM92_IRQ_EMAC
  320         },
  321 #ifndef SKYEYE_WORKAROUNDS
  322         {
  323                 "uart", 0,
  324                 AT91RM92_BASE + AT91RM92_DBGU_BASE, AT91RM92_DBGU_SIZE,
  325                 AT91RM92_IRQ_SYSTEM
  326         },
  327         {
  328                 "uart", 1,
  329                 AT91RM92_BASE + AT91RM92_USART0_BASE, AT91RM92_USART_SIZE,
  330                 AT91RM92_IRQ_USART0
  331         },
  332         {
  333                 "uart", 2,
  334                 AT91RM92_BASE + AT91RM92_USART1_BASE, AT91RM92_USART_SIZE,
  335                 AT91RM92_IRQ_USART1
  336         },
  337         {
  338                 "uart", 3,
  339                 AT91RM92_BASE + AT91RM92_USART2_BASE, AT91RM92_USART_SIZE,
  340                 AT91RM92_IRQ_USART2
  341         },
  342         {
  343                 "uart", 4,
  344                 AT91RM92_BASE + AT91RM92_USART3_BASE, AT91RM92_USART_SIZE,
  345                 AT91RM92_IRQ_USART3
  346         },
  347 #else
  348         {
  349                 "uart", 0,
  350                 AT91RM92_BASE + AT91RM92_USART0_BASE, AT91RM92_USART_SIZE,
  351                 AT91RM92_IRQ_USART0
  352         },
  353 #endif
  354         {
  355                 "at91_ssc", 0,
  356                 AT91RM92_BASE + AT91RM92_SSC0_BASE, AT91RM92_SSC_SIZE,
  357                 AT91RM92_IRQ_SSC0
  358         },
  359         {
  360                 "at91_ssc", 1,
  361                 AT91RM92_BASE + AT91RM92_SSC1_BASE, AT91RM92_SSC_SIZE,
  362                 AT91RM92_IRQ_SSC1
  363         },
  364         {
  365                 "at91_ssc", 2,
  366                 AT91RM92_BASE + AT91RM92_SSC2_BASE, AT91RM92_SSC_SIZE,
  367                 AT91RM92_IRQ_SSC2
  368         },
  369         {
  370                 "at91_spi", 0,
  371                 AT91RM92_BASE + AT91RM92_SPI_BASE, AT91RM92_SPI_SIZE,
  372                 AT91RM92_IRQ_SPI
  373         },
  374         {
  375                 "ohci", 0,
  376                 AT91RM92_OHCI_BASE, AT91RM92_OHCI_SIZE,
  377                 AT91RM92_IRQ_UHP
  378         },
  379         {       0, 0, 0, 0, 0 }
  380 };
  381 
  382 static void
  383 at91_cpu_add_builtin_children(device_t dev, struct at91_softc *sc)
  384 {
  385         int i;
  386         struct cpu_devs *walker;
  387         
  388         // XXX should look at the device id in the DBGU register and
  389         // XXX based on the CPU load in these devices
  390         for (i = 0, walker = at91rm9200_devs; walker->name; i++, walker++) {
  391                 at91_add_child(dev, i, walker->name, walker->unit,
  392                     walker->mem_base, walker->mem_len, walker->irq0,
  393                     walker->irq1, walker->irq2);
  394         }
  395 }
  396 
  397 #define NORMDEV 50
  398 
  399 static int
  400 at91_attach(device_t dev)
  401 {
  402         struct at91_softc *sc = device_get_softc(dev);
  403         int i;
  404 
  405         at91_softc = sc;
  406         sc->sc_st = &at91_bs_tag;
  407         sc->sc_sh = AT91RM92_BASE;
  408         sc->dev = dev;
  409         if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE,
  410             AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0)
  411                 panic("Enable to map IRQ registers");
  412         sc->sc_irq_rman.rm_type = RMAN_ARRAY;
  413         sc->sc_irq_rman.rm_descr = "AT91RM92 IRQs";
  414         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  415         sc->sc_mem_rman.rm_descr = "AT91RM92 Memory";
  416 #if 0
  417         sc->sc_usbmem_rman.rm_type = RMAN_ARRAY;
  418         sc->sc_usbmem_rman.rm_descr = "AT91RM92 USB Memory-mapped regs";
  419 #endif
  420         if (rman_init(&sc->sc_irq_rman) != 0 ||
  421             rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
  422                 panic("at91_attach: failed to set up IRQ rman");
  423         if (rman_init(&sc->sc_mem_rman) != 0 ||
  424             rman_manage_region(&sc->sc_mem_rman, 0xdff00000ul,
  425             0xdffffffful) != 0)
  426                 panic("at91_attach: failed to set up memory rman");
  427         if (rman_manage_region(&sc->sc_mem_rman, AT91RM92_OHCI_BASE,
  428             AT91RM92_OHCI_BASE + AT91RM92_OHCI_SIZE - 1) != 0)
  429                 panic("at91_attach: failed to set up ohci memory");
  430 
  431         for (i = 0; i < 32; i++) {
  432                 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SVR + 
  433                     i * 4, i);
  434                 /* Priority. */
  435                 /* XXX: Give better priorities to IRQs */
  436                 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SMR + i * 4,
  437                     0);
  438                 if (i < 8)
  439                         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_EOICR,
  440                             1);
  441                     
  442         }
  443         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_SPU, 32);
  444         /* No debug. */
  445         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_DCR, 0);
  446         /* Disable and clear all interrupts. */
  447         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IDCR, 0xffffffff);
  448         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_ICCR, 0xffffffff);
  449 
  450         /* XXX */
  451         /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */
  452         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff);
  453         /* DIsable all interrupts for DBGU */
  454         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0x20c, 0xffffffff);
  455         /* Disable all interrupts for the SDRAM controller */
  456         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff);
  457 
  458         at91_cpu_add_builtin_children(dev, sc);
  459 
  460         bus_generic_probe(dev);
  461         bus_generic_attach(dev);
  462         enable_interrupts(I32_bit | F32_bit);
  463         return (0);
  464 }
  465 
  466 static struct resource *
  467 at91_alloc_resource(device_t dev, device_t child, int type, int *rid,
  468     u_long start, u_long end, u_long count, u_int flags)
  469 {
  470         struct at91_softc *sc = device_get_softc(dev);
  471         struct resource_list_entry *rle;
  472         struct at91_ivar *ivar = device_get_ivars(child);
  473         struct resource_list *rl = &ivar->resources;
  474 
  475         if (device_get_parent(child) != dev)
  476                 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
  477                     type, rid, start, end, count, flags));
  478         
  479         rle = resource_list_find(rl, type, *rid);
  480         if (rle == NULL)
  481                 return (NULL);
  482         if (rle->res)
  483                 panic("Resource rid %d type %d already in use", *rid, type);
  484         if (start == 0UL && end == ~0UL) {
  485                 start = rle->start;
  486                 count = ulmax(count, rle->count);
  487                 end = ulmax(rle->end, start + count - 1);
  488         }
  489         switch (type)
  490         {
  491         case SYS_RES_IRQ:
  492                 rle->res = rman_reserve_resource(&sc->sc_irq_rman,
  493                     start, end, count, flags, child);
  494                 break;
  495         case SYS_RES_MEMORY:
  496 #if 0
  497                 if (start >= 0x00300000 && start <= 0x003fffff)
  498                         rle->res = rman_reserve_resource(&sc->sc_usbmem_rman,
  499                             start, end, count, flags, child);
  500                 else
  501 #endif
  502                         rle->res = rman_reserve_resource(&sc->sc_mem_rman,
  503                             start, end, count, flags, child);
  504                 rman_set_bustag(rle->res, &at91_bs_tag);
  505                 rman_set_bushandle(rle->res, start);
  506                 break;
  507         }
  508         if (rle->res) {
  509                 rle->start = rman_get_start(rle->res);
  510                 rle->end = rman_get_end(rle->res);
  511                 rle->count = count;
  512                 rman_set_rid(rle->res, *rid);
  513         }
  514         return (rle->res);
  515 }
  516 
  517 static struct resource_list *
  518 at91_get_resource_list(device_t dev, device_t child)
  519 {
  520         struct at91_ivar *ivar;
  521 
  522         ivar = device_get_ivars(child);
  523         return (&(ivar->resources));
  524 }
  525 
  526 static int
  527 at91_release_resource(device_t dev, device_t child, int type,
  528     int rid, struct resource *r)
  529 {
  530         struct resource_list *rl;
  531         struct resource_list_entry *rle;
  532 
  533         rl = at91_get_resource_list(dev, child);
  534         if (rl == NULL)
  535                 return (EINVAL);
  536         rle = resource_list_find(rl, type, rid);
  537         if (rle == NULL)
  538                 return (EINVAL);
  539         rman_release_resource(r);
  540         rle->res = NULL;
  541         return (0);
  542 }
  543 
  544 static int
  545 at91_setup_intr(device_t dev, device_t child,
  546     struct resource *ires, int flags, driver_intr_t *intr, void *arg,
  547     void **cookiep)
  548 {
  549         struct at91_softc *sc = device_get_softc(dev);
  550 
  551         if (rman_get_start(ires) == AT91RM92_IRQ_SYSTEM && !(flags & INTR_FAST))
  552                 panic("All system interrupt ISRs must be type INTR_FAST");
  553         BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, intr, arg,
  554             cookiep);
  555         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IECR,
  556             1 << rman_get_start(ires));
  557         return (0);
  558 }
  559 
  560 static int
  561 at91_teardown_intr(device_t dev, device_t child, struct resource *res,
  562     void *cookie)
  563 {
  564         struct at91_softc *sc = device_get_softc(dev);
  565 
  566         bus_space_write_4(sc->sc_st, sc->sc_sys_sh, IC_IDCR, 
  567             1 << rman_get_start(res));
  568         return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
  569 }
  570 
  571 static int
  572 at91_activate_resource(device_t bus, device_t child, int type, int rid,
  573     struct resource *r)
  574 {
  575 #if 0
  576         u_long p;
  577         int error;
  578         
  579         if (type == SYS_RES_MEMORY) {
  580                 error = bus_space_map(rman_get_bustag(r),
  581                     rman_get_bushandle(r), rman_get_size(r), 0, &p);
  582                 if (error) 
  583                         return (error);
  584                 rman_set_bushandle(r, p);
  585         }
  586 #endif  
  587         return (rman_activate_resource(r));
  588 }
  589 
  590 static int
  591 at91_print_child(device_t dev, device_t child)
  592 {
  593         struct at91_ivar *ivars;
  594         struct resource_list *rl;
  595         int retval = 0;
  596 
  597         ivars = device_get_ivars(child);
  598         rl = &ivars->resources;
  599 
  600         retval += bus_print_child_header(dev, child);
  601 
  602         retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
  603         retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
  604         retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
  605         if (device_get_flags(dev))
  606                 retval += printf(" flags %#x", device_get_flags(dev));
  607 
  608         retval += bus_print_child_footer(dev, child);
  609 
  610         return (retval);
  611 }
  612 
  613 void
  614 arm_mask_irq(uintptr_t nb)
  615 {
  616         
  617         bus_space_write_4(at91_softc->sc_st, 
  618             at91_softc->sc_sys_sh, IC_IDCR, 1 << nb);
  619 
  620 }
  621 
  622 int
  623 arm_get_next_irq()
  624 {
  625 
  626         int status;
  627         int irq;
  628         
  629         irq = bus_space_read_4(at91_softc->sc_st,
  630             at91_softc->sc_sys_sh, IC_IVR);
  631         status = bus_space_read_4(at91_softc->sc_st,
  632             at91_softc->sc_sys_sh, IC_ISR);
  633         if (status == 0) {
  634                 bus_space_write_4(at91_softc->sc_st,
  635                     at91_softc->sc_sys_sh, IC_EOICR, 1);
  636                 return (-1);
  637         }
  638         return (irq);
  639 }
  640 
  641 void
  642 arm_unmask_irq(uintptr_t nb)
  643 {
  644         
  645         bus_space_write_4(at91_softc->sc_st, 
  646         at91_softc->sc_sys_sh, IC_IECR, 1 << nb);
  647         bus_space_write_4(at91_softc->sc_st, at91_softc->sc_sys_sh,
  648             IC_EOICR, 0);
  649 
  650 }
  651 
  652 static device_method_t at91_methods[] = {
  653         DEVMETHOD(device_probe, at91_probe),
  654         DEVMETHOD(device_attach, at91_attach),
  655         DEVMETHOD(device_identify, at91_identify),
  656 
  657         DEVMETHOD(bus_alloc_resource, at91_alloc_resource),
  658         DEVMETHOD(bus_setup_intr, at91_setup_intr),
  659         DEVMETHOD(bus_teardown_intr, at91_teardown_intr),
  660         DEVMETHOD(bus_activate_resource, at91_activate_resource),
  661         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  662         DEVMETHOD(bus_get_resource_list,at91_get_resource_list),
  663         DEVMETHOD(bus_set_resource,     bus_generic_rl_set_resource),
  664         DEVMETHOD(bus_get_resource,     bus_generic_rl_get_resource),
  665         DEVMETHOD(bus_release_resource, at91_release_resource),
  666         DEVMETHOD(bus_print_child,      at91_print_child),
  667 
  668         {0, 0},
  669 };
  670 
  671 static driver_t at91_driver = {
  672         "atmelarm",
  673         at91_methods,
  674         sizeof(struct at91_softc),
  675 };
  676 static devclass_t at91_devclass;
  677 
  678 DRIVER_MODULE(atmelarm, nexus, at91_driver, at91_devclass, 0, 0);

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