1 /*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD: releng/9.0/sys/arm/at91/at91_machdep.c 223562 2011-06-26 10:07:48Z kevlo $");
48
49 #define _ARM32_BUS_DMA_PRIVATE
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/sysproto.h>
53 #include <sys/signalvar.h>
54 #include <sys/imgact.h>
55 #include <sys/kernel.h>
56 #include <sys/ktr.h>
57 #include <sys/linker.h>
58 #include <sys/lock.h>
59 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/pcpu.h>
62 #include <sys/proc.h>
63 #include <sys/ptrace.h>
64 #include <sys/cons.h>
65 #include <sys/bio.h>
66 #include <sys/bus.h>
67 #include <sys/buf.h>
68 #include <sys/exec.h>
69 #include <sys/kdb.h>
70 #include <sys/msgbuf.h>
71 #include <machine/reg.h>
72 #include <machine/cpu.h>
73
74 #include <vm/vm.h>
75 #include <vm/pmap.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_page.h>
78 #include <vm/vm_pager.h>
79 #include <vm/vm_map.h>
80 #include <machine/pmap.h>
81 #include <machine/vmparam.h>
82 #include <machine/pcb.h>
83 #include <machine/undefined.h>
84 #include <machine/machdep.h>
85 #include <machine/metadata.h>
86 #include <machine/armreg.h>
87 #include <machine/bus.h>
88 #include <sys/reboot.h>
89
90 #include <arm/at91/at91board.h>
91 #include <arm/at91/at91var.h>
92 #include <arm/at91/at91rm92reg.h>
93 #include <arm/at91/at91sam9g20reg.h>
94
95 #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
96 #define KERNEL_PT_KERN 1
97 #define KERNEL_PT_KERN_NUM 22
98 #define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
99 #define KERNEL_PT_AFKERNEL_NUM 5
100
101 /* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
102 #define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
103
104 /* Define various stack sizes in pages */
105 #define IRQ_STACK_SIZE 1
106 #define ABT_STACK_SIZE 1
107 #define UND_STACK_SIZE 1
108
109 extern u_int data_abort_handler_address;
110 extern u_int prefetch_abort_handler_address;
111 extern u_int undefined_handler_address;
112
113 struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
114
115 extern void *_end;
116
117 extern int *end;
118
119 struct pcpu __pcpu;
120 struct pcpu *pcpup = &__pcpu;
121
122 /* Physical and virtual addresses for some global pages */
123
124 vm_paddr_t phys_avail[10];
125 vm_paddr_t dump_avail[4];
126 vm_offset_t physical_pages;
127
128 struct pv_addr systempage;
129 struct pv_addr msgbufpv;
130 struct pv_addr irqstack;
131 struct pv_addr undstack;
132 struct pv_addr abtstack;
133 struct pv_addr kernelstack;
134
135 static void *boot_arg1;
136 static void *boot_arg2;
137
138 static struct trapframe proc0_tf;
139
140 /* Static device mappings. */
141 const struct pmap_devmap at91_devmap[] = {
142 /*
143 * Map the on-board devices VA == PA so that we can access them
144 * with the MMU on or off.
145 */
146 {
147 /*
148 * This at least maps the interrupt controller, the UART
149 * and the timer. Other devices should use newbus to
150 * map their memory anyway.
151 */
152 0xdff00000,
153 0xfff00000,
154 0x00100000,
155 VM_PROT_READ|VM_PROT_WRITE,
156 PTE_NOCACHE,
157 },
158 /* We can't just map the OHCI registers VA == PA, because
159 * AT91xx_xxx_BASE belongs to the userland address space.
160 * We could just choose a different virtual address, but a better
161 * solution would probably be to just use pmap_mapdev() to allocate
162 * KVA, as we don't need the OHCI controller before the vm
163 * initialization is done. However, the AT91 resource allocation
164 * system doesn't know how to use pmap_mapdev() yet.
165 * Care must be taken to ensure PA and VM address do not overlap
166 * between entries.
167 */
168 {
169 /*
170 * Add the ohci controller, and anything else that might be
171 * on this chip select for a VA/PA mapping.
172 */
173 /* Internal Memory 1MB */
174 AT91RM92_OHCI_BASE,
175 AT91RM92_OHCI_PA_BASE,
176 0x00100000,
177 VM_PROT_READ|VM_PROT_WRITE,
178 PTE_NOCACHE,
179 },
180 {
181 /* CompactFlash controller. Portion of EBI CS4 1MB */
182 AT91RM92_CF_BASE,
183 AT91RM92_CF_PA_BASE,
184 0x00100000,
185 VM_PROT_READ|VM_PROT_WRITE,
186 PTE_NOCACHE,
187 },
188 /* The next two should be good for the 9260, 9261 and 9G20 since
189 * addresses mapping is the same. */
190 {
191 /* Internal Memory 1MB */
192 AT91SAM9G20_OHCI_BASE,
193 AT91SAM9G20_OHCI_PA_BASE,
194 0x00100000,
195 VM_PROT_READ|VM_PROT_WRITE,
196 PTE_NOCACHE,
197 },
198 {
199 /* EBI CS3 256MB */
200 AT91SAM9G20_NAND_BASE,
201 AT91SAM9G20_NAND_PA_BASE,
202 AT91SAM9G20_NAND_SIZE,
203 VM_PROT_READ|VM_PROT_WRITE,
204 PTE_NOCACHE,
205 },
206 { 0, 0, 0, 0, 0, }
207 };
208
209 long
210 at91_ramsize(void)
211 {
212 uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
213 uint32_t cr, mr;
214 int banks, rows, cols, bw;
215
216 if (at91_is_rm92()) {
217 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
218 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
219 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
220 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
221 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
222 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
223 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
224 } else {
225 /* This should be good for the 9260, 9261 and 9G20 as addresses
226 * and registers are the same */
227 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
228 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
229 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
230 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
231 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
232 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
233 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
234 }
235
236 return (1 << (cols + rows + banks + bw));
237 }
238
239 void *
240 initarm(void *arg, void *arg2)
241 {
242 struct pv_addr kernel_l1pt;
243 struct pv_addr dpcpu;
244 int loop, i;
245 u_int l1pagetable;
246 vm_offset_t freemempos;
247 vm_offset_t afterkern;
248 uint32_t memsize;
249 vm_offset_t lastaddr;
250
251 boot_arg1 = arg;
252 boot_arg2 = arg2;
253 set_cpufuncs();
254 lastaddr = fake_preload_metadata();
255 pcpu_init(pcpup, 0, sizeof(struct pcpu));
256 PCPU_SET(curthread, &thread0);
257
258 /* Do basic tuning, hz etc */
259 init_param1();
260
261 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
262 /* Define a macro to simplify memory allocation */
263 #define valloc_pages(var, np) \
264 alloc_pages((var).pv_va, (np)); \
265 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
266
267 #define alloc_pages(var, np) \
268 (var) = freemempos; \
269 freemempos += (np * PAGE_SIZE); \
270 memset((char *)(var), 0, ((np) * PAGE_SIZE));
271
272 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
273 freemempos += PAGE_SIZE;
274 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
275 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
276 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
277 valloc_pages(kernel_pt_table[loop],
278 L2_TABLE_SIZE / PAGE_SIZE);
279 } else {
280 kernel_pt_table[loop].pv_va = freemempos -
281 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
282 L2_TABLE_SIZE_REAL;
283 kernel_pt_table[loop].pv_pa =
284 kernel_pt_table[loop].pv_va - KERNVIRTADDR +
285 KERNPHYSADDR;
286 }
287 i++;
288 }
289 /*
290 * Allocate a page for the system page mapped to V0x00000000
291 * This page will just contain the system vectors and can be
292 * shared by all processes.
293 */
294 valloc_pages(systempage, 1);
295
296 /* Allocate dynamic per-cpu area. */
297 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
298 dpcpu_init((void *)dpcpu.pv_va, 0);
299
300 /* Allocate stacks for all modes */
301 valloc_pages(irqstack, IRQ_STACK_SIZE);
302 valloc_pages(abtstack, ABT_STACK_SIZE);
303 valloc_pages(undstack, UND_STACK_SIZE);
304 valloc_pages(kernelstack, KSTACK_PAGES);
305 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
306
307 /*
308 * Now we start construction of the L1 page table
309 * We start by mapping the L2 page tables into the L1.
310 * This means that we can replace L1 mappings later on if necessary
311 */
312 l1pagetable = kernel_l1pt.pv_va;
313
314 /* Map the L2 pages tables in the L1 page table */
315 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
316 &kernel_pt_table[KERNEL_PT_SYS]);
317 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
318 pmap_link_l2pt(l1pagetable, KERNBASE + i * L1_S_SIZE,
319 &kernel_pt_table[KERNEL_PT_KERN + i]);
320 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
321 (((uint32_t)lastaddr - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
322 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
323 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE - 1));
324 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
325 pmap_link_l2pt(l1pagetable, afterkern + i * L1_S_SIZE,
326 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
327 }
328
329 /* Map the vector page. */
330 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
331 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
332
333 /* Map the DPCPU pages */
334 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
335 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
336
337 /* Map the stack pages */
338 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
339 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
340 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
341 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
342 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
343 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
344 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
345 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
346
347 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
348 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
349 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
350 msgbufsize, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
351
352 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
353 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
354 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
355 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
356 }
357
358 pmap_devmap_bootstrap(l1pagetable, at91_devmap);
359 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
360 setttb(kernel_l1pt.pv_pa);
361 cpu_tlb_flushID();
362 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
363
364 cninit();
365
366 /* Get chip id so device drivers know about differences */
367 at91_chip_id = *(volatile uint32_t *)
368 (AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
369
370 memsize = board_init();
371 physmem = memsize / PAGE_SIZE;
372
373 /*
374 * Pages were allocated during the secondary bootstrap for the
375 * stacks for different CPU modes.
376 * We must now set the r13 registers in the different CPU modes to
377 * point to these stacks.
378 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
379 * of the stack memory.
380 */
381 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
382 set_stackptr(PSR_IRQ32_MODE,
383 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
384 set_stackptr(PSR_ABT32_MODE,
385 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
386 set_stackptr(PSR_UND32_MODE,
387 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
388
389 /*
390 * We must now clean the cache again....
391 * Cleaning may be done by reading new data to displace any
392 * dirty data in the cache. This will have happened in setttb()
393 * but since we are boot strapping the addresses used for the read
394 * may have just been remapped and thus the cache could be out
395 * of sync. A re-clean after the switch will cure this.
396 * After booting there are no gross relocations of the kernel thus
397 * this problem will not occur after initarm().
398 */
399 cpu_idcache_wbinv_all();
400
401 /* Set stack for exception handlers */
402
403 data_abort_handler_address = (u_int)data_abort_handler;
404 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
405 undefined_handler_address = (u_int)undefinedinstruction_bounce;
406 undefined_init();
407
408 proc_linkup0(&proc0, &thread0);
409 thread0.td_kstack = kernelstack.pv_va;
410 thread0.td_pcb = (struct pcb *)
411 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
412 thread0.td_pcb->pcb_flags = 0;
413 thread0.td_frame = &proc0_tf;
414 pcpup->pc_curpcb = thread0.td_pcb;
415
416 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
417
418 pmap_curmaxkvaddr = afterkern + L1_S_SIZE * (KERNEL_PT_KERN_NUM - 1);
419
420 /*
421 * ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
422 * calling pmap_bootstrap.
423 */
424 dump_avail[0] = PHYSADDR;
425 dump_avail[1] = PHYSADDR + memsize;
426 dump_avail[2] = 0;
427 dump_avail[3] = 0;
428
429 pmap_bootstrap(freemempos,
430 KERNVIRTADDR + 3 * memsize,
431 &kernel_l1pt);
432 msgbufp = (void*)msgbufpv.pv_va;
433 msgbufinit(msgbufp, msgbufsize);
434 mutex_init();
435
436 i = 0;
437 #if PHYSADDR != KERNPHYSADDR
438 phys_avail[i++] = PHYSADDR;
439 phys_avail[i++] = KERNPHYSADDR;
440 #endif
441 phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
442 phys_avail[i++] = PHYSADDR + memsize;
443 phys_avail[i++] = 0;
444 phys_avail[i++] = 0;
445 init_param2(physmem);
446 kdb_init();
447 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
448 sizeof(struct pcb)));
449 }
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