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sys/arm/at91/at91_mci.c
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1 /*- 2 * Copyright (c) 2006 Bernd Walter. All rights reserved. 3 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bio.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/kthread.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 #include <sys/time.h> 45 #include <sys/timetc.h> 46 #include <sys/watchdog.h> 47 48 #include <machine/bus.h> 49 #include <machine/cpu.h> 50 #include <machine/cpufunc.h> 51 #include <machine/resource.h> 52 #include <machine/frame.h> 53 #include <machine/intr.h> 54 #include <arm/at91/at91rm92reg.h> 55 #include <arm/at91/at91var.h> 56 #include <arm/at91/at91_mcireg.h> 57 #include <arm/at91/at91_pdcreg.h> 58 #include <dev/mmc/bridge.h> 59 #include <dev/mmc/mmcreg.h> 60 #include <dev/mmc/mmcbrvar.h> 61 62 #include "mmcbr_if.h" 63 64 #define BBSZ 512 65 66 struct at91_mci_softc { 67 void *intrhand; /* Interrupt handle */ 68 device_t dev; 69 int flags; 70 #define CMD_STARTED 1 71 #define STOP_STARTED 2 72 struct resource *irq_res; /* IRQ resource */ 73 struct resource *mem_res; /* Memory resource */ 74 struct mtx sc_mtx; 75 bus_dma_tag_t dmatag; 76 bus_dmamap_t map; 77 int mapped; 78 struct mmc_host host; 79 int wire4; 80 int bus_busy; 81 struct mmc_request *req; 82 struct mmc_command *curcmd; 83 char bounce_buffer[BBSZ]; 84 }; 85 86 static inline uint32_t 87 RD4(struct at91_mci_softc *sc, bus_size_t off) 88 { 89 return bus_read_4(sc->mem_res, off); 90 } 91 92 static inline void 93 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) 94 { 95 bus_write_4(sc->mem_res, off, val); 96 } 97 98 /* bus entry points */ 99 static int at91_mci_probe(device_t dev); 100 static int at91_mci_attach(device_t dev); 101 static int at91_mci_detach(device_t dev); 102 static void at91_mci_intr(void *); 103 104 /* helper routines */ 105 static int at91_mci_activate(device_t dev); 106 static void at91_mci_deactivate(device_t dev); 107 108 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 109 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 110 #define AT91_MCI_LOCK_INIT(_sc) \ 111 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 112 "mci", MTX_DEF) 113 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 114 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 115 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 116 117 static void 118 at91_mci_pdc_disable(struct at91_mci_softc *sc) 119 { 120 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 121 WR4(sc, PDC_RPR, 0); 122 WR4(sc, PDC_RCR, 0); 123 WR4(sc, PDC_RNPR, 0); 124 WR4(sc, PDC_RNCR, 0); 125 WR4(sc, PDC_TPR, 0); 126 WR4(sc, PDC_TCR, 0); 127 WR4(sc, PDC_TNPR, 0); 128 WR4(sc, PDC_TNCR, 0); 129 } 130 131 static void 132 at91_mci_init(device_t dev) 133 { 134 struct at91_mci_softc *sc = device_get_softc(dev); 135 136 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */ 137 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ 138 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1); 139 WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX 140 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */ 141 } 142 143 static void 144 at91_mci_fini(device_t dev) 145 { 146 struct at91_mci_softc *sc = device_get_softc(dev); 147 148 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ 149 at91_mci_pdc_disable(sc); 150 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* Put the device into reset */ 151 } 152 153 static int 154 at91_mci_probe(device_t dev) 155 { 156 157 device_set_desc(dev, "MCI mmc/sd host bridge"); 158 return (0); 159 } 160 161 static int 162 at91_mci_attach(device_t dev) 163 { 164 struct at91_mci_softc *sc = device_get_softc(dev); 165 int err; 166 device_t child; 167 168 sc->dev = dev; 169 err = at91_mci_activate(dev); 170 if (err) 171 goto out; 172 173 AT91_MCI_LOCK_INIT(sc); 174 175 /* 176 * Allocate DMA tags and maps 177 */ 178 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 179 BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, 1, MAXPHYS, 180 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); 181 if (err != 0) 182 goto out; 183 184 err = bus_dmamap_create(sc->dmatag, 0, &sc->map); 185 if (err != 0) 186 goto out; 187 188 at91_mci_fini(dev); 189 at91_mci_init(dev); 190 191 /* 192 * Activate the interrupt 193 */ 194 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 195 NULL, at91_mci_intr, sc, &sc->intrhand); 196 if (err) { 197 AT91_MCI_LOCK_DESTROY(sc); 198 goto out; 199 } 200 sc->host.f_min = 375000; 201 sc->host.f_max = 30000000; 202 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 203 sc->host.caps = MMC_CAP_4_BIT_DATA; 204 child = device_add_child(dev, "mmc", 0); 205 device_set_ivars(dev, &sc->host); 206 err = bus_generic_attach(dev); 207 out:; 208 if (err) 209 at91_mci_deactivate(dev); 210 return (err); 211 } 212 213 static int 214 at91_mci_detach(device_t dev) 215 { 216 at91_mci_fini(dev); 217 at91_mci_deactivate(dev); 218 return (EBUSY); /* XXX */ 219 } 220 221 static int 222 at91_mci_activate(device_t dev) 223 { 224 struct at91_mci_softc *sc; 225 int rid; 226 227 sc = device_get_softc(dev); 228 rid = 0; 229 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 230 RF_ACTIVE); 231 if (sc->mem_res == NULL) 232 goto errout; 233 rid = 0; 234 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 235 RF_ACTIVE); 236 if (sc->irq_res == NULL) 237 goto errout; 238 return (0); 239 errout: 240 at91_mci_deactivate(dev); 241 return (ENOMEM); 242 } 243 244 static void 245 at91_mci_deactivate(device_t dev) 246 { 247 struct at91_mci_softc *sc; 248 249 sc = device_get_softc(dev); 250 if (sc->intrhand) 251 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 252 sc->intrhand = 0; 253 bus_generic_detach(sc->dev); 254 if (sc->mem_res) 255 bus_release_resource(dev, SYS_RES_IOPORT, 256 rman_get_rid(sc->mem_res), sc->mem_res); 257 sc->mem_res = 0; 258 if (sc->irq_res) 259 bus_release_resource(dev, SYS_RES_IRQ, 260 rman_get_rid(sc->irq_res), sc->irq_res); 261 sc->irq_res = 0; 262 return; 263 } 264 265 static void 266 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 267 { 268 if (error != 0) 269 return; 270 *(bus_addr_t *)arg = segs[0].ds_addr; 271 } 272 273 static int 274 at91_mci_update_ios(device_t brdev, device_t reqdev) 275 { 276 uint32_t at91_master_clock = AT91C_MASTER_CLOCK; 277 struct at91_mci_softc *sc; 278 struct mmc_host *host; 279 struct mmc_ios *ios; 280 uint32_t clkdiv; 281 282 sc = device_get_softc(brdev); 283 host = &sc->host; 284 ios = &host->ios; 285 // bus mode? 286 if (ios->clock == 0) { 287 WR4(sc, MCI_CR, MCI_CR_MCIDIS); 288 clkdiv = 0; 289 } else { 290 WR4(sc, MCI_CR, MCI_CR_MCIEN); 291 if ((at91_master_clock % (ios->clock * 2)) == 0) 292 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 293 else 294 clkdiv = (at91_master_clock / ios->clock) / 2; 295 } 296 if (ios->bus_width == bus_width_4 && sc->wire4) 297 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS); 298 else 299 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS); 300 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv); 301 #if 0 302 if (sc->vcc_pin) { 303 if (sc->power_mode == MMC_POWER_OFF) 304 gpio_set(sc->vcc_pin, 0); 305 else 306 gpio_set(sc->vcc_pin, 1); 307 } 308 #endif 309 return (0); 310 } 311 312 static void 313 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd) 314 { 315 uint32_t cmdr, ier = 0, mr; 316 uint32_t *src, *dst; 317 int i; 318 struct mmc_data *data; 319 struct mmc_request *req; 320 size_t block_size = 1 << 9; // Fixed, per mmc/sd spec for 2GB cards 321 void *vaddr; 322 bus_addr_t paddr; 323 324 sc->curcmd = cmd; 325 data = cmd->data; 326 cmdr = cmd->opcode; 327 req = cmd->mrq; 328 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) 329 cmdr |= MCI_CMDR_RSPTYP_NO; 330 else { 331 /* Allow big timeout for responses */ 332 cmdr |= MCI_CMDR_MAXLAT; 333 if (cmd->flags & MMC_RSP_136) 334 cmdr |= MCI_CMDR_RSPTYP_136; 335 else 336 cmdr |= MCI_CMDR_RSPTYP_48; 337 } 338 if (cmd->opcode == MMC_STOP_TRANSMISSION) 339 cmdr |= MCI_CMDR_TRCMD_STOP; 340 if (sc->host.ios.bus_mode == opendrain) 341 cmdr |= MCI_CMDR_OPDCMD; 342 if (!data) { 343 // The no data case is fairly simple 344 at91_mci_pdc_disable(sc); 345 // printf("CMDR %x ARGR %x\n", cmdr, cmd->arg); 346 WR4(sc, MCI_ARGR, cmd->arg); 347 WR4(sc, MCI_CMDR, cmdr); 348 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY); 349 return; 350 } 351 if (data->flags & MMC_DATA_READ) 352 cmdr |= MCI_CMDR_TRDIR; 353 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) 354 cmdr |= MCI_CMDR_TRCMD_START; 355 if (data->flags & MMC_DATA_STREAM) 356 cmdr |= MCI_CMDR_TRTYP_STREAM; 357 if (data->flags & MMC_DATA_MULTI) 358 cmdr |= MCI_CMDR_TRTYP_MULTIPLE; 359 // Set block size and turn on PDC mode for dma xfer and disable 360 // PDC until we're ready. 361 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN; 362 WR4(sc, MCI_MR, mr | (block_size << 16) | MCI_MR_PDCMODE); 363 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 364 if (cmdr & MCI_CMDR_TRCMD_START) { 365 if (cmdr & MCI_CMDR_TRDIR) 366 vaddr = cmd->data->data; 367 else { 368 if (data->len != BBSZ) 369 panic("Write multiblock write support"); 370 vaddr = sc->bounce_buffer; 371 src = (uint32_t *)cmd->data->data; 372 dst = (uint32_t *)vaddr; 373 for (i = 0; i < data->len / 4; i++) 374 dst[i] = bswap32(src[i]); 375 } 376 data->xfer_len = 0; 377 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len, 378 at91_mci_getaddr, &paddr, 0) != 0) { 379 if (req->cmd->flags & STOP_STARTED) 380 req->stop->error = MMC_ERR_NO_MEMORY; 381 else 382 req->cmd->error = MMC_ERR_NO_MEMORY; 383 sc->req = NULL; 384 sc->curcmd = NULL; 385 req->done(req); 386 return; 387 } 388 sc->mapped++; 389 if (cmdr & MCI_CMDR_TRDIR) { 390 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD); 391 WR4(sc, PDC_RPR, paddr); 392 WR4(sc, PDC_RCR, data->len / 4); 393 ier = MCI_SR_ENDRX; 394 } else { 395 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE); 396 WR4(sc, PDC_TPR, paddr); 397 WR4(sc, PDC_TCR, data->len / 4); 398 ier = MCI_SR_TXBUFE; 399 } 400 } 401 // printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg); 402 WR4(sc, MCI_ARGR, cmd->arg); 403 if (cmdr & MCI_CMDR_TRCMD_START) { 404 if (cmdr & MCI_CMDR_TRDIR) { 405 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN); 406 WR4(sc, MCI_CMDR, cmdr); 407 } else { 408 WR4(sc, MCI_CMDR, cmdr); 409 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN); 410 } 411 } 412 WR4(sc, MCI_IER, MCI_SR_ERROR | ier); 413 } 414 415 static void 416 at91_mci_start(struct at91_mci_softc *sc) 417 { 418 struct mmc_request *req; 419 420 req = sc->req; 421 if (req == NULL) 422 return; 423 // assert locked 424 if (!(sc->flags & CMD_STARTED)) { 425 sc->flags |= CMD_STARTED; 426 // printf("Starting CMD\n"); 427 at91_mci_start_cmd(sc, req->cmd); 428 return; 429 } 430 if (!(sc->flags & STOP_STARTED) && req->stop) { 431 // printf("Starting Stop\n"); 432 sc->flags |= STOP_STARTED; 433 at91_mci_start_cmd(sc, req->stop); 434 return; 435 } 436 /* We must be done -- bad idea to do this while locked? */ 437 sc->req = NULL; 438 sc->curcmd = NULL; 439 req->done(req); 440 } 441 442 static int 443 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 444 { 445 struct at91_mci_softc *sc = device_get_softc(brdev); 446 447 AT91_MCI_LOCK(sc); 448 // XXX do we want to be able to queue up multiple commands? 449 // XXX sounds like a good idea, but all protocols are sync, so 450 // XXX maybe the idea is naive... 451 if (sc->req != NULL) { 452 AT91_MCI_UNLOCK(sc); 453 return EBUSY; 454 } 455 sc->req = req; 456 sc->flags = 0; 457 at91_mci_start(sc); 458 AT91_MCI_UNLOCK(sc); 459 return (0); 460 } 461 462 static int 463 at91_mci_get_ro(device_t brdev, device_t reqdev) 464 { 465 return (0); 466 } 467 468 static int 469 at91_mci_acquire_host(device_t brdev, device_t reqdev) 470 { 471 struct at91_mci_softc *sc = device_get_softc(brdev); 472 int err = 0; 473 474 AT91_MCI_LOCK(sc); 475 while (sc->bus_busy) 476 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5); 477 sc->bus_busy++; 478 AT91_MCI_UNLOCK(sc); 479 return (err); 480 } 481 482 static int 483 at91_mci_release_host(device_t brdev, device_t reqdev) 484 { 485 struct at91_mci_softc *sc = device_get_softc(brdev); 486 487 AT91_MCI_LOCK(sc); 488 sc->bus_busy--; 489 wakeup(sc); 490 AT91_MCI_UNLOCK(sc); 491 return (0); 492 } 493 494 static void 495 at91_mci_read_done(struct at91_mci_softc *sc) 496 { 497 uint32_t *walker; 498 struct mmc_command *cmd; 499 int i, len; 500 501 cmd = sc->curcmd; 502 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->dmatag, sc->map); 504 sc->mapped--; 505 walker = (uint32_t *)cmd->data->data; 506 len = cmd->data->len / 4; 507 for (i = 0; i < len; i++) 508 walker[i] = bswap32(walker[i]); 509 // Finish up the sequence... 510 WR4(sc, MCI_IDR, MCI_SR_ENDRX); 511 WR4(sc, MCI_IER, MCI_SR_RXBUFF); 512 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 513 } 514 515 static void 516 at91_mci_xmit_done(struct at91_mci_softc *sc) 517 { 518 // Finish up the sequence... 519 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 520 WR4(sc, MCI_IDR, MCI_SR_TXBUFE); 521 WR4(sc, MCI_IER, MCI_SR_NOTBUSY); 522 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTWRITE); 523 bus_dmamap_unload(sc->dmatag, sc->map); 524 sc->mapped--; 525 } 526 527 static void 528 at91_mci_intr(void *arg) 529 { 530 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg; 531 uint32_t sr; 532 int i, done = 0; 533 struct mmc_command *cmd; 534 535 AT91_MCI_LOCK(sc); 536 sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR); 537 // printf("i 0x%x\n", sr); 538 cmd = sc->curcmd; 539 if (sr & MCI_SR_ERROR) { 540 // Ignore CRC errors on CMD2 and ACMD47, per relevant standards 541 if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND || 542 cmd->opcode == ACMD_SD_SEND_OP_COND)) 543 cmd->error = MMC_ERR_NONE; 544 else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE)) 545 cmd->error = MMC_ERR_TIMEOUT; 546 else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE)) 547 cmd->error = MMC_ERR_BADCRC; 548 else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE)) 549 cmd->error = MMC_ERR_FIFO; 550 else 551 cmd->error = MMC_ERR_FAILED; 552 done = 1; 553 if (sc->mapped && cmd->error) { 554 bus_dmamap_unload(sc->dmatag, sc->map); 555 sc->mapped--; 556 } 557 } else { 558 if (sr & MCI_SR_TXBUFE) { 559 // printf("TXBUFE\n"); 560 at91_mci_xmit_done(sc); 561 } 562 if (sr & MCI_SR_RXBUFF) { 563 // printf("RXBUFF\n"); 564 WR4(sc, MCI_IDR, MCI_SR_RXBUFF); 565 WR4(sc, MCI_IER, MCI_SR_CMDRDY); 566 } 567 if (sr & MCI_SR_ENDTX) { 568 // printf("ENDTX\n"); 569 } 570 if (sr & MCI_SR_ENDRX) { 571 // printf("ENDRX\n"); 572 at91_mci_read_done(sc); 573 } 574 if (sr & MCI_SR_NOTBUSY) { 575 // printf("NOTBUSY\n"); 576 WR4(sc, MCI_IDR, MCI_SR_NOTBUSY); 577 WR4(sc, MCI_IER, MCI_SR_CMDRDY); 578 } 579 if (sr & MCI_SR_DTIP) { 580 // printf("Data transfer in progress\n"); 581 } 582 if (sr & MCI_SR_BLKE) { 583 // printf("Block transfer end\n"); 584 } 585 if (sr & MCI_SR_TXRDY) { 586 // printf("Ready to transmit\n"); 587 } 588 if (sr & MCI_SR_RXRDY) { 589 // printf("Ready to receive\n"); 590 } 591 if (sr & MCI_SR_CMDRDY) { 592 // printf("Command ready\n"); 593 done = 1; 594 cmd->error = MMC_ERR_NONE; 595 } 596 } 597 if (done) { 598 WR4(sc, MCI_IDR, 0xffffffff); 599 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) { 600 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); 601 i++) { 602 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4); 603 // printf("RSPR[%d] = %x\n", i, cmd->resp[i]); 604 } 605 } 606 at91_mci_start(sc); 607 } 608 AT91_MCI_UNLOCK(sc); 609 } 610 611 static int 612 at91_mci_read_ivar(device_t bus, device_t child, int which, u_char *result) 613 { 614 struct at91_mci_softc *sc = device_get_softc(bus); 615 616 switch (which) { 617 default: 618 return (EINVAL); 619 case MMCBR_IVAR_BUS_MODE: 620 *(int *)result = sc->host.ios.bus_mode; 621 break; 622 case MMCBR_IVAR_BUS_WIDTH: 623 *(int *)result = sc->host.ios.bus_width; 624 break; 625 case MMCBR_IVAR_CHIP_SELECT: 626 *(int *)result = sc->host.ios.chip_select; 627 break; 628 case MMCBR_IVAR_CLOCK: 629 *(int *)result = sc->host.ios.clock; 630 break; 631 case MMCBR_IVAR_F_MIN: 632 *(int *)result = sc->host.f_min; 633 break; 634 case MMCBR_IVAR_F_MAX: 635 *(int *)result = sc->host.f_max; 636 break; 637 case MMCBR_IVAR_HOST_OCR: 638 *(int *)result = sc->host.host_ocr; 639 break; 640 case MMCBR_IVAR_MODE: 641 *(int *)result = sc->host.mode; 642 break; 643 case MMCBR_IVAR_OCR: 644 *(int *)result = sc->host.ocr; 645 break; 646 case MMCBR_IVAR_POWER_MODE: 647 *(int *)result = sc->host.ios.power_mode; 648 break; 649 case MMCBR_IVAR_VDD: 650 *(int *)result = sc->host.ios.vdd; 651 break; 652 case MMCBR_IVAR_MAX_DATA: 653 *(int *)result = 1; 654 break; 655 } 656 return (0); 657 } 658 659 static int 660 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 661 { 662 struct at91_mci_softc *sc = device_get_softc(bus); 663 664 switch (which) { 665 default: 666 return (EINVAL); 667 case MMCBR_IVAR_BUS_MODE: 668 sc->host.ios.bus_mode = value; 669 break; 670 case MMCBR_IVAR_BUS_WIDTH: 671 sc->host.ios.bus_width = value; 672 break; 673 case MMCBR_IVAR_CHIP_SELECT: 674 sc->host.ios.chip_select = value; 675 break; 676 case MMCBR_IVAR_CLOCK: 677 sc->host.ios.clock = value; 678 break; 679 case MMCBR_IVAR_MODE: 680 sc->host.mode = value; 681 break; 682 case MMCBR_IVAR_OCR: 683 sc->host.ocr = value; 684 break; 685 case MMCBR_IVAR_POWER_MODE: 686 sc->host.ios.power_mode = value; 687 break; 688 case MMCBR_IVAR_VDD: 689 sc->host.ios.vdd = value; 690 break; 691 /* These are read-only */ 692 case MMCBR_IVAR_HOST_OCR: 693 case MMCBR_IVAR_F_MIN: 694 case MMCBR_IVAR_F_MAX: 695 case MMCBR_IVAR_MAX_DATA: 696 return (EINVAL); 697 } 698 return (0); 699 } 700 701 static device_method_t at91_mci_methods[] = { 702 /* device_if */ 703 DEVMETHOD(device_probe, at91_mci_probe), 704 DEVMETHOD(device_attach, at91_mci_attach), 705 DEVMETHOD(device_detach, at91_mci_detach), 706 707 /* Bus interface */ 708 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar), 709 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar), 710 711 /* mmcbr_if */ 712 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios), 713 DEVMETHOD(mmcbr_request, at91_mci_request), 714 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro), 715 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host), 716 DEVMETHOD(mmcbr_release_host, at91_mci_release_host), 717 718 {0, 0}, 719 }; 720 721 static driver_t at91_mci_driver = { 722 "at91_mci", 723 at91_mci_methods, 724 sizeof(struct at91_mci_softc), 725 }; 726 static devclass_t at91_mci_devclass; 727 728 729 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, 0, 0);
Cache object: 392efe13eaeac5e6037b0be45fc62b74
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