Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/at91/at91_mci.c
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1 /*- 2 * Copyright (c) 2006 Bernd Walter. All rights reserved. 3 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bio.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/kthread.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/resource.h> 44 #include <sys/rman.h> 45 #include <sys/time.h> 46 #include <sys/timetc.h> 47 #include <sys/watchdog.h> 48 49 #include <machine/bus.h> 50 #include <machine/cpu.h> 51 #include <machine/cpufunc.h> 52 #include <machine/resource.h> 53 #include <machine/frame.h> 54 #include <machine/intr.h> 55 #include <arm/at91/at91rm92reg.h> 56 #include <arm/at91/at91var.h> 57 #include <arm/at91/at91_mcireg.h> 58 #include <arm/at91/at91_pdcreg.h> 59 #include <dev/mmc/bridge.h> 60 #include <dev/mmc/mmcreg.h> 61 #include <dev/mmc/mmcbrvar.h> 62 63 #include "mmcbr_if.h" 64 65 #define BBSZ 512 66 67 struct at91_mci_softc { 68 void *intrhand; /* Interrupt handle */ 69 device_t dev; 70 int sc_cap; 71 #define CAP_HAS_4WIRE 1 /* Has 4 wire bus */ 72 #define CAP_NEEDS_BOUNCE 2 /* broken hardware needing bounce */ 73 int flags; 74 #define CMD_STARTED 1 75 #define STOP_STARTED 2 76 struct resource *irq_res; /* IRQ resource */ 77 struct resource *mem_res; /* Memory resource */ 78 struct mtx sc_mtx; 79 bus_dma_tag_t dmatag; 80 bus_dmamap_t map; 81 int mapped; 82 struct mmc_host host; 83 int bus_busy; 84 struct mmc_request *req; 85 struct mmc_command *curcmd; 86 char bounce_buffer[BBSZ]; 87 }; 88 89 static inline uint32_t 90 RD4(struct at91_mci_softc *sc, bus_size_t off) 91 { 92 return bus_read_4(sc->mem_res, off); 93 } 94 95 static inline void 96 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) 97 { 98 bus_write_4(sc->mem_res, off, val); 99 } 100 101 /* bus entry points */ 102 static int at91_mci_probe(device_t dev); 103 static int at91_mci_attach(device_t dev); 104 static int at91_mci_detach(device_t dev); 105 static void at91_mci_intr(void *); 106 107 /* helper routines */ 108 static int at91_mci_activate(device_t dev); 109 static void at91_mci_deactivate(device_t dev); 110 111 #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 112 #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 113 #define AT91_MCI_LOCK_INIT(_sc) \ 114 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 115 "mci", MTX_DEF) 116 #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 117 #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 118 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 119 120 static void 121 at91_mci_pdc_disable(struct at91_mci_softc *sc) 122 { 123 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 124 WR4(sc, PDC_RPR, 0); 125 WR4(sc, PDC_RCR, 0); 126 WR4(sc, PDC_RNPR, 0); 127 WR4(sc, PDC_RNCR, 0); 128 WR4(sc, PDC_TPR, 0); 129 WR4(sc, PDC_TCR, 0); 130 WR4(sc, PDC_TNPR, 0); 131 WR4(sc, PDC_TNCR, 0); 132 } 133 134 static void 135 at91_mci_init(device_t dev) 136 { 137 struct at91_mci_softc *sc = device_get_softc(dev); 138 139 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */ 140 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ 141 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1); 142 WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX 143 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */ 144 } 145 146 static void 147 at91_mci_fini(device_t dev) 148 { 149 struct at91_mci_softc *sc = device_get_softc(dev); 150 151 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ 152 at91_mci_pdc_disable(sc); 153 WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* Put the device into reset */ 154 } 155 156 static int 157 at91_mci_probe(device_t dev) 158 { 159 160 device_set_desc(dev, "MCI mmc/sd host bridge"); 161 return (0); 162 } 163 164 static int 165 at91_mci_attach(device_t dev) 166 { 167 struct at91_mci_softc *sc = device_get_softc(dev); 168 int err; 169 device_t child; 170 171 sc->dev = dev; 172 sc->sc_cap = CAP_NEEDS_BOUNCE; 173 err = at91_mci_activate(dev); 174 if (err) 175 goto out; 176 177 AT91_MCI_LOCK_INIT(sc); 178 179 /* 180 * Allocate DMA tags and maps 181 */ 182 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 183 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, 1, 184 MAXPHYS, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); 185 if (err != 0) 186 goto out; 187 188 err = bus_dmamap_create(sc->dmatag, 0, &sc->map); 189 if (err != 0) 190 goto out; 191 192 at91_mci_fini(dev); 193 at91_mci_init(dev); 194 195 /* 196 * Activate the interrupt 197 */ 198 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 199 NULL, at91_mci_intr, sc, &sc->intrhand); 200 if (err) { 201 AT91_MCI_LOCK_DESTROY(sc); 202 goto out; 203 } 204 sc->host.f_min = 375000; 205 sc->host.f_max = at91_master_clock / 2; /* Typically 30MHz */ 206 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 207 if (sc->sc_cap & CAP_HAS_4WIRE) 208 sc->host.caps = MMC_CAP_4_BIT_DATA; 209 else 210 sc->host.caps = 0; 211 child = device_add_child(dev, "mmc", 0); 212 device_set_ivars(dev, &sc->host); 213 err = bus_generic_attach(dev); 214 out: 215 if (err) 216 at91_mci_deactivate(dev); 217 return (err); 218 } 219 220 static int 221 at91_mci_detach(device_t dev) 222 { 223 at91_mci_fini(dev); 224 at91_mci_deactivate(dev); 225 return (EBUSY); /* XXX */ 226 } 227 228 static int 229 at91_mci_activate(device_t dev) 230 { 231 struct at91_mci_softc *sc; 232 int rid; 233 234 sc = device_get_softc(dev); 235 rid = 0; 236 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 237 RF_ACTIVE); 238 if (sc->mem_res == NULL) 239 goto errout; 240 rid = 0; 241 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 242 RF_ACTIVE); 243 if (sc->irq_res == NULL) 244 goto errout; 245 return (0); 246 errout: 247 at91_mci_deactivate(dev); 248 return (ENOMEM); 249 } 250 251 static void 252 at91_mci_deactivate(device_t dev) 253 { 254 struct at91_mci_softc *sc; 255 256 sc = device_get_softc(dev); 257 if (sc->intrhand) 258 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 259 sc->intrhand = 0; 260 bus_generic_detach(sc->dev); 261 if (sc->mem_res) 262 bus_release_resource(dev, SYS_RES_IOPORT, 263 rman_get_rid(sc->mem_res), sc->mem_res); 264 sc->mem_res = 0; 265 if (sc->irq_res) 266 bus_release_resource(dev, SYS_RES_IRQ, 267 rman_get_rid(sc->irq_res), sc->irq_res); 268 sc->irq_res = 0; 269 return; 270 } 271 272 static void 273 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 274 { 275 if (error != 0) 276 return; 277 *(bus_addr_t *)arg = segs[0].ds_addr; 278 } 279 280 static int 281 at91_mci_update_ios(device_t brdev, device_t reqdev) 282 { 283 struct at91_mci_softc *sc; 284 struct mmc_host *host; 285 struct mmc_ios *ios; 286 uint32_t clkdiv; 287 288 sc = device_get_softc(brdev); 289 host = &sc->host; 290 ios = &host->ios; 291 // bus mode? 292 if (ios->clock == 0) { 293 WR4(sc, MCI_CR, MCI_CR_MCIDIS); 294 clkdiv = 0; 295 } else { 296 WR4(sc, MCI_CR, MCI_CR_MCIEN); 297 if ((at91_master_clock % (ios->clock * 2)) == 0) 298 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 299 else 300 clkdiv = (at91_master_clock / ios->clock) / 2; 301 } 302 if (ios->bus_width == bus_width_4) 303 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS); 304 else 305 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS); 306 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv); 307 /* Do we need a settle time here? */ 308 /* XXX We need to turn the device on/off here with a GPIO pin */ 309 return (0); 310 } 311 312 static void 313 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd) 314 { 315 uint32_t cmdr, ier = 0, mr; 316 uint32_t *src, *dst; 317 int i; 318 struct mmc_data *data; 319 struct mmc_request *req; 320 void *vaddr; 321 bus_addr_t paddr; 322 323 sc->curcmd = cmd; 324 data = cmd->data; 325 cmdr = cmd->opcode; 326 req = cmd->mrq; 327 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) 328 cmdr |= MCI_CMDR_RSPTYP_NO; 329 else { 330 /* Allow big timeout for responses */ 331 cmdr |= MCI_CMDR_MAXLAT; 332 if (cmd->flags & MMC_RSP_136) 333 cmdr |= MCI_CMDR_RSPTYP_136; 334 else 335 cmdr |= MCI_CMDR_RSPTYP_48; 336 } 337 if (cmd->opcode == MMC_STOP_TRANSMISSION) 338 cmdr |= MCI_CMDR_TRCMD_STOP; 339 if (sc->host.ios.bus_mode == opendrain) 340 cmdr |= MCI_CMDR_OPDCMD; 341 if (!data) { 342 // The no data case is fairly simple 343 at91_mci_pdc_disable(sc); 344 // printf("CMDR %x ARGR %x\n", cmdr, cmd->arg); 345 WR4(sc, MCI_ARGR, cmd->arg); 346 WR4(sc, MCI_CMDR, cmdr); 347 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY); 348 return; 349 } 350 if (data->flags & MMC_DATA_READ) 351 cmdr |= MCI_CMDR_TRDIR; 352 if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) 353 cmdr |= MCI_CMDR_TRCMD_START; 354 if (data->flags & MMC_DATA_STREAM) 355 cmdr |= MCI_CMDR_TRTYP_STREAM; 356 if (data->flags & MMC_DATA_MULTI) 357 cmdr |= MCI_CMDR_TRTYP_MULTIPLE; 358 // Set block size and turn on PDC mode for dma xfer and disable 359 // PDC until we're ready. 360 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN; 361 WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE); 362 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 363 if (cmdr & MCI_CMDR_TRCMD_START) { 364 if (cmdr & MCI_CMDR_TRDIR) 365 vaddr = cmd->data->data; 366 else { 367 if (sc->sc_cap & CAP_NEEDS_BOUNCE) { 368 vaddr = sc->bounce_buffer; 369 src = (uint32_t *)cmd->data->data; 370 dst = (uint32_t *)vaddr; 371 for (i = 0; i < data->len / 4; i++) 372 dst[i] = bswap32(src[i]); 373 } 374 else 375 vaddr = cmd->data->data; 376 } 377 data->xfer_len = 0; 378 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len, 379 at91_mci_getaddr, &paddr, 0) != 0) { 380 if (req->cmd->flags & STOP_STARTED) 381 req->stop->error = MMC_ERR_NO_MEMORY; 382 else 383 req->cmd->error = MMC_ERR_NO_MEMORY; 384 sc->req = NULL; 385 sc->curcmd = NULL; 386 req->done(req); 387 return; 388 } 389 sc->mapped++; 390 if (cmdr & MCI_CMDR_TRDIR) { 391 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD); 392 WR4(sc, PDC_RPR, paddr); 393 WR4(sc, PDC_RCR, data->len / 4); 394 ier = MCI_SR_ENDRX; 395 } else { 396 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE); 397 WR4(sc, PDC_TPR, paddr); 398 WR4(sc, PDC_TCR, data->len / 4); 399 ier = MCI_SR_TXBUFE; 400 } 401 } 402 // printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg); 403 WR4(sc, MCI_ARGR, cmd->arg); 404 if (cmdr & MCI_CMDR_TRCMD_START) { 405 if (cmdr & MCI_CMDR_TRDIR) { 406 WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN); 407 WR4(sc, MCI_CMDR, cmdr); 408 } else { 409 WR4(sc, MCI_CMDR, cmdr); 410 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN); 411 } 412 } 413 WR4(sc, MCI_IER, MCI_SR_ERROR | ier); 414 } 415 416 static void 417 at91_mci_start(struct at91_mci_softc *sc) 418 { 419 struct mmc_request *req; 420 421 req = sc->req; 422 if (req == NULL) 423 return; 424 // assert locked 425 if (!(sc->flags & CMD_STARTED)) { 426 sc->flags |= CMD_STARTED; 427 // printf("Starting CMD\n"); 428 at91_mci_start_cmd(sc, req->cmd); 429 return; 430 } 431 if (!(sc->flags & STOP_STARTED) && req->stop) { 432 // printf("Starting Stop\n"); 433 sc->flags |= STOP_STARTED; 434 at91_mci_start_cmd(sc, req->stop); 435 return; 436 } 437 /* We must be done -- bad idea to do this while locked? */ 438 sc->req = NULL; 439 sc->curcmd = NULL; 440 req->done(req); 441 } 442 443 static int 444 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req) 445 { 446 struct at91_mci_softc *sc = device_get_softc(brdev); 447 448 AT91_MCI_LOCK(sc); 449 // XXX do we want to be able to queue up multiple commands? 450 // XXX sounds like a good idea, but all protocols are sync, so 451 // XXX maybe the idea is naive... 452 if (sc->req != NULL) { 453 AT91_MCI_UNLOCK(sc); 454 return EBUSY; 455 } 456 sc->req = req; 457 sc->flags = 0; 458 at91_mci_start(sc); 459 AT91_MCI_UNLOCK(sc); 460 return (0); 461 } 462 463 static int 464 at91_mci_get_ro(device_t brdev, device_t reqdev) 465 { 466 return (0); 467 } 468 469 static int 470 at91_mci_acquire_host(device_t brdev, device_t reqdev) 471 { 472 struct at91_mci_softc *sc = device_get_softc(brdev); 473 int err = 0; 474 475 AT91_MCI_LOCK(sc); 476 while (sc->bus_busy) 477 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5); 478 sc->bus_busy++; 479 AT91_MCI_UNLOCK(sc); 480 return (err); 481 } 482 483 static int 484 at91_mci_release_host(device_t brdev, device_t reqdev) 485 { 486 struct at91_mci_softc *sc = device_get_softc(brdev); 487 488 AT91_MCI_LOCK(sc); 489 sc->bus_busy--; 490 wakeup(sc); 491 AT91_MCI_UNLOCK(sc); 492 return (0); 493 } 494 495 static void 496 at91_mci_read_done(struct at91_mci_softc *sc) 497 { 498 uint32_t *walker; 499 struct mmc_command *cmd; 500 int i, len; 501 502 cmd = sc->curcmd; 503 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD); 504 bus_dmamap_unload(sc->dmatag, sc->map); 505 sc->mapped--; 506 if (sc->sc_cap & CAP_NEEDS_BOUNCE) { 507 walker = (uint32_t *)cmd->data->data; 508 len = cmd->data->len / 4; 509 for (i = 0; i < len; i++) 510 walker[i] = bswap32(walker[i]); 511 } 512 // Finish up the sequence... 513 WR4(sc, MCI_IDR, MCI_SR_ENDRX); 514 WR4(sc, MCI_IER, MCI_SR_RXBUFF); 515 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 516 } 517 518 static void 519 at91_mci_xmit_done(struct at91_mci_softc *sc) 520 { 521 // Finish up the sequence... 522 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); 523 WR4(sc, MCI_IDR, MCI_SR_TXBUFE); 524 WR4(sc, MCI_IER, MCI_SR_NOTBUSY); 525 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTWRITE); 526 bus_dmamap_unload(sc->dmatag, sc->map); 527 sc->mapped--; 528 } 529 530 static void 531 at91_mci_intr(void *arg) 532 { 533 struct at91_mci_softc *sc = (struct at91_mci_softc*)arg; 534 uint32_t sr; 535 int i, done = 0; 536 struct mmc_command *cmd; 537 538 AT91_MCI_LOCK(sc); 539 sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR); 540 // printf("i 0x%x\n", sr); 541 cmd = sc->curcmd; 542 if (sr & MCI_SR_ERROR) { 543 // Ignore CRC errors on CMD2 and ACMD47, per relevant standards 544 if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND || 545 cmd->opcode == ACMD_SD_SEND_OP_COND)) 546 cmd->error = MMC_ERR_NONE; 547 else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE)) 548 cmd->error = MMC_ERR_TIMEOUT; 549 else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE)) 550 cmd->error = MMC_ERR_BADCRC; 551 else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE)) 552 cmd->error = MMC_ERR_FIFO; 553 else 554 cmd->error = MMC_ERR_FAILED; 555 done = 1; 556 if (sc->mapped && cmd->error) { 557 bus_dmamap_unload(sc->dmatag, sc->map); 558 sc->mapped--; 559 } 560 } else { 561 if (sr & MCI_SR_TXBUFE) { 562 // printf("TXBUFE\n"); 563 at91_mci_xmit_done(sc); 564 } 565 if (sr & MCI_SR_RXBUFF) { 566 // printf("RXBUFF\n"); 567 WR4(sc, MCI_IDR, MCI_SR_RXBUFF); 568 WR4(sc, MCI_IER, MCI_SR_CMDRDY); 569 } 570 if (sr & MCI_SR_ENDTX) { 571 // printf("ENDTX\n"); 572 } 573 if (sr & MCI_SR_ENDRX) { 574 // printf("ENDRX\n"); 575 at91_mci_read_done(sc); 576 } 577 if (sr & MCI_SR_NOTBUSY) { 578 // printf("NOTBUSY\n"); 579 WR4(sc, MCI_IDR, MCI_SR_NOTBUSY); 580 WR4(sc, MCI_IER, MCI_SR_CMDRDY); 581 } 582 if (sr & MCI_SR_DTIP) { 583 // printf("Data transfer in progress\n"); 584 } 585 if (sr & MCI_SR_BLKE) { 586 // printf("Block transfer end\n"); 587 } 588 if (sr & MCI_SR_TXRDY) { 589 // printf("Ready to transmit\n"); 590 } 591 if (sr & MCI_SR_RXRDY) { 592 // printf("Ready to receive\n"); 593 } 594 if (sr & MCI_SR_CMDRDY) { 595 // printf("Command ready\n"); 596 done = 1; 597 cmd->error = MMC_ERR_NONE; 598 } 599 } 600 if (done) { 601 WR4(sc, MCI_IDR, 0xffffffff); 602 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) { 603 for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); 604 i++) { 605 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4); 606 // printf("RSPR[%d] = %x\n", i, cmd->resp[i]); 607 } 608 } 609 at91_mci_start(sc); 610 } 611 AT91_MCI_UNLOCK(sc); 612 } 613 614 static int 615 at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 616 { 617 struct at91_mci_softc *sc = device_get_softc(bus); 618 619 switch (which) { 620 default: 621 return (EINVAL); 622 case MMCBR_IVAR_BUS_MODE: 623 *(int *)result = sc->host.ios.bus_mode; 624 break; 625 case MMCBR_IVAR_BUS_WIDTH: 626 *(int *)result = sc->host.ios.bus_width; 627 break; 628 case MMCBR_IVAR_CHIP_SELECT: 629 *(int *)result = sc->host.ios.chip_select; 630 break; 631 case MMCBR_IVAR_CLOCK: 632 *(int *)result = sc->host.ios.clock; 633 break; 634 case MMCBR_IVAR_F_MIN: 635 *(int *)result = sc->host.f_min; 636 break; 637 case MMCBR_IVAR_F_MAX: 638 *(int *)result = sc->host.f_max; 639 break; 640 case MMCBR_IVAR_HOST_OCR: 641 *(int *)result = sc->host.host_ocr; 642 break; 643 case MMCBR_IVAR_MODE: 644 *(int *)result = sc->host.mode; 645 break; 646 case MMCBR_IVAR_OCR: 647 *(int *)result = sc->host.ocr; 648 break; 649 case MMCBR_IVAR_POWER_MODE: 650 *(int *)result = sc->host.ios.power_mode; 651 break; 652 case MMCBR_IVAR_VDD: 653 *(int *)result = sc->host.ios.vdd; 654 break; 655 case MMCBR_IVAR_CAPS: 656 *(int *)result = sc->host.caps; 657 break; 658 case MMCBR_IVAR_MAX_DATA: 659 *(int *)result = 1; 660 break; 661 } 662 return (0); 663 } 664 665 static int 666 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 667 { 668 struct at91_mci_softc *sc = device_get_softc(bus); 669 670 switch (which) { 671 default: 672 return (EINVAL); 673 case MMCBR_IVAR_BUS_MODE: 674 sc->host.ios.bus_mode = value; 675 break; 676 case MMCBR_IVAR_BUS_WIDTH: 677 sc->host.ios.bus_width = value; 678 break; 679 case MMCBR_IVAR_CHIP_SELECT: 680 sc->host.ios.chip_select = value; 681 break; 682 case MMCBR_IVAR_CLOCK: 683 sc->host.ios.clock = value; 684 break; 685 case MMCBR_IVAR_MODE: 686 sc->host.mode = value; 687 break; 688 case MMCBR_IVAR_OCR: 689 sc->host.ocr = value; 690 break; 691 case MMCBR_IVAR_POWER_MODE: 692 sc->host.ios.power_mode = value; 693 break; 694 case MMCBR_IVAR_VDD: 695 sc->host.ios.vdd = value; 696 break; 697 /* These are read-only */ 698 case MMCBR_IVAR_CAPS: 699 case MMCBR_IVAR_HOST_OCR: 700 case MMCBR_IVAR_F_MIN: 701 case MMCBR_IVAR_F_MAX: 702 case MMCBR_IVAR_MAX_DATA: 703 return (EINVAL); 704 } 705 return (0); 706 } 707 708 static device_method_t at91_mci_methods[] = { 709 /* device_if */ 710 DEVMETHOD(device_probe, at91_mci_probe), 711 DEVMETHOD(device_attach, at91_mci_attach), 712 DEVMETHOD(device_detach, at91_mci_detach), 713 714 /* Bus interface */ 715 DEVMETHOD(bus_read_ivar, at91_mci_read_ivar), 716 DEVMETHOD(bus_write_ivar, at91_mci_write_ivar), 717 718 /* mmcbr_if */ 719 DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios), 720 DEVMETHOD(mmcbr_request, at91_mci_request), 721 DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro), 722 DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host), 723 DEVMETHOD(mmcbr_release_host, at91_mci_release_host), 724 725 {0, 0}, 726 }; 727 728 static driver_t at91_mci_driver = { 729 "at91_mci", 730 at91_mci_methods, 731 sizeof(struct at91_mci_softc), 732 }; 733 static devclass_t at91_mci_devclass; 734 735 736 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, 0, 0);
Cache object: 55e3bead966a533db7062bd5eb28ab23
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