The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_mci.c

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    1 /*-
    2  * Copyright (c) 2006 Bernd Walter.  All rights reserved.
    3  * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
    4  * Copyright (c) 2010 Greg Ansley.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/9.0/sys/arm/at91/at91_mci.c 213496 2010-10-06 22:25:21Z cognet $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bio.h>
   34 #include <sys/bus.h>
   35 #include <sys/conf.h>
   36 #include <sys/endian.h>
   37 #include <sys/kernel.h>
   38 #include <sys/kthread.h>
   39 #include <sys/lock.h>
   40 #include <sys/malloc.h>
   41 #include <sys/module.h>
   42 #include <sys/mutex.h>
   43 #include <sys/queue.h>
   44 #include <sys/resource.h>
   45 #include <sys/rman.h>
   46 #include <sys/sysctl.h>
   47 #include <sys/time.h>
   48 #include <sys/timetc.h>
   49 #include <sys/watchdog.h>
   50 
   51 #include <machine/bus.h>
   52 #include <machine/cpu.h>
   53 #include <machine/cpufunc.h>
   54 #include <machine/resource.h>
   55 #include <machine/frame.h>
   56 #include <machine/intr.h>
   57 
   58 #include <arm/at91/at91var.h>
   59 #include <arm/at91/at91_mcireg.h>
   60 #include <arm/at91/at91_pdcreg.h>
   61 
   62 #include <dev/mmc/bridge.h>
   63 #include <dev/mmc/mmcreg.h>
   64 #include <dev/mmc/mmcbrvar.h>
   65 
   66 #include "mmcbr_if.h"
   67 
   68 #include "opt_at91.h"
   69 
   70 #define BBSZ    512
   71 
   72 struct at91_mci_softc {
   73         void *intrhand;                 /* Interrupt handle */
   74         device_t dev;
   75         int sc_cap;
   76 #define CAP_HAS_4WIRE           1       /* Has 4 wire bus */
   77 #define CAP_NEEDS_BYTESWAP      2       /* broken hardware needing bounce */
   78         int flags;
   79         int has_4wire;
   80 #define CMD_STARTED     1
   81 #define STOP_STARTED    2
   82         struct resource *irq_res;       /* IRQ resource */
   83         struct resource *mem_res;       /* Memory resource */
   84         struct mtx sc_mtx;
   85         bus_dma_tag_t dmatag;
   86         bus_dmamap_t map;
   87         int mapped;
   88         struct mmc_host host;
   89         int bus_busy;
   90         struct mmc_request *req;
   91         struct mmc_command *curcmd;
   92         char bounce_buffer[BBSZ];
   93 };
   94 
   95 static inline uint32_t
   96 RD4(struct at91_mci_softc *sc, bus_size_t off)
   97 {
   98         return (bus_read_4(sc->mem_res, off));
   99 }
  100 
  101 static inline void
  102 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
  103 {
  104         bus_write_4(sc->mem_res, off, val);
  105 }
  106 
  107 /* bus entry points */
  108 static int at91_mci_probe(device_t dev);
  109 static int at91_mci_attach(device_t dev);
  110 static int at91_mci_detach(device_t dev);
  111 static void at91_mci_intr(void *);
  112 
  113 /* helper routines */
  114 static int at91_mci_activate(device_t dev);
  115 static void at91_mci_deactivate(device_t dev);
  116 
  117 #define AT91_MCI_LOCK(_sc)              mtx_lock(&(_sc)->sc_mtx)
  118 #define AT91_MCI_UNLOCK(_sc)            mtx_unlock(&(_sc)->sc_mtx)
  119 #define AT91_MCI_LOCK_INIT(_sc) \
  120         mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
  121             "mci", MTX_DEF)
  122 #define AT91_MCI_LOCK_DESTROY(_sc)      mtx_destroy(&_sc->sc_mtx);
  123 #define AT91_MCI_ASSERT_LOCKED(_sc)     mtx_assert(&_sc->sc_mtx, MA_OWNED);
  124 #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
  125 
  126 static void
  127 at91_mci_pdc_disable(struct at91_mci_softc *sc)
  128 {
  129         WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
  130         WR4(sc, PDC_RPR, 0);
  131         WR4(sc, PDC_RCR, 0);
  132         WR4(sc, PDC_RNPR, 0);
  133         WR4(sc, PDC_RNCR, 0);
  134         WR4(sc, PDC_TPR, 0);
  135         WR4(sc, PDC_TCR, 0);
  136         WR4(sc, PDC_TNPR, 0);
  137         WR4(sc, PDC_TNCR, 0);
  138 }
  139 
  140 static void
  141 at91_mci_init(device_t dev)
  142 {
  143         struct at91_mci_softc *sc = device_get_softc(dev);
  144 
  145         WR4(sc, MCI_CR, MCI_CR_MCIEN);          /* Enable controller */
  146         WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
  147         WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
  148         WR4(sc, MCI_MR, 0x834a);        // XXX GROSS HACK FROM LINUX
  149 #ifndef  AT91_MCI_SLOT_B
  150         WR4(sc, MCI_SDCR, 0);                   /* SLOT A, 1 bit bus */
  151 #else
  152         /* XXX Really should add second "unit" but nobody using using 
  153          * a two slot card that we know of. XXX */
  154         WR4(sc, MCI_SDCR, 1);                   /* SLOT B, 1 bit bus */
  155 #endif
  156 }
  157 
  158 static void
  159 at91_mci_fini(device_t dev)
  160 {
  161         struct at91_mci_softc *sc = device_get_softc(dev);
  162 
  163         WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
  164         at91_mci_pdc_disable(sc);
  165         WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* Put the device into reset */
  166 }
  167 
  168 static int
  169 at91_mci_probe(device_t dev)
  170 {
  171 
  172         device_set_desc(dev, "MCI mmc/sd host bridge");
  173         return (0);
  174 }
  175 
  176 static int
  177 at91_mci_attach(device_t dev)
  178 {
  179         struct at91_mci_softc *sc = device_get_softc(dev);
  180         struct sysctl_ctx_list *sctx;
  181         struct sysctl_oid *soid;
  182         device_t child;
  183         int err;
  184 
  185         sc->dev = dev;
  186 
  187         sc->sc_cap = 0;
  188         if (at91_is_rm92())
  189                 sc->sc_cap |= CAP_NEEDS_BYTESWAP;
  190         err = at91_mci_activate(dev);
  191         if (err)
  192                 goto out;
  193 
  194         AT91_MCI_LOCK_INIT(sc);
  195 
  196         /*
  197          * Allocate DMA tags and maps
  198          */
  199         err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
  200             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXPHYS, 1,
  201             MAXPHYS, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag);
  202         if (err != 0)
  203                 goto out;
  204 
  205         err = bus_dmamap_create(sc->dmatag, 0,  &sc->map);
  206         if (err != 0)
  207                 goto out;
  208 
  209         at91_mci_fini(dev);
  210         at91_mci_init(dev);
  211 
  212         /*
  213          * Activate the interrupt
  214          */
  215         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
  216             NULL, at91_mci_intr, sc, &sc->intrhand);
  217         if (err) {
  218                 AT91_MCI_LOCK_DESTROY(sc);
  219                 goto out;
  220         }
  221 
  222         sctx = device_get_sysctl_ctx(dev);
  223         soid = device_get_sysctl_tree(dev);
  224         SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
  225             CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
  226 
  227 #ifdef AT91_MCI_HAS_4WIRE
  228         sc->has_4wire = 1;
  229 #endif
  230         if (sc->has_4wire)
  231                 sc->sc_cap |= CAP_HAS_4WIRE;
  232 
  233         sc->host.f_min = at91_master_clock / 512;
  234         sc->host.f_min = 375000;
  235         sc->host.f_max = at91_master_clock / 2;
  236         if (sc->host.f_max > 50000000)  
  237                 sc->host.f_max = 50000000;      /* Limit to 50MHz */
  238 
  239         sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
  240         sc->host.caps = 0;
  241         if (sc->sc_cap & CAP_HAS_4WIRE)
  242                 sc->host.caps |= MMC_CAP_4_BIT_DATA;
  243         child = device_add_child(dev, "mmc", 0);
  244         device_set_ivars(dev, &sc->host);
  245         err = bus_generic_attach(dev);
  246 out:;
  247         if (err)
  248                 at91_mci_deactivate(dev);
  249         return (err);
  250 }
  251 
  252 static int
  253 at91_mci_detach(device_t dev)
  254 {
  255         at91_mci_fini(dev);
  256         at91_mci_deactivate(dev);
  257         return (EBUSY); /* XXX */
  258 }
  259 
  260 static int
  261 at91_mci_activate(device_t dev)
  262 {
  263         struct at91_mci_softc *sc;
  264         int rid;
  265 
  266         sc = device_get_softc(dev);
  267         rid = 0;
  268         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  269             RF_ACTIVE);
  270         if (sc->mem_res == NULL)
  271                 goto errout;
  272 
  273         rid = 0;
  274         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  275             RF_ACTIVE);
  276         if (sc->irq_res == NULL)
  277                 goto errout;
  278 
  279         return (0);
  280 errout:
  281         at91_mci_deactivate(dev);
  282         return (ENOMEM);
  283 }
  284 
  285 static void
  286 at91_mci_deactivate(device_t dev)
  287 {
  288         struct at91_mci_softc *sc;
  289 
  290         sc = device_get_softc(dev);
  291         if (sc->intrhand)
  292                 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
  293         sc->intrhand = 0;
  294         bus_generic_detach(sc->dev);
  295         if (sc->mem_res)
  296                 bus_release_resource(dev, SYS_RES_IOPORT,
  297                     rman_get_rid(sc->mem_res), sc->mem_res);
  298         sc->mem_res = 0;
  299         if (sc->irq_res)
  300                 bus_release_resource(dev, SYS_RES_IRQ,
  301                     rman_get_rid(sc->irq_res), sc->irq_res);
  302         sc->irq_res = 0;
  303         return;
  304 }
  305 
  306 static void
  307 at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
  308 {
  309         if (error != 0)
  310                 return;
  311         *(bus_addr_t *)arg = segs[0].ds_addr;
  312 }
  313 
  314 static int
  315 at91_mci_update_ios(device_t brdev, device_t reqdev)
  316 {
  317         struct at91_mci_softc *sc;
  318         struct mmc_host *host;
  319         struct mmc_ios *ios;
  320         uint32_t clkdiv;
  321 
  322         sc = device_get_softc(brdev);
  323         host = &sc->host;
  324         ios = &host->ios;
  325         // bus mode?
  326         if (ios->clock == 0) {
  327                 WR4(sc, MCI_CR, MCI_CR_MCIDIS);
  328                 clkdiv = 0;
  329         } else {
  330                 WR4(sc, MCI_CR, MCI_CR_MCIEN);
  331                 if ((at91_master_clock % (ios->clock * 2)) == 0)
  332                         clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
  333                 else
  334                         clkdiv = (at91_master_clock / ios->clock) / 2;
  335         }
  336         if (ios->bus_width == bus_width_4)
  337                 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
  338         else
  339                 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
  340         WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
  341         /* Do we need a settle time here? */
  342         /* XXX We need to turn the device on/off here with a GPIO pin */
  343         return (0);
  344 }
  345 
  346 static void
  347 at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
  348 {
  349         uint32_t cmdr, ier = 0, mr;
  350         uint32_t *src, *dst;
  351         int i;
  352         struct mmc_data *data;
  353         void *vaddr;
  354         bus_addr_t paddr;
  355 
  356         sc->curcmd = cmd;
  357         data = cmd->data;
  358         cmdr = cmd->opcode;
  359 
  360         /* XXX Upper layers don't always set this */
  361         cmd->mrq = sc->req;
  362 
  363         if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
  364                 cmdr |= MCI_CMDR_RSPTYP_NO;
  365         else {
  366                 /* Allow big timeout for responses */
  367                 cmdr |= MCI_CMDR_MAXLAT;
  368                 if (cmd->flags & MMC_RSP_136)
  369                         cmdr |= MCI_CMDR_RSPTYP_136;
  370                 else
  371                         cmdr |= MCI_CMDR_RSPTYP_48;
  372         }
  373         if (cmd->opcode == MMC_STOP_TRANSMISSION)
  374                 cmdr |= MCI_CMDR_TRCMD_STOP;
  375         if (sc->host.ios.bus_mode == opendrain)
  376                 cmdr |= MCI_CMDR_OPDCMD;
  377         if (!data) {
  378                 // The no data case is fairly simple
  379                 at91_mci_pdc_disable(sc);
  380 //              printf("CMDR %x ARGR %x\n", cmdr, cmd->arg);
  381                 WR4(sc, MCI_ARGR, cmd->arg);
  382                 WR4(sc, MCI_CMDR, cmdr);
  383                 WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
  384                 return;
  385         }
  386         if (data->flags & MMC_DATA_READ)
  387                 cmdr |= MCI_CMDR_TRDIR;
  388         if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
  389                 cmdr |= MCI_CMDR_TRCMD_START;
  390         if (data->flags & MMC_DATA_STREAM)
  391                 cmdr |= MCI_CMDR_TRTYP_STREAM;
  392         if (data->flags & MMC_DATA_MULTI)
  393                 cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
  394         // Set block size and turn on PDC mode for dma xfer and disable
  395         // PDC until we're ready.
  396         mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
  397         WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
  398         WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
  399         if (cmdr & MCI_CMDR_TRCMD_START) {
  400                 if (cmdr & MCI_CMDR_TRDIR)
  401                         vaddr = cmd->data->data;
  402                 else {
  403                         /* Use bounce buffer even if we don't need
  404                          * byteswap, since buffer may straddle a page
  405                          * boundry, and we don't handle multi-segment
  406                          * transfers in hardware.
  407                          * (page issues seen from 'bsdlabel -w' which
  408                          * uses raw geom access to the volume).
  409                          * Greg Ansley (gja (at) ansley.com)
  410                          */
  411                         vaddr = sc->bounce_buffer;
  412                         src = (uint32_t *)cmd->data->data;
  413                         dst = (uint32_t *)vaddr;
  414                         if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
  415                                 for (i = 0; i < data->len / 4; i++)
  416                                         dst[i] = bswap32(src[i]);
  417                         } else
  418                                 memcpy(dst, src, data->len);
  419                 }
  420                 data->xfer_len = 0;
  421                 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
  422                     at91_mci_getaddr, &paddr, 0) != 0) {
  423                         cmd->error = MMC_ERR_NO_MEMORY;
  424                         sc->req = NULL;
  425                         sc->curcmd = NULL;
  426                         cmd->mrq->done(cmd->mrq);
  427                         return;
  428                 }
  429                 sc->mapped++;
  430                 if (cmdr & MCI_CMDR_TRDIR) {
  431                         bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
  432                         WR4(sc, PDC_RPR, paddr);
  433                         WR4(sc, PDC_RCR, data->len / 4);
  434                         ier = MCI_SR_ENDRX;
  435                 } else {
  436                         bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREWRITE);
  437                         WR4(sc, PDC_TPR, paddr);
  438                         WR4(sc, PDC_TCR, data->len / 4);
  439                         ier = MCI_SR_TXBUFE;
  440                 }
  441         }
  442 //      printf("CMDR %x ARGR %x with data\n", cmdr, cmd->arg);
  443         WR4(sc, MCI_ARGR, cmd->arg);
  444         if (cmdr & MCI_CMDR_TRCMD_START) {
  445                 if (cmdr & MCI_CMDR_TRDIR) {
  446                         WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
  447                         WR4(sc, MCI_CMDR, cmdr);
  448                 } else {
  449                         WR4(sc, MCI_CMDR, cmdr);
  450                         WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
  451                 }
  452         }
  453         WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
  454 }
  455 
  456 static void
  457 at91_mci_start(struct at91_mci_softc *sc)
  458 {
  459         struct mmc_request *req;
  460 
  461         req = sc->req;
  462         if (req == NULL)
  463                 return;
  464         // assert locked
  465         if (!(sc->flags & CMD_STARTED)) {
  466                 sc->flags |= CMD_STARTED;
  467 //              printf("Starting CMD\n");
  468                 at91_mci_start_cmd(sc, req->cmd);
  469                 return;
  470         }
  471         if (!(sc->flags & STOP_STARTED) && req->stop) {
  472 //              printf("Starting Stop\n");
  473                 sc->flags |= STOP_STARTED;
  474                 at91_mci_start_cmd(sc, req->stop);
  475                 return;
  476         }
  477         /* We must be done -- bad idea to do this while locked? */
  478         sc->req = NULL;
  479         sc->curcmd = NULL;
  480         req->done(req);
  481 }
  482 
  483 static int
  484 at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
  485 {
  486         struct at91_mci_softc *sc = device_get_softc(brdev);
  487 
  488         AT91_MCI_LOCK(sc);
  489         // XXX do we want to be able to queue up multiple commands?
  490         // XXX sounds like a good idea, but all protocols are sync, so
  491         // XXX maybe the idea is naive...
  492         if (sc->req != NULL) {
  493                 AT91_MCI_UNLOCK(sc);
  494                 return (EBUSY);
  495         }
  496         sc->req = req;
  497         sc->flags = 0;
  498         at91_mci_start(sc);
  499         AT91_MCI_UNLOCK(sc);
  500         return (0);
  501 }
  502 
  503 static int
  504 at91_mci_get_ro(device_t brdev, device_t reqdev)
  505 {
  506         return (0);
  507 }
  508 
  509 static int
  510 at91_mci_acquire_host(device_t brdev, device_t reqdev)
  511 {
  512         struct at91_mci_softc *sc = device_get_softc(brdev);
  513         int err = 0;
  514 
  515         AT91_MCI_LOCK(sc);
  516         while (sc->bus_busy)
  517                 msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
  518         sc->bus_busy++;
  519         AT91_MCI_UNLOCK(sc);
  520         return (err);
  521 }
  522 
  523 static int
  524 at91_mci_release_host(device_t brdev, device_t reqdev)
  525 {
  526         struct at91_mci_softc *sc = device_get_softc(brdev);
  527 
  528         AT91_MCI_LOCK(sc);
  529         sc->bus_busy--;
  530         wakeup(sc);
  531         AT91_MCI_UNLOCK(sc);
  532         return (0);
  533 }
  534 
  535 static void
  536 at91_mci_read_done(struct at91_mci_softc *sc)
  537 {
  538         uint32_t *walker;
  539         struct mmc_command *cmd;
  540         int i, len;
  541 
  542         cmd = sc->curcmd;
  543         bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
  544         bus_dmamap_unload(sc->dmatag, sc->map);
  545         sc->mapped--;
  546         if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
  547                 walker = (uint32_t *)cmd->data->data;
  548                 len = cmd->data->len / 4;
  549                 for (i = 0; i < len; i++)
  550                         walker[i] = bswap32(walker[i]);
  551         }
  552         // Finish up the sequence...
  553         WR4(sc, MCI_IDR, MCI_SR_ENDRX);
  554         WR4(sc, MCI_IER, MCI_SR_RXBUFF);
  555         WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
  556 }
  557 
  558 static void
  559 at91_mci_xmit_done(struct at91_mci_softc *sc)
  560 {
  561         // Finish up the sequence...
  562         WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
  563         WR4(sc, MCI_IDR, MCI_SR_TXBUFE);
  564         WR4(sc, MCI_IER, MCI_SR_NOTBUSY);
  565         bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTWRITE);
  566         bus_dmamap_unload(sc->dmatag, sc->map);
  567         sc->mapped--;
  568 }
  569 
  570 static void
  571 at91_mci_intr(void *arg)
  572 {
  573         struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
  574         uint32_t sr;
  575         int i, done = 0;
  576         struct mmc_command *cmd;
  577 
  578         AT91_MCI_LOCK(sc);
  579         sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR);
  580 //      printf("i 0x%x\n", sr);
  581         cmd = sc->curcmd;
  582         if (sr & MCI_SR_ERROR) {
  583                 // Ignore CRC errors on CMD2 and ACMD47, per relevant standards
  584                 if ((sr & MCI_SR_RCRCE) && (cmd->opcode == MMC_SEND_OP_COND ||
  585                     cmd->opcode == ACMD_SD_SEND_OP_COND))
  586                         cmd->error = MMC_ERR_NONE;
  587                 else if (sr & (MCI_SR_RTOE | MCI_SR_DTOE))
  588                         cmd->error = MMC_ERR_TIMEOUT;
  589                 else if (sr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
  590                         cmd->error = MMC_ERR_BADCRC;
  591                 else if (sr & (MCI_SR_OVRE | MCI_SR_UNRE))
  592                         cmd->error = MMC_ERR_FIFO;
  593                 else
  594                         cmd->error = MMC_ERR_FAILED;
  595                 done = 1;
  596                 if (sc->mapped && cmd->error) {
  597                         bus_dmamap_unload(sc->dmatag, sc->map);
  598                         sc->mapped--;
  599                 }
  600         } else {
  601                 if (sr & MCI_SR_TXBUFE) {
  602 //                      printf("TXBUFE\n");
  603                         at91_mci_xmit_done(sc);
  604                 }
  605                 if (sr & MCI_SR_RXBUFF) {
  606 //                      printf("RXBUFF\n");
  607                         WR4(sc, MCI_IDR, MCI_SR_RXBUFF);
  608                         WR4(sc, MCI_IER, MCI_SR_CMDRDY);
  609                 }
  610                 if (sr & MCI_SR_ENDTX) {
  611 //                      printf("ENDTX\n");
  612                 }
  613                 if (sr & MCI_SR_ENDRX) {
  614 //                      printf("ENDRX\n");
  615                         at91_mci_read_done(sc);
  616                 }
  617                 if (sr & MCI_SR_NOTBUSY) {
  618 //                      printf("NOTBUSY\n");
  619                         WR4(sc, MCI_IDR, MCI_SR_NOTBUSY);
  620                         WR4(sc, MCI_IER, MCI_SR_CMDRDY);
  621                 }
  622                 if (sr & MCI_SR_DTIP) {
  623 //                      printf("Data transfer in progress\n");
  624                 }
  625                 if (sr & MCI_SR_BLKE) {
  626 //                      printf("Block transfer end\n");
  627                 }
  628                 if (sr & MCI_SR_TXRDY) {
  629 //                      printf("Ready to transmit\n");
  630                 }
  631                 if (sr & MCI_SR_RXRDY) {
  632 //                      printf("Ready to receive\n");
  633                 }
  634                 if (sr & MCI_SR_CMDRDY) {
  635 //                      printf("Command ready\n");
  636                         done = 1;
  637                         cmd->error = MMC_ERR_NONE;
  638                 }
  639         }
  640         if (done) {
  641                 WR4(sc, MCI_IDR, 0xffffffff);
  642                 if (cmd != NULL && (cmd->flags & MMC_RSP_PRESENT)) {
  643                         for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1);
  644                              i++) {
  645                                 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
  646 //                              printf("RSPR[%d] = %x\n", i, cmd->resp[i]);
  647                         }
  648                 }
  649                 at91_mci_start(sc);
  650         }
  651         AT91_MCI_UNLOCK(sc);
  652 }
  653 
  654 static int
  655 at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
  656 {
  657         struct at91_mci_softc *sc = device_get_softc(bus);
  658 
  659         switch (which) {
  660         default:
  661                 return (EINVAL);
  662         case MMCBR_IVAR_BUS_MODE:
  663                 *(int *)result = sc->host.ios.bus_mode;
  664                 break;
  665         case MMCBR_IVAR_BUS_WIDTH:
  666                 *(int *)result = sc->host.ios.bus_width;
  667                 break;
  668         case MMCBR_IVAR_CHIP_SELECT:
  669                 *(int *)result = sc->host.ios.chip_select;
  670                 break;
  671         case MMCBR_IVAR_CLOCK:
  672                 *(int *)result = sc->host.ios.clock;
  673                 break;
  674         case MMCBR_IVAR_F_MIN:
  675                 *(int *)result = sc->host.f_min;
  676                 break;
  677         case MMCBR_IVAR_F_MAX:
  678                 *(int *)result = sc->host.f_max;
  679                 break;
  680         case MMCBR_IVAR_HOST_OCR:
  681                 *(int *)result = sc->host.host_ocr;
  682                 break;
  683         case MMCBR_IVAR_MODE:
  684                 *(int *)result = sc->host.mode;
  685                 break;
  686         case MMCBR_IVAR_OCR:
  687                 *(int *)result = sc->host.ocr;
  688                 break;
  689         case MMCBR_IVAR_POWER_MODE:
  690                 *(int *)result = sc->host.ios.power_mode;
  691                 break;
  692         case MMCBR_IVAR_VDD:
  693                 *(int *)result = sc->host.ios.vdd;
  694                 break;
  695         case MMCBR_IVAR_CAPS:
  696                 if (sc->has_4wire) {
  697                         sc->sc_cap |= CAP_HAS_4WIRE;
  698                         sc->host.caps |= MMC_CAP_4_BIT_DATA;
  699                 } else {
  700                         sc->sc_cap &= ~CAP_HAS_4WIRE;
  701                         sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
  702                 }
  703                 *(int *)result = sc->host.caps;
  704                 break;
  705         case MMCBR_IVAR_MAX_DATA:
  706                 *(int *)result = 1;
  707                 break;
  708         }
  709         return (0);
  710 }
  711 
  712 static int
  713 at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
  714 {
  715         struct at91_mci_softc *sc = device_get_softc(bus);
  716 
  717         switch (which) {
  718         default:
  719                 return (EINVAL);
  720         case MMCBR_IVAR_BUS_MODE:
  721                 sc->host.ios.bus_mode = value;
  722                 break;
  723         case MMCBR_IVAR_BUS_WIDTH:
  724                 sc->host.ios.bus_width = value;
  725                 break;
  726         case MMCBR_IVAR_CHIP_SELECT:
  727                 sc->host.ios.chip_select = value;
  728                 break;
  729         case MMCBR_IVAR_CLOCK:
  730                 sc->host.ios.clock = value;
  731                 break;
  732         case MMCBR_IVAR_MODE:
  733                 sc->host.mode = value;
  734                 break;
  735         case MMCBR_IVAR_OCR:
  736                 sc->host.ocr = value;
  737                 break;
  738         case MMCBR_IVAR_POWER_MODE:
  739                 sc->host.ios.power_mode = value;
  740                 break;
  741         case MMCBR_IVAR_VDD:
  742                 sc->host.ios.vdd = value;
  743                 break;
  744         /* These are read-only */
  745         case MMCBR_IVAR_CAPS:
  746         case MMCBR_IVAR_HOST_OCR:
  747         case MMCBR_IVAR_F_MIN:
  748         case MMCBR_IVAR_F_MAX:
  749         case MMCBR_IVAR_MAX_DATA:
  750                 return (EINVAL);
  751         }
  752         return (0);
  753 }
  754 
  755 static device_method_t at91_mci_methods[] = {
  756         /* device_if */
  757         DEVMETHOD(device_probe, at91_mci_probe),
  758         DEVMETHOD(device_attach, at91_mci_attach),
  759         DEVMETHOD(device_detach, at91_mci_detach),
  760 
  761         /* Bus interface */
  762         DEVMETHOD(bus_read_ivar,        at91_mci_read_ivar),
  763         DEVMETHOD(bus_write_ivar,       at91_mci_write_ivar),
  764 
  765         /* mmcbr_if */
  766         DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
  767         DEVMETHOD(mmcbr_request, at91_mci_request),
  768         DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
  769         DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
  770         DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
  771 
  772         {0, 0},
  773 };
  774 
  775 static driver_t at91_mci_driver = {
  776         "at91_mci",
  777         at91_mci_methods,
  778         sizeof(struct at91_mci_softc),
  779 };
  780 static devclass_t at91_mci_devclass;
  781 
  782 
  783 DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, 0, 0);

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