The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_mcireg.h

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    1 /*-
    2  * Copyright (c) 2006 Berndt Walter.  All rights reserved.
    3  * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /* $FreeBSD: releng/8.1/sys/arm/at91/at91_mcireg.h 185265 2008-11-25 00:13:26Z imp $ */
   28 
   29 #ifndef ARM_AT91_AT91_MCIREG_H
   30 #define ARM_AT91_AT91_MCIREG_H
   31 
   32 #define MMC_MAX         30
   33 
   34 #define MCI_CR          0x00    /* MCI Control Register */
   35 #define MCI_MR          0x04    /* MCI Mode Register */
   36 #define MCI_DTOR        0x08    /* MCI Data Timeout Register */
   37 #define MCI_SDCR        0x0c    /* MCI SD Card Register */
   38 #define MCI_ARGR        0x10    /* MCI Argument Register */
   39 #define MCI_CMDR        0x14    /* MCI Command Register */
   40 #define MCI_RSPR        0x20    /* MCI Response Registers - 4 of them */
   41 #define MCI_RDR         0x30    /* MCI Receive Data Register */
   42 #define MCI_TDR         0x34    /* MCI Transmit Data Register */
   43 #define MCI_SR          0x40    /* MCI Status Register */
   44 #define MCI_IER         0x44    /* MCI Interrupt Enable Register */
   45 #define MCI_IDR         0x48    /* MCI Interrupt Disable Register */
   46 #define MCI_IMR         0x4c    /* MCI Interrupt Mask Register */
   47 
   48 /* -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------  */
   49 #define MCI_CR_MCIEN       (0x1u <<  0) /* (MCI) Multimedia Interface Enable */
   50 #define MCI_CR_MCIDIS      (0x1u <<  1) /* (MCI) Multimedia Interface Disable */
   51 #define MCI_CR_PWSEN       (0x1u <<  2) /* (MCI) Power Save Mode Enable */
   52 #define MCI_CR_PWSDIS      (0x1u <<  3) /* (MCI) Power Save Mode Disable */
   53 #define MCI_CR_SWRST      (0x1u <<  7) /* (MCI) Software Reset */
   54 /* -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------  */
   55 #define MCI_MR_CLKDIV      (0xffu <<  0) /* (MCI) Clock Divider */
   56 #define MCI_MR_PWSDIV      (0x3fu <<  8) /* (MCI) Power Saving Divider */
   57 #define MCI_MR_PDCPADV     (0x1u << 14) /* (MCI) PDC Padding Value */
   58 #define MCI_MR_PDCMODE     (0x1u << 15) /* (MCI) PDC Oriented Mode */
   59 #define MCI_MR_BLKLEN      0x3fff0000ul /* (MCI) Data Block Length */
   60 /* -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------  */
   61 #define MCI_DTOR_DTOCYC      (0xfu <<  0) /* (MCI) Data Timeout Cycle Number */
   62 #define MCI_DTOR_DTOMUL      (0x7u <<  4) /* (MCI) Data Timeout Multiplier */
   63 #define         MCI_DTOR_DTOMUL_1                    (0x0u <<  4) /* (MCI) DTOCYC x 1 */
   64 #define         MCI_DTOR_DTOMUL_16                   (0x1u <<  4) /* (MCI) DTOCYC x 16 */
   65 #define         MCI_DTOR_DTOMUL_128                  (0x2u <<  4) /* (MCI) DTOCYC x 128 */
   66 #define         MCI_DTOR_DTOMUL_256                  (0x3u <<  4) /* (MCI) DTOCYC x 256 */
   67 #define         MCI_DTOR_DTOMUL_1k                   (0x4u <<  4) /* (MCI) DTOCYC x 1024 */
   68 #define         MCI_DTOR_DTOMUL_4k                   (0x5u <<  4) /* (MCI) DTOCYC x 4096 */
   69 #define         MCI_DTOR_DTOMUL_64k                  (0x6u <<  4) /* (MCI) DTOCYC x 65536 */
   70 #define         MCI_DTOR_DTOMUL_1M                   (0x7u <<  4) /* (MCI) DTOCYC x 1048576 */
   71 /* -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------  */
   72 #define MCI_SDCR_SDCSEL      (0x1u <<  0) /* (MCI) SD Card Selector */
   73 #define MCI_SDCR_SDCBUS      (0x1u <<  7) /* (MCI) SD Card Bus Width */
   74 /* -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------  */
   75 #define MCI_CMDR_CMDNB       (0x1Fu <<  0) /* (MCI) Command Number */
   76 #define MCI_CMDR_RSPTYP      (0x3u <<  6) /* (MCI) Response Type */
   77 #define         MCI_CMDR_RSPTYP_NO                   (0x0u <<  6) /* (MCI) No response */
   78 #define         MCI_CMDR_RSPTYP_48                   (0x1u <<  6) /* (MCI) 48-bit response */
   79 #define         MCI_CMDR_RSPTYP_136                  (0x2u <<  6) /* (MCI) 136-bit response */
   80 #define MCI_CMDR_SPCMD       (0x7u <<  8) /* (MCI) Special CMD */
   81 #define         MCI_CMDR_SPCMD_NONE                 (0x0u <<  8) /* (MCI) Not a special CMD */
   82 #define         MCI_CMDR_SPCMD_INIT                 (0x1u <<  8) /* (MCI) Initialization CMD */
   83 #define         MCI_CMDR_SPCMD_SYNC                 (0x2u <<  8) /* (MCI) Synchronized CMD */
   84 #define         MCI_CMDR_SPCMD_IT_CMD               (0x4u <<  8) /* (MCI) Interrupt command */
   85 #define         MCI_CMDR_SPCMD_IT_REP               (0x5u <<  8) /* (MCI) Interrupt response */
   86 #define MCI_CMDR_OPDCMD      (0x1u << 11) /* (MCI) Open Drain Command */
   87 #define MCI_CMDR_MAXLAT      (0x1u << 12) /* (MCI) Maximum Latency for Command to respond */
   88 #define MCI_CMDR_TRCMD       (0x3u << 16) /* (MCI) Transfer CMD */
   89 #define         MCI_CMDR_TRCMD_NO                   (0x0u << 16) /* (MCI) No transfer */
   90 #define         MCI_CMDR_TRCMD_START                (0x1u << 16) /* (MCI) Start transfer */
   91 #define         MCI_CMDR_TRCMD_STOP                 (0x2u << 16) /* (MCI) Stop transfer */
   92 #define MCI_CMDR_TRDIR       (0x1u << 18) /* (MCI) Transfer Direction */
   93 #define MCI_CMDR_TRTYP       (0x3u << 19) /* (MCI) Transfer Type */
   94 #define         MCI_CMDR_TRTYP_BLOCK                (0x0u << 19) /* (MCI) Block Transfer type */
   95 #define         MCI_CMDR_TRTYP_MULTIPLE             (0x1u << 19) /* (MCI) Multiple Block transfer type */
   96 #define         MCI_CMDR_TRTYP_STREAM               (0x2u << 19) /* (MCI) Stream transfer type */
   97 /* -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------  */
   98 #define MCI_SR_CMDRDY   (0x1u <<  0) /* (MCI) Command Ready flag */
   99 #define MCI_SR_RXRDY    (0x1u <<  1) /* (MCI) RX Ready flag */
  100 #define MCI_SR_TXRDY    (0x1u <<  2) /* (MCI) TX Ready flag */
  101 #define MCI_SR_BLKE     (0x1u <<  3) /* (MCI) Data Block Transfer Ended flag */
  102 #define MCI_SR_DTIP     (0x1u <<  4) /* (MCI) Data Transfer in Progress flag */
  103 #define MCI_SR_NOTBUSY  (0x1u <<  5) /* (MCI) Data Line Not Busy flag */
  104 #define MCI_SR_ENDRX    (0x1u <<  6) /* (MCI) End of RX Buffer flag */
  105 #define MCI_SR_ENDTX    (0x1u <<  7) /* (MCI) End of TX Buffer flag */
  106 #define MCI_SR_RXBUFF   (0x1u << 14) /* (MCI) RX Buffer Full flag */
  107 #define MCI_SR_TXBUFE   (0x1u << 15) /* (MCI) TX Buffer Empty flag */
  108 #define MCI_SR_RINDE    (0x1u << 16) /* (MCI) Response Index Error flag */
  109 #define MCI_SR_RDIRE    (0x1u << 17) /* (MCI) Response Direction Error flag */
  110 #define MCI_SR_RCRCE    (0x1u << 18) /* (MCI) Response CRC Error flag */
  111 #define MCI_SR_RENDE    (0x1u << 19) /* (MCI) Response End Bit Error flag */
  112 #define MCI_SR_RTOE     (0x1u << 20) /* (MCI) Response Time-out Error flag */
  113 #define MCI_SR_DCRCE    (0x1u << 21) /* (MCI) data CRC Error flag */
  114 #define MCI_SR_DTOE     (0x1u << 22) /* (MCI) Data timeout Error flag */
  115 #define MCI_SR_OVRE     (0x1u << 30) /* (MCI) Overrun flag */
  116 #define MCI_SR_UNRE     (0x1u << 31) /* (MCI) Underrun flag */
  117 
  118 /* -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------  */
  119 /* -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------  */
  120 /* -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------  */
  121 
  122 #define MCI_SR_ERROR    (MCI_SR_UNRE | MCI_SR_OVRE | MCI_SR_DTOE | \
  123                         MCI_SR_DCRCE | MCI_SR_RTOE | MCI_SR_RENDE | \
  124                         MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE)
  125 
  126 #define AT91C_BUS_WIDTH_1BIT            0x00
  127 #define AT91C_BUS_WIDTH_4BITS           0x02
  128 
  129 #endif /* ARM_AT91_AT91_MCIREG_H */

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