1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_pdcreg.h,v 1.2 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef ARM_AT91_AT91_PDCREG_H
29 #define ARM_AT91_AT91_PDCREG_H
30
31 #define PDC_RPR 0x100 /* PDC Receive Pointer Register */
32 #define PDC_RCR 0x104 /* PDC Receive Counter Register */
33 #define PDC_TPR 0x108 /* PDC Transmit Pointer Register */
34 #define PDC_TCR 0x10c /* PDC Transmit Counter Register */
35 #define PDC_RNPR 0x110 /* PDC Receive Next Pointer Register */
36 #define PDC_RNCR 0x114 /* PDC Receive Next Counter Register */
37 #define PDC_TNPR 0x118 /* PDC Transmit Next Pointer Reg */
38 #define PDC_TNCR 0x11c /* PDC Transmit Next Counter Reg */
39 #define PDC_PTCR 0x120 /* PDC Transfer Control Register */
40 #define PDC_PTSR 0x124 /* PDC Transfer Status Register */
41
42 /* PTCR/PTSR */
43 #define PDC_PTCR_RXTEN (1UL << 0) /* RXTEN: Receiver Transfer Enable */
44 #define PDC_PTCR_RXTDIS (1UL << 1) /* RXTDIS: Receiver Transfer Disable */
45 #define PDC_PTCR_TXTEN (1UL << 8) /* TXTEN: Transmitter Transfer En */
46 #define PDC_PTCR_TXTDIS (1UL << 9) /* TXTDIS: Transmitter Transmit Dis */
47
48 #endif /* ARM_AT91_AT91_PDCREG_H */
49 Cache object: cde0381c85432cd1065d15a6f1d474f6
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