1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_pioreg.h,v 1.3 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef ARM_AT91_AT91_PIOREG_H
29 #define ARM_AT91_AT91_PIOREG_H
30
31 /* Registers */
32 #define PIO_PER 0x00 /* PIO Enable Register */
33 #define PIO_PDR 0x04 /* PIO Disable Register */
34 #define PIO_PSR 0x08 /* PIO Status Register */
35 /* 0x0c reserved */
36 #define PIO_OER 0x10 /* PIO Output Enable Register */
37 #define PIO_ODR 0x14 /* PIO Output Disable Register */
38 #define PIO_OSR 0x18 /* PIO Output Status Register */
39 /* 0x1c reserved */
40 #define PIO_IFER 0x20 /* PIO Glitch Input Enable Register */
41 #define PIO_IFDR 0x24 /* PIO Glitch Input Disable Register */
42 #define PIO_IFSR 0x28 /* PIO Glitch Input Status Register */
43 /* 0x2c reserved */
44 #define PIO_SODR 0x30 /* PIO Set Output Data Register */
45 #define PIO_CODR 0x34 /* PIO Clear Output Data Register */
46 #define PIO_ODSR 0x38 /* PIO Output Data Status Register */
47 #define PIO_PDSR 0x3c /* PIO Pin Data Status Register */
48 #define PIO_IER 0x40 /* PIO Interrupt Enable Register */
49 #define PIO_IDR 0x44 /* PIO Interrupt Disable Register */
50 #define PIO_IMR 0x48 /* PIO Interrupt Mask Register */
51 #define PIO_ISR 0x4c /* PIO Interrupt Status Register */
52 #define PIO_MDER 0x50 /* PIO Multi-Driver Enable Register */
53 #define PIO_MDDR 0x54 /* PIO Multi-Driver Disable Register */
54 #define PIO_MDSR 0x58 /* PIO Multi-Driver Status Register */
55 /* 0x5c reserved */
56 #define PIO_PUDR 0x60 /* PIO Pull-up Disable Register */
57 #define PIO_PUER 0x64 /* PIO Pull-up Enable Register */
58 #define PIO_PUSR 0x68 /* PIO Pull-up Status Register */
59 /* 0x6c reserved */
60 #define PIO_ASR 0x70 /* PIO Peripheral A Select Register */
61 #define PIO_BSR 0x74 /* PIO Peripheral B Select Register */
62 #define PIO_ABSR 0x78 /* PIO AB Status Register */
63 /* 0x7c-0x9c reserved */
64 #define PIO_OWER 0xa0 /* PIO Output Write Enable Register */
65 #define PIO_OWDR 0xa4 /* PIO Output Write Disable Register */
66 #define PIO_OWSR 0xa8 /* PIO Output Write Status Register */
67 /* 0xac reserved */
68
69 #endif /* ARM_AT91_AT91_PIOREG_H */
70 Cache object: 1340417ecd39c06426a21a2c270d51c6
|