1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25 /* $FreeBSD: releng/7.3/sys/arm/at91/at91_pioreg.h 165711 2007-01-01 00:46:54Z imp $ */
26
27 #ifndef ARM_AT91_AT91_PIOREG_H
28 #define ARM_AT91_AT91_PIOREG_H
29
30 /* Registers */
31 #define PIO_PER 0x00 /* PIO Enable Register */
32 #define PIO_PDR 0x04 /* PIO Disable Register */
33 #define PIO_PSR 0x08 /* PIO Status Register */
34 /* 0x0c reserved */
35 #define PIO_OER 0x10 /* PIO Output Enable Register */
36 #define PIO_ODR 0x14 /* PIO Output Disable Register */
37 #define PIO_OSR 0x18 /* PIO Output Status Register */
38 /* 0x1c reserved */
39 #define PIO_IFER 0x20 /* PIO Glitch Input Enable Register */
40 #define PIO_IFDR 0x24 /* PIO Glitch Input Disable Register */
41 #define PIO_IFSR 0x28 /* PIO Glitch Input Status Register */
42 /* 0x2c reserved */
43 #define PIO_SODR 0x30 /* PIO Set Output Data Register */
44 #define PIO_CODR 0x34 /* PIO Clear Output Data Register */
45 #define PIO_ODSR 0x38 /* PIO Output Data Status Register */
46 #define PIO_PDSR 0x3c /* PIO Pin Data Status Register */
47 #define PIO_IER 0x40 /* PIO Interrupt Enable Register */
48 #define PIO_IDR 0x44 /* PIO Interrupt Disable Register */
49 #define PIO_IMR 0x48 /* PIO Interrupt Mask Register */
50 #define PIO_ISR 0x4c /* PIO Interrupt Status Register */
51 #define PIO_MDER 0x50 /* PIO Multi-Driver Enable Register */
52 #define PIO_MDDR 0x54 /* PIO Multi-Driver Disable Register */
53 #define PIO_MDSR 0x58 /* PIO Multi-Driver Status Register */
54 /* 0x5c reserved */
55 #define PIO_PUDR 0x60 /* PIO Pull-up Disable Register */
56 #define PIO_PUER 0x64 /* PIO Pull-up Enable Register */
57 #define PIO_PUSR 0x68 /* PIO Pull-up Status Register */
58 /* 0x6c reserved */
59 #define PIO_ASR 0x70 /* PIO Peripheral A Select Register */
60 #define PIO_BSR 0x74 /* PIO Peripheral B Select Register */
61 #define PIO_ABSR 0x78 /* PIO AB Status Register */
62 /* 0x7c-0x9c reserved */
63 #define PIO_OWER 0xa0 /* PIO Output Write Enable Register */
64 #define PIO_OWDR 0xa4 /* PIO Output Write Disable Register */
65 #define PIO_OWSR 0xa8 /* PIO Output Write Status Register */
66 /* 0xac reserved */
67
68 #endif /* ARM_AT91_AT91_PIOREG_H */
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