The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_pmcreg.h

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    1 /*-
    2  * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  */
   24 
   25 /* $FreeBSD$ */
   26 
   27 #ifndef ARM_AT91_AT91_PMCREG_H
   28 #define ARM_AT91_AT91_PMCREG_H
   29 
   30 /* Registers */
   31 #define PMC_SCER        0x00            /* System Clock Enable Register */
   32 #define PMC_SCDR        0x04            /* System Clock Disable Register */
   33 #define PMC_SCSR        0x08            /* System Clock Status Register */
   34                 /*      0x0c               reserved */
   35 #define PMC_PCER        0x10            /* Peripheral Clock Enable Register */
   36 #define PMC_PCDR        0x14            /* Peripheral Clock Disable Register */
   37 #define PMC_PCSR        0x18            /* Peripheral Clock Status Register */
   38                 /*      0x1c               reserved */
   39 #define CKGR_MOR        0x20            /* Main Oscillator Register */
   40 #define CKGR_MCFR       0x24            /* Main Clock Frequency Register */
   41 #define CKGR_PLLAR      0x28            /* PLL A Register */
   42 #define CKGR_PLLBR      0x2c            /* PLL B Register */
   43 #define PMC_MCKR        0x30            /* Master Clock Register */
   44                 /*      0x34               reserved */
   45                 /*      0x38               reserved */
   46                 /*      0x3c               reserved */
   47 #define PMC_PCK0        0x40            /* Programmable Clock 0 Register */
   48 #define PMC_PCK1        0x44            /* Programmable Clock 1 Register */
   49 #define PMC_PCK2        0x48            /* Programmable Clock 2 Register */
   50 #define PMC_PCK3        0x4c            /* Programmable Clock 3 Register */
   51                 /*      0x50               reserved */
   52                 /*      0x54               reserved */
   53                 /*      0x58               reserved */
   54                 /*      0x5c               reserved */
   55 #define PMC_IER         0x60            /* Interrupt Enable Register */
   56 #define PMC_IDR         0x64            /* Interrupt Disable Register */
   57 #define PMC_SR          0x68            /* Status Register */
   58 #define PMC_IMR         0x6c            /* Interrupt Mask Register */
   59 
   60 /* PMC System Clock Enable Register */
   61 /* PMC System Clock Disable Register */
   62 /* PMC System Clock StatusRegister */
   63 #define PMC_SCER_PCK    (1UL << 0)      /* PCK: Processor Clock Enable */
   64 #define PMC_SCER_UDP    (1UL << 1)      /* UDP: USB Device Port Clock Enable */
   65 #define PMC_SCER_MCKUDP (1UL << 2)      /* MCKUDP: Master disable susp/res */
   66 #define PMC_SCER_UHP    (1UL << 4)      /* UHP: USB Host Port Clock Enable */
   67 #define PMC_SCER_PCK0   (1UL << 8)      /* PCK0: Programmable Clock out en */
   68 #define PMC_SCER_PCK1   (1UL << 10)     /* PCK1: Programmable Clock out en */
   69 #define PMC_SCER_PCK2   (1UL << 11)     /* PCK2: Programmable Clock out en */
   70 #define PMC_SCER_PCK3   (1UL << 12)     /* PCK3: Programmable Clock out en */
   71 
   72 /* PMC Peripheral Clock Enable Register */
   73 /* PMC Peripheral Clock Disable Register */
   74 /* PMC Peripheral Clock Status Register */
   75 /* Each bit here is 1 << peripheral number  to enable/disable/status */
   76 
   77 /* PMC Clock Generator Main Oscillator Register */
   78 #define CKGR_MOR_MOSCEN (1UL << 0)      /* MOSCEN: Main Oscillator Enable */
   79 #define CKGR_MOR_OSCBYPASS (1UL << 1)   /* Oscillator Bypass */
   80 #define CKGR_MOR_OSCOUNT(x) (x << 8)    /* Main Oscillator Start-up Time */
   81 
   82 /* PMC Clock Generator Main Clock Frequency Register */
   83 #define CKGR_MCFR_MAINRDY       (1UL << 16)     /* Main Clock Ready */
   84 #define CKGR_MCFR_MAINF_MASK    0xfffful        /* Main Clock Frequency */
   85 
   86 /* PMC Interrupt Enable Register */
   87 /* PMC Interrupt Disable Register */
   88 /* PMC Status Register */
   89 /* PMC Interrupt Mask Register */
   90 #define PMC_IER_MOSCS   (1UL << 0)      /* Main Oscillator Status */
   91 #define PMC_IER_LOCKA   (1UL << 1)      /* PLL A Locked */
   92 #define PMC_IER_LOCKB   (1UL << 2)      /* PLL B Locked */
   93 #define PMC_IER_MCKRDY  (1UL << 3)      /* Master Clock Status */
   94 #define PMC_IER_PCK0RDY (1UL << 8)      /* Programmable Clock 0 Ready */
   95 #define PMC_IER_PCK1RDY (1UL << 9)      /* Programmable Clock 1 Ready */
   96 #define PMC_IER_PCK2RDY (1UL << 10)     /* Programmable Clock 2 Ready */
   97 #define PMC_IER_PCK3RDY (1UL << 11)     /* Programmable Clock 3 Ready */
   98 
   99 /*
  100  * PLL input frequency spec sheet says it must be between 1MHz and 32MHz,
  101  * but it works down as low as 100kHz, a frequency necessary for some
  102  * output frequencies to work.
  103  */
  104 #define PMC_PLL_MIN_IN_FREQ     100000
  105 #define PMC_PLL_MAX_IN_FREQ     32000000
  106 
  107 /*
  108  * PLL Max output frequency is 240MHz.  The errata says 180MHz is the max
  109  * for some revisions of this part.  Be more permissive and optimistic.
  110  */
  111 #define PMC_PLL_MAX_OUT_FREQ    240000000
  112 
  113 #define PMC_PLL_MULT_MIN        2
  114 #define PMC_PLL_MULT_MAX        2048
  115 
  116 #define PMC_PLL_SHIFT_TOL       5       /* Allow errors 1 part in 32 */
  117 
  118 #define PMC_PLL_FAST_THRESH     155000000
  119 
  120 #endif /* ARM_AT91_AT91_PMCREG_H */

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