The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_rstreg.h

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    1 /*-
    2  * Copyright (c) 2009 Greg Ansley.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 /* $FreeBSD: releng/9.0/sys/arm/at91/at91_rstreg.h 213496 2010-10-06 22:25:21Z cognet $ */
   27 
   28 #ifndef ARM_AT91_AT91RSTREG_H
   29 #define ARM_AT91_AT91RSTREG_H
   30 
   31 #define RST_CR          0x0     /* Control Register */
   32 #define RST_SR          0x4     /* Status Register */
   33 #define RST_MR          0x8     /* Mode Register */
   34 
   35 /* RST_CR */
   36 #define RST_CR_PROCRST          (1<<0)
   37 #define RST_CR_PERRST           (1<<2)
   38 #define RST_CR_EXTRST           (1<<3)
   39 #define RST_CR_KEY              (0xa5<<24)
   40 
   41 /* RST_SR */
   42 #define RST_SR_SRCMP            (1<<17) /* Software Reset in progress */        
   43 #define RST_SR_NRSTL            (1<<16) /* NRST pin level at MCK */     
   44 #define RST_SR_URSTS            (1<<0)  /* NRST pin has been active */  
   45 
   46 #define RST_SR_RST_POW          (0<<8)  /* General (Power On) reset */  
   47 #define RST_SR_RST_WAKE         (1<<8)  /* Wake-up reset */
   48 #define RST_SR_RST_WDT          (2<<8)  /* Watchdog reset */
   49 #define RST_SR_RST_SOFT         (3<<8)  /* Software  reset */
   50 #define RST_SR_RST_USR          (4<<8)  /* User (External) reset */
   51 #define RST_SR_RST_MASK         (7<<8)  /* User (External) reset */
   52 
   53 /* RST_MR */
   54 #define RST_MR_URSTEN           (1<<0)  /* User reset enable */ 
   55 #define RST_MR_URSIEN           (1<<4)  /* User interrupt enable */     
   56 #define RST_MR_ERSTL(x)         ((x)<<8) /* External reset length */    
   57 #define RST_MR_KEY              (0xa5<<24)
   58 
   59 #endif /* ARM_AT91_AT91RSTREG_H */

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