1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_rtcreg.h,v 1.3 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef ARM_AT91_AT91_RTCREG_H
29 #define ARM_AT91_AT91_RTCREG_H
30
31 /* Registers */
32 #define RTC_CR 0x00 /* RTC Control Register */
33 #define RTC_MR 0x04 /* RTC Mode Register */
34 #define RTC_TIMR 0x08 /* RTC Time Register */
35 #define RTC_CALR 0x0c /* RTC Calendar Register */
36 #define RTC_TIMALR 0x10 /* RTC Time Alarm Register */
37 #define RTC_CALALR 0x14 /* RTC Calendar Alarm Register */
38 #define RTC_SR 0x18 /* RTC Status Register */
39 #define RTC_SCCR 0x1c /* RTC Status Command Clear Register */
40 #define RTC_IER 0x20 /* RTC Interrupt Enable Register */
41 #define RTC_IDR 0x24 /* RTC Interrupt Disable Register */
42 #define RTC_IMR 0x28 /* RTC Interrupt Mask Register */
43 #define RTC_VER 0x2c /* RTC Valid Entry Register */
44
45 /* TIMR */
46 #define RTC_TIMR_SEC_M 0x7fUL
47 #define RTC_TIMR_SEC_S 0
48 #define RTC_TIMR_SEC(x) FROMBCD(((x) & RTC_TIMR_SEC_M) >> RTC_TIMR_SEC_S)
49 #define RTC_TIMR_MIN_M 0x7f00UL
50 #define RTC_TIMR_MIN_S 8
51 #define RTC_TIMR_MIN(x) FROMBCD(((x) & RTC_TIMR_MIN_M) >> RTC_TIMR_MIN_S)
52 #define RTC_TIMR_HR_M 0x3f0000UL
53 #define RTC_TIMR_HR_S 16
54 #define RTC_TIMR_HR(x) FROMBCD(((x) & RTC_TIMR_HR_M) >> RTC_TIMR_HR_S)
55 #define RTC_TIMR_MK(hr, min, sec) \
56 ((TOBCD(hr) << RTC_TIMR_HR_S) | \
57 (TOBCD(min) << RTC_TIMR_MIN_S) | \
58 (TOBCD(sec) << RTC_TIMR_SEC_S))
59 #define RTC_TIMR_PM (1UL << 22)
60
61 /* CALR */
62 #define RTC_CALR_CEN_M 0x0000007fUL
63 #define RTC_CALR_CEN_S 0
64 #define RTC_CALR_CEN(x) FROMBCD(((x) & RTC_CALR_CEN_M) >> RTC_CALR_CEN_S)
65 #define RTC_CALR_YEAR_M 0x0000ff00UL
66 #define RTC_CALR_YEAR_S 8
67 #define RTC_CALR_YEAR(x) FROMBCD(((x) & RTC_CALR_YEAR_M) >> RTC_CALR_YEAR_S)
68 #define RTC_CALR_MON_M 0x001f0000UL
69 #define RTC_CALR_MON_S 16
70 #define RTC_CALR_MON(x) FROMBCD(((x) & RTC_CALR_MON_M) >> RTC_CALR_MON_S)
71 #define RTC_CALR_DOW_M 0x00d0000UL
72 #define RTC_CALR_DOW_S 21
73 #define RTC_CALR_DOW(x) FROMBCD(((x) & RTC_CALR_DOW_M) >> RTC_CALR_DOW_S)
74 #define RTC_CALR_DAY_M 0x3f00000UL
75 #define RTC_CALR_DAY_S 24
76 #define RTC_CALR_DAY(x) FROMBCD(((x) & RTC_CALR_DAY_M) >> RTC_CALR_DAY_S)
77 #define RTC_CALR_MK(yr, mon, day, dow) \
78 ((TOBCD((yr) / 100 + 19) << RTC_CALR_CEN_S) | \
79 (TOBCD((yr) % 100) << RTC_CALR_YEAR_S) | \
80 (TOBCD(mon) << RTC_CALR_MON_S) | \
81 (TOBCD(dow) << RTC_CALR_DOW_S) | \
82 (TOBCD(day) << RTC_CALR_DAY_S))
83
84 #endif /* ARM_AT91_AT91_RTCREG_H */
85 Cache object: 8a2e78ebfa03969efa51b7f67e041ce8
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