at91_smc.h

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    1 /*-
    2  * Copyright (c) 2014 M. Warner Losh.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 /* $FreeBSD$ */
   27 
   28 #ifndef ARM_AT91_AT91_SMC_H
   29 #define ARM_AT91_AT91_SMC_H
   30 
   31 /* Registers */
   32 #define SMC_SETUP       0x00
   33 #define SMC_PULSE       0x04
   34 #define SMC_CYCLE       0x08
   35 #define SMC_MODE        0x0C
   36 
   37 #define SMC_CS_OFF(cs)  (0x10 * (cs))
   38 
   39 /* Setup */
   40 #define SMC_SETUP_NCS_RD_SETUP(x)       ((x) << 24)
   41 #define SMC_SETUP_NRD_SETUP(x)          ((x) << 16)
   42 #define SMC_SETUP_NCS_WR_SETUP(x)       ((x) << 8)
   43 #define SMC_SETUP_NWE_SETUP(x)          (x)
   44 
   45 /* Pulse */
   46 #define SMC_PULSE_NCS_RD_PULSE(x)       ((x) << 24)
   47 #define SMC_PULSE_NRD_PULSE(x)          ((x) << 16)
   48 #define SMC_PULSE_NCS_WR_PULSE(x)       ((x) << 8)
   49 #define SMC_PULSE_NWE_PULSE(x)          (x)
   50 
   51 /* Cycle */
   52 #define SMC_CYCLE_NRD_CYCLE(x)          ((x) << 16)
   53 #define SMC_CYCLE_NWE_CYCLE(x)          (x)
   54 
   55 /* Mode */
   56 #define SMC_MODE_READ                   (1 << 0)
   57 #define SMC_MODE_WRITE                  (1 << 1)
   58 #define SMC_MODE_EXNW_DISABLED          (0 << 4)
   59 #define SMC_MODE_EXNW_FROZEN_MODE       (2 << 4)
   60 #define SMC_MODE_EXNW_READY_MODE        (3 << 4)
   61 #define SMC_MODE_BAT                    (1 << 8)
   62 #define SMC_MODE_DBW_8BIT               (0 << 12)
   63 #define SMC_MODE_DBW_16BIT              (1 << 12)
   64 #define SMC_MODE_DBW_32_BIT             (2 << 12)
   65 #define SMC_MODE_TDF_CYCLES(x)          ((x) << 16)
   66 #define SMC_MODE_TDF_MODE               (1 << 20)
   67 #define SMC_MODE_PMEN                   (1 << 24)
   68 #define SMC_PS_4BYTE                    (0 << 28)
   69 #define SMC_PS_8BYTE                    (1 << 28)
   70 #define SMC_PS_16BYTE                   (2 << 28)
   71 #define SMC_PS_32BYTE                   (3 << 28)
   72 
   73 /*
   74  * structure to ease init. See the SMC chapter in the datasheet for
   75  * the appropriate SoC you are using for details.
   76  */
   77 struct at91_smc_init
   78 {
   79         /* Setup register */
   80         uint8_t ncs_rd_setup;
   81         uint8_t nrd_setup;
   82         uint8_t ncs_wr_setup;
   83         uint8_t nwe_setup;
   84 
   85         /* Pulse register */
   86         uint8_t ncs_rd_pulse;
   87         uint8_t nrd_pulse;
   88         uint8_t ncs_wr_pulse;
   89         uint8_t nwe_pulse;
   90 
   91         /* Cycle register */
   92         uint16_t nrd_cycle;
   93         uint16_t nwe_cycle;
   94 
   95         /* Mode register */
   96         uint8_t mode;           /* Combo of READ/WRITE/EXNW fields */
   97         uint8_t bat;
   98         uint8_t dwb;
   99         uint8_t tdf_cycles;
  100         uint8_t tdf_mode;
  101         uint8_t pmen;
  102         uint8_t ps;
  103 };
  104 
  105 /*
  106  * Convenience routine to fill in SMC registers for a given chip select.
  107  */
  108 void at91_smc_setup(int id, int cs, const struct at91_smc_init *smc);
  109 
  110 /*
  111  * Disable/Enable different External Bus Interfaces (EBI)
  112  */
  113 void at91_ebi_enable(int cs);
  114 void at91_ebi_disable(int cs);
  115 
  116 #endif /* ARM_AT91_AT91_SMC_H */

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FreeBSD/Linux Kernel Cross Reference sys/arm/at91/at91_smc.h

FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_smc.h