Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_spi.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2006 M. Warner Losh. 3 * Copyright (c) 2011-2012 Ian Lepore. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/sx.h> 44 45 #include <machine/bus.h> 46 47 #include <arm/at91/at91var.h> 48 #include <arm/at91/at91_spireg.h> 49 #include <arm/at91/at91_pdcreg.h> 50 51 #include <dev/spibus/spi.h> 52 #include <dev/spibus/spibusvar.h> 53 54 #ifdef FDT 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/ofw_bus_subr.h> 58 #endif 59 60 #include "spibus_if.h" 61 62 struct at91_spi_softc 63 { 64 device_t dev; /* Myself */ 65 void *intrhand; /* Interrupt handle */ 66 struct resource *irq_res; /* IRQ resource */ 67 struct resource *mem_res; /* Memory resource */ 68 bus_dma_tag_t dmatag; /* bus dma tag for transfers */ 69 bus_dmamap_t map[4]; /* Maps for the transaction */ 70 struct sx xfer_mtx; /* Enforce one transfer at a time */ 71 uint32_t xfer_done; /* interrupt<->mainthread signaling */ 72 }; 73 74 #define CS_TO_MR(cs) ((~(1 << (cs)) & 0x0f) << 16) 75 76 static inline uint32_t 77 RD4(struct at91_spi_softc *sc, bus_size_t off) 78 { 79 80 return (bus_read_4(sc->mem_res, off)); 81 } 82 83 static inline void 84 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) 85 { 86 87 bus_write_4(sc->mem_res, off, val); 88 } 89 90 /* bus entry points */ 91 static int at91_spi_attach(device_t dev); 92 static int at91_spi_detach(device_t dev); 93 static int at91_spi_probe(device_t dev); 94 static int at91_spi_transfer(device_t dev, device_t child, 95 struct spi_command *cmd); 96 97 /* helper routines */ 98 static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, 99 int error); 100 static int at91_spi_activate(device_t dev); 101 static void at91_spi_deactivate(device_t dev); 102 static void at91_spi_intr(void *arg); 103 104 static int 105 at91_spi_probe(device_t dev) 106 { 107 #ifdef FDT 108 if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-spi")) 109 return (ENXIO); 110 #endif 111 device_set_desc(dev, "AT91 SPI"); 112 return (0); 113 } 114 115 static int 116 at91_spi_attach(device_t dev) 117 { 118 struct at91_spi_softc *sc; 119 int err; 120 uint32_t csr; 121 122 sc = device_get_softc(dev); 123 124 sc->dev = dev; 125 sx_init(&sc->xfer_mtx, device_get_nameunit(dev)); 126 127 /* 128 * Allocate resources. 129 */ 130 err = at91_spi_activate(dev); 131 if (err) 132 goto out; 133 134 #ifdef FDT 135 /* 136 * Disable devices need to hold their resources, so return now and not attach 137 * the spibus, setup interrupt handlers, etc. 138 */ 139 if (!ofw_bus_status_okay(dev)) 140 return 0; 141 #endif 142 143 /* 144 * Set up the hardware. 145 */ 146 147 WR4(sc, SPI_CR, SPI_CR_SWRST); 148 /* "Software Reset must be Written Twice" erratum */ 149 WR4(sc, SPI_CR, SPI_CR_SWRST); 150 WR4(sc, SPI_IDR, 0xffffffff); 151 152 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | 153 CS_TO_MR(0)); 154 155 /* 156 * For now, run the bus at the slowest speed possible as otherwise we 157 * may encounter data corruption on transmit as seen with ETHERNUT5 158 * and AT45DB321D even though both board and slave device can take 159 * more. 160 * This also serves as a work-around for the "NPCSx rises if no data 161 * data is to be transmitted" erratum. The ideal workaround for the 162 * latter is to take the chip select control away from the peripheral 163 * and manage it directly as a GPIO line. The easy solution is to 164 * slow down the bus so dramatically that it just never gets starved 165 * as may be seen when the OCHI controller is running and consuming 166 * memory and APB bandwidth. 167 * Also, currently we lack a way for lettting both the board and the 168 * slave devices take their maximum supported SPI clocks into account. 169 * Also, we hard-wire SPI mode to 3. 170 */ 171 csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); 172 WR4(sc, SPI_CSR0, csr); 173 WR4(sc, SPI_CSR1, csr); 174 WR4(sc, SPI_CSR2, csr); 175 WR4(sc, SPI_CSR3, csr); 176 177 WR4(sc, SPI_CR, SPI_CR_SPIEN); 178 179 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS); 180 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS); 181 WR4(sc, PDC_RNPR, 0); 182 WR4(sc, PDC_RNCR, 0); 183 WR4(sc, PDC_TNPR, 0); 184 WR4(sc, PDC_TNCR, 0); 185 WR4(sc, PDC_RPR, 0); 186 WR4(sc, PDC_RCR, 0); 187 WR4(sc, PDC_TPR, 0); 188 WR4(sc, PDC_TCR, 0); 189 RD4(sc, SPI_RDR); 190 RD4(sc, SPI_SR); 191 192 device_add_child(dev, "spibus", -1); 193 bus_generic_attach(dev); 194 out: 195 if (err) 196 at91_spi_deactivate(dev); 197 return (err); 198 } 199 200 static int 201 at91_spi_detach(device_t dev) 202 { 203 204 return (EBUSY); /* XXX */ 205 } 206 207 static int 208 at91_spi_activate(device_t dev) 209 { 210 struct at91_spi_softc *sc; 211 int err, i, rid; 212 213 sc = device_get_softc(dev); 214 err = ENOMEM; 215 216 rid = 0; 217 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 218 RF_ACTIVE); 219 if (sc->mem_res == NULL) 220 goto out; 221 222 rid = 0; 223 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 224 RF_ACTIVE); 225 if (sc->irq_res == NULL) 226 goto out; 227 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 228 NULL, at91_spi_intr, sc, &sc->intrhand); 229 if (err != 0) 230 goto out; 231 232 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 233 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2048, 1, 234 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); 235 if (err != 0) 236 goto out; 237 238 for (i = 0; i < 4; i++) { 239 err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]); 240 if (err != 0) 241 goto out; 242 } 243 out: 244 if (err != 0) 245 at91_spi_deactivate(dev); 246 return (err); 247 } 248 249 static void 250 at91_spi_deactivate(device_t dev) 251 { 252 struct at91_spi_softc *sc; 253 int i; 254 255 sc = device_get_softc(dev); 256 bus_generic_detach(dev); 257 258 for (i = 0; i < 4; i++) 259 if (sc->map[i]) 260 bus_dmamap_destroy(sc->dmatag, sc->map[i]); 261 262 if (sc->dmatag) 263 bus_dma_tag_destroy(sc->dmatag); 264 265 if (sc->intrhand) 266 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 267 sc->intrhand = NULL; 268 if (sc->irq_res) 269 bus_release_resource(dev, SYS_RES_IRQ, 270 rman_get_rid(sc->irq_res), sc->irq_res); 271 sc->irq_res = NULL; 272 273 if (sc->mem_res) 274 bus_release_resource(dev, SYS_RES_MEMORY, 275 rman_get_rid(sc->mem_res), sc->mem_res); 276 sc->mem_res = NULL; 277 } 278 279 static void 280 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs __unused, 281 int error) 282 { 283 284 if (error != 0) 285 return; 286 *(bus_addr_t *)arg = segs[0].ds_addr; 287 } 288 289 static int 290 at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 291 { 292 struct at91_spi_softc *sc; 293 bus_addr_t addr; 294 int err, i, j, mode[4], cs; 295 296 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 297 ("%s: TX/RX command sizes should be equal", __func__)); 298 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 299 ("%s: TX/RX data sizes should be equal", __func__)); 300 301 /* get the proper chip select */ 302 spibus_get_cs(child, &cs); 303 304 sc = device_get_softc(dev); 305 i = 0; 306 307 sx_xlock(&sc->xfer_mtx); 308 309 /* 310 * Disable transfers while we set things up. 311 */ 312 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 313 314 /* 315 * PSCDEC = 0 has a range of 0..3 for chip select. We 316 * don't support PSCDEC = 1 which has a range of 0..15. 317 */ 318 if (cs < 0 || cs > 3) { 319 device_printf(dev, 320 "Invalid chip select %d requested by %s\n", cs, 321 device_get_nameunit(child)); 322 err = EINVAL; 323 goto out; 324 } 325 326 #ifdef SPI_CHIP_SELECT_HIGH_SUPPORT 327 /* 328 * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we 329 * don't support that yet, or other spi modes. 330 */ 331 if (at91_is_rm92() && cs == 0 && 332 (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { 333 device_printf(dev, 334 "Invalid chip select high requested by %s for cs 0.\n", 335 device_get_nameunit(child)); 336 err = EINVAL; 337 goto out; 338 } 339 #endif 340 err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs); 341 WR4(sc, SPI_MR, err); 342 343 /* 344 * Set up the TX side of the transfer. 345 */ 346 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd, 347 cmd->tx_cmd_sz, at91_getaddr, &addr, 0)) != 0) 348 goto out; 349 WR4(sc, PDC_TPR, addr); 350 WR4(sc, PDC_TCR, cmd->tx_cmd_sz); 351 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); 352 mode[i++] = BUS_DMASYNC_POSTWRITE; 353 if (cmd->tx_data_sz > 0) { 354 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], 355 cmd->tx_data, cmd->tx_data_sz, at91_getaddr, &addr, 0)) != 356 0) 357 goto out; 358 WR4(sc, PDC_TNPR, addr); 359 WR4(sc, PDC_TNCR, cmd->tx_data_sz); 360 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); 361 mode[i++] = BUS_DMASYNC_POSTWRITE; 362 } 363 364 /* 365 * Set up the RX side of the transfer. 366 */ 367 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd, 368 cmd->rx_cmd_sz, at91_getaddr, &addr, 0)) != 0) 369 goto out; 370 WR4(sc, PDC_RPR, addr); 371 WR4(sc, PDC_RCR, cmd->rx_cmd_sz); 372 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); 373 mode[i++] = BUS_DMASYNC_POSTREAD; 374 if (cmd->rx_data_sz > 0) { 375 if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], 376 cmd->rx_data, cmd->rx_data_sz, at91_getaddr, &addr, 0)) != 377 0) 378 goto out; 379 WR4(sc, PDC_RNPR, addr); 380 WR4(sc, PDC_RNCR, cmd->rx_data_sz); 381 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); 382 mode[i++] = BUS_DMASYNC_POSTREAD; 383 } 384 385 /* 386 * Start the transfer, wait for it to complete. 387 */ 388 sc->xfer_done = 0; 389 WR4(sc, SPI_IER, SPI_SR_RXBUFF); 390 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); 391 do 392 err = tsleep(&sc->xfer_done, PCATCH | PZERO, "at91_spi", hz); 393 while (sc->xfer_done == 0 && err != EINTR); 394 395 /* 396 * Stop the transfer and clean things up. 397 */ 398 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 399 if (err == 0) 400 for (j = 0; j < i; j++) 401 bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]); 402 out: 403 for (j = 0; j < i; j++) 404 bus_dmamap_unload(sc->dmatag, sc->map[j]); 405 406 sx_xunlock(&sc->xfer_mtx); 407 408 return (err); 409 } 410 411 static void 412 at91_spi_intr(void *arg) 413 { 414 struct at91_spi_softc *sc; 415 uint32_t sr; 416 417 sc = (struct at91_spi_softc*)arg; 418 419 sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); 420 if ((sr & SPI_SR_RXBUFF) != 0) { 421 sc->xfer_done = 1; 422 WR4(sc, SPI_IDR, SPI_SR_RXBUFF); 423 wakeup(&sc->xfer_done); 424 } 425 if ((sr & ~SPI_SR_RXBUFF) != 0) { 426 device_printf(sc->dev, "Unexpected ISR %#x\n", sr); 427 WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); 428 } 429 } 430 431 static devclass_t at91_spi_devclass; 432 433 static device_method_t at91_spi_methods[] = { 434 /* Device interface */ 435 DEVMETHOD(device_probe, at91_spi_probe), 436 DEVMETHOD(device_attach, at91_spi_attach), 437 DEVMETHOD(device_detach, at91_spi_detach), 438 439 /* spibus interface */ 440 DEVMETHOD(spibus_transfer, at91_spi_transfer), 441 442 DEVMETHOD_END 443 }; 444 445 static driver_t at91_spi_driver = { 446 "spi", 447 at91_spi_methods, 448 sizeof(struct at91_spi_softc), 449 }; 450 451 #ifdef FDT 452 DRIVER_MODULE(at91_spi, simplebus, at91_spi_driver, at91_spi_devclass, NULL, 453 NULL); 454 #else 455 DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, NULL, 456 NULL); 457 #endif
Cache object: ec830da83a264e6469af5d553d944441
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]