1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_spireg.h,v 1.4 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef ARM_AT91_AT91_SPIREG_H
29 #define ARM_AT91_AT91_SPIREG_H
30
31 #define SPI_CR 0x00 /* CR: Control Register */
32 #define SPI_CR_SPIEN 0x1
33 #define SPI_CR_SPIDIS 0x2
34 #define SPI_CR_SWRST 0x8
35 #define SPI_MR 0x04 /* MR: Mode Register */
36 #define SPI_MR_MSTR 0x01
37 #define SPI_MR_PS 0x02
38 #define SPI_MR_PCSDEC 0x04
39 #define SPI_MR_DIV32 0x08
40 #define SPI_MR_MODFDIS 0x10
41 #define SPI_MR_LLB 0x80
42 #define SPI_MR_PSC_CS0 0xe0000
43 #define SPI_MR_PSC_CS1 0xd0000
44 #define SPI_MR_PSC_CS2 0xb0000
45 #define SPI_MR_PSC_CS3 0x70000
46 #define SPI_RDR 0x08 /* RDR: Receive Data Register */
47 #define SPI_TDR 0x0c /* TDR: Transmit Data Register */
48 #define SPI_SR 0x10 /* SR: Status Register */
49 #define SPI_SR_RDRF 0x00001
50 #define SPI_SR_TDRE 0x00002
51 #define SPI_SR_MODF 0x00004
52 #define SPI_SR_OVRES 0x00008
53 #define SPI_SR_ENDRX 0x00010
54 #define SPI_SR_ENDTX 0x00020
55 #define SPI_SR_RXBUFF 0x00040
56 #define SPI_SR_TXBUFE 0x00080
57 #define SPI_SR_SPIENS 0x10000
58 #define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
59 #define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
60 #define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
61 #define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
62 #define SPI_CSR_CPOL 0x01
63 #define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
64 #define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
65 #define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
66
67 #endif /* ARM_AT91_AT91_SPIREG_H */
68 Cache object: 5625a55a713c064c3e1213c1cb1b5a9b
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