1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_sscreg.h,v 1.4 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef ARM_AT91_AT91_SSCREG_H
29 #define ARM_AT91_AT91_SSCREG_H
30
31 /* Registers */
32 #define SSC_CR 0x00 /* Control Register */
33 #define SSC_CMR 0x04 /* Clock Mode Register */
34 /* 0x08 Reserved */
35 /* 0x0c Reserved */
36 #define SSC_RCMR 0x10 /* Receive Clock Mode Register */
37 #define SSC_RFMR 0x14 /* Receive Frame Mode Register */
38 #define SSC_TCMR 0x18 /* Transmit Clock Mode Register */
39 #define SSC_TFMR 0x1c /* Transmit Frame Mode register */
40 #define SSC_RHR 0x20 /* Receive Holding Register */
41 #define SSC_THR 0x24 /* Transmit Holding Register */
42 /* 0x28 Reserved */
43 /* 0x2c Reserved */
44 #define SSC_RSHR 0x30 /* Receive Sync Holding Register */
45 #define SSC_TSHR 0x34 /* Transmit Sync Holding Register */
46 /* 0x38 Reserved */
47 /* 0x3c Reserved */
48 #define SSC_SR 0x40 /* Status Register */
49 #define SSC_IER 0x44 /* Interrupt Enable Register */
50 #define SSC_IDR 0x48 /* Interrupt Disable Register */
51 #define SSC_IMR 0x4c /* Interrupt Mask Register */
52 /* And PDC registers */
53
54 /* SSC_CR */
55 #define SSC_CR_RXEN (1u << 0) /* RXEN: Receive Enable */
56 #define SSC_CR_RXDIS (1u << 1) /* RXDIS: Receive Disable */
57 #define SSC_CR_TXEN (1u << 8) /* TXEN: Transmit Enable */
58 #define SSC_CR_TXDIS (1u << 9) /* TXDIS: Transmit Disable */
59 #define SSC_CR_SWRST (1u << 15) /* SWRST: Software Reset */
60
61 /* SSC_CMR */
62 #define SSC_CMR_DIV 0xfffu /* DIV: Clock Divider mask */
63
64 /* SSC_RCMR */
65 #define SSC_RCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
66 #define SSC_RCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
67 #define SSC_RCMR_START (0xfu << 8) /* START: Receive Start Sel */
68 #define SSC_RCMR_START_CONT (0u << 8)
69 #define SSC_RCMR_START_TX_START (1u << 8)
70 #define SSC_RCMR_START_LOW_RF (2u << 8)
71 #define SSC_RCMR_START_HIGH_RF (3u << 8)
72 #define SSC_RCMR_START_FALL_EDGE_RF (4u << 8)
73 #define SSC_RCMR_START_RISE_EDGE_RF (5u << 8)
74 #define SSC_RCMR_START_LEVEL_CHANGE_RF (6u << 8)
75 #define SSC_RCMR_START_ANY_EDGE_RF (7u << 8)
76 #define SSC_RCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
77 #define SSC_RCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
78 #define SSC_RCMR_CKO_NONE (0u << 2)
79 #define SSC_RCMR_CKO_CONTINUOUS (1u << 2)
80 #define SSC_RCMR_CKS (3u) /* CKS: Receive Clock Selection */
81 #define SSC_RCMR_CKS_DIVIDED (0)
82 #define SSC_RCMR_CKS_TK_CLOCK (1)
83 #define SSC_RCMR_CKS_RK (2)
84
85 /* SSC_RFMR */
86 #define SSC_RFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
87 #define SSC_RFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
88 #define SSC_RFMR_FSOS_NONE (0u << 20)
89 #define SSC_RFMR_FSOS_NEG_PULSE (1u << 20)
90 #define SSC_RFMR_FSOS_POS_PULSE (2u << 20)
91 #define SSC_RFMR_FSOS_LOW (3u << 20)
92 #define SSC_RFMR_FSOS_HIGH (4u << 20)
93 #define SSC_RFMR_FSOS_TOGGLE (5u << 20)
94 #define SSC_RFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
95 #define SSC_RFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
96 #define SSC_RFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
97 #define SSC_RFMR_LOOP (1u << 5) /* LOOP: Loop Mode */
98 #define SSC_RFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
99
100 /* SSC_TCMR */
101 #define SSC_TCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
102 #define SSC_TCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
103 #define SSC_TCMR_START (0xfu << 8) /* START: Receive Start Sel */
104 #define SSC_TCMR_START_CONT (0u << 8)
105 #define SSC_TCMR_START_RX_START (1u << 8)
106 #define SSC_TCMR_START_LOW_RF (2u << 8)
107 #define SSC_TCMR_START_HIGH_RF (3u << 8)
108 #define SSC_TCMR_START_FALL_EDGE_RF (4u << 8)
109 #define SSC_TCMR_START_RISE_EDGE_RF (5u << 8)
110 #define SSC_TCMR_START_LEVEL_CHANGE_RF (6u << 8)
111 #define SSC_TCMR_START_ANY_EDGE_RF (7u << 8)
112 #define SSC_TCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
113 #define SSC_TCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
114 #define SSC_TCMR_CKO_NONE (0u << 2)
115 #define SSC_TCMR_CKO_CONTINUOUS (1u << 2)
116 #define SSC_TCMR_CKS (3u) /* CKS: Receive Clock Selection */
117 #define SSC_TCMR_CKS_DIVIDED (0)
118 #define SSC_TCMR_CKS_RK_CLOCK (1)
119 #define SSC_TCMR_CKS_TK (2)
120
121 /* SSC_TFMR */
122 #define SSC_TFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
123 #define SSC_TFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
124 #define SSC_TFMR_FSOS_NONE (0u << 20)
125 #define SSC_TFMR_FSOS_NEG_PULSE (1u << 20)
126 #define SSC_TFMR_FSOS_POS_PULSE (2u << 20)
127 #define SSC_TFMR_FSOS_LOW (3u << 20)
128 #define SSC_TFMR_FSOS_HIGH (4u << 20)
129 #define SSC_TFMR_FSOS_TOGGLE (5u << 20)
130 #define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
131 #define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
132 #define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
133 #define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */
134 #define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
135
136 /* SSC_SR */
137 #define SSC_SR_TXRDY (1u << 0)
138 #define SSC_SR_TXEMPTY (1u << 1)
139 #define SSC_SR_ENDTX (1u << 2)
140 #define SSC_SR_TXBUFE (1u << 3)
141 #define SSC_SR_RXRDY (1u << 4)
142 #define SSC_SR_OVRUN (1u << 5)
143 #define SSC_SR_ENDRX (1u << 6)
144 #define SSC_SR_RXBUFF (1u << 7)
145 #define SSC_SR_TXSYN (1u << 10)
146 #define SSC_SR_RSSYN (1u << 11)
147 #define SSC_SR_TXEN (1u << 16)
148 #define SSC_SR_RXEN (1u << 17)
149
150 #endif /* ARM_AT91_AT91_SSCREG_H */
151 Cache object: 7efe56e41ccde3e0097f779ffdff1d6a
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