at91_st.c

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    1 /*-
    2  * Copyright (c) 2005 Olivier Houchard.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD$");
   28 
   29 #include <sys/param.h>
   30 #include <sys/systm.h>
   31 #include <sys/kernel.h>
   32 #include <sys/module.h>
   33 #include <sys/time.h>
   34 #include <sys/bus.h>
   35 #include <sys/resource.h>
   36 #include <sys/rman.h>
   37 #include <sys/timetc.h>
   38 #include <sys/watchdog.h>
   39 
   40 #include <machine/bus.h>
   41 #include <machine/cpu.h>
   42 #include <machine/cpufunc.h>
   43 #include <machine/resource.h>
   44 #include <machine/frame.h>
   45 #include <machine/intr.h>
   46 #include <arm/at91/at91var.h>
   47 #include <arm/at91/at91_streg.h>
   48 #include <arm/at91/at91rm92reg.h>
   49 
   50 static struct at91_st_softc {
   51         struct resource *       sc_irq_res;
   52         struct resource *       sc_mem_res;
   53         void *                  sc_intrhand;
   54         eventhandler_tag        sc_wet; /* watchdog event handler tag */
   55 } *timer_softc;
   56 
   57 static inline uint32_t
   58 RD4(bus_size_t off)
   59 {
   60 
   61         if (timer_softc == NULL) {
   62                 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
   63 
   64                 return *p;
   65         }
   66 
   67         return (bus_read_4(timer_softc->sc_mem_res, off));
   68 }
   69 
   70 static inline void
   71 WR4(bus_size_t off, uint32_t val)
   72 {
   73 
   74         if (timer_softc == NULL) {
   75                 uint32_t *p = (uint32_t *)(AT91_BASE + AT91RM92_ST_BASE + off);
   76 
   77                 *p = val;
   78         }
   79         else
   80                 bus_write_4(timer_softc->sc_mem_res, off, val);
   81 }
   82 
   83 static void at91_st_watchdog(void *, u_int, int *);
   84 static void at91_st_initclocks(device_t , struct at91_st_softc *);
   85 
   86 static inline int
   87 st_crtr(void)
   88 {
   89         int cur1, cur2;
   90         do {
   91                 cur1 = RD4(ST_CRTR);
   92                 cur2 = RD4(ST_CRTR);
   93         } while (cur1 != cur2);
   94         return (cur1);
   95 }
   96 
   97 static unsigned at91_st_get_timecount(struct timecounter *tc);
   98 
   99 static struct timecounter at91_st_timecounter = {
  100         at91_st_get_timecount, /* get_timecount */
  101         NULL, /* no poll_pps */
  102         0xfffffu, /* counter_mask */
  103         32768, /* frequency */
  104         "AT91RM9200 timer", /* name */
  105         1000 /* quality */
  106 };
  107 
  108 static int
  109 clock_intr(void *arg)
  110 {
  111         struct trapframe *fp = arg;
  112 
  113         /* The interrupt is shared, so we have to make sure it's for us. */
  114         if (RD4(ST_SR) & ST_SR_PITS) {
  115                 hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
  116                 return (FILTER_HANDLED);
  117         }
  118         return (FILTER_STRAY);
  119 }
  120 
  121 void
  122 at91_st_delay(int n)
  123 {
  124         uint32_t start, end, cur;
  125 
  126         start = st_crtr();
  127         n = (n * 1000) / 32768;
  128         if (n <= 0)
  129                 n = 1;
  130         end = (start + n) & ST_CRTR_MASK;
  131         cur = start;
  132         if (start > end) {
  133                 while (cur >= start || cur < end)
  134                         cur = st_crtr();
  135         } else {
  136                 while (cur < end)
  137                         cur = st_crtr();
  138         }
  139 }
  140 
  141 void
  142 at91_st_cpu_reset(void)
  143 {
  144         /*
  145          * Reset the CPU by programmig the watchdog timer to reset the
  146          * CPU after 128 'slow' clocks, or about ~4ms.  Loop until
  147          * the reset happens for safety.
  148          */
  149         WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
  150         WR4(ST_CR, ST_CR_WDRST);
  151         while (1)
  152                 continue;
  153 }
  154 
  155 static int
  156 at91_st_probe(device_t dev)
  157 {
  158 
  159         device_set_desc(dev, "ST");
  160         return (0);
  161 }
  162 
  163 static void
  164 at91_st_deactivate(device_t dev)
  165 {
  166         struct at91_st_softc *sc = timer_softc;
  167 
  168         if (sc->sc_intrhand)
  169                 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
  170         sc->sc_intrhand = NULL;
  171 
  172         if (sc->sc_irq_res)
  173                 bus_release_resource(dev, SYS_RES_IRQ,
  174                     rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
  175         sc->sc_irq_res = NULL;
  176 
  177         if (sc->sc_mem_res)
  178                 bus_release_resource(dev, SYS_RES_MEMORY,
  179                     rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
  180         sc->sc_mem_res = NULL;
  181 }
  182 
  183 static int
  184 at91_st_activate(device_t dev)
  185 {
  186         int rid;
  187         int err;
  188         struct at91_st_softc *sc = timer_softc;
  189 
  190         rid = 0;
  191         sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  192             RF_ACTIVE);
  193         err = ENOMEM;
  194         if (sc->sc_mem_res == NULL)
  195                 goto out;
  196         /* Disable all interrupts */
  197         WR4(ST_IDR, 0xffffffff);
  198 
  199         /* The system timer shares the system irq (1) */
  200         rid = 0;
  201         sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
  202             RF_ACTIVE | RF_SHAREABLE);
  203         if (sc->sc_irq_res == NULL) {
  204                 printf("Unable to allocate irq for the system timer");
  205                 goto out;
  206         }
  207         err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_CLK, clock_intr,
  208             NULL, NULL, &sc->sc_intrhand);
  209 out:
  210         if (err != 0)
  211                 at91_st_deactivate(dev);
  212         return (err);
  213 }
  214 
  215 static int
  216 at91_st_attach(device_t dev)
  217 {
  218         int err;
  219 
  220         timer_softc = device_get_softc(dev);
  221         err = at91_st_activate(dev);
  222         if (err)
  223                 return err;
  224 
  225         timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
  226           at91_st_watchdog, dev, 0);
  227 
  228         device_printf(dev,
  229           "watchdog registered, timeout intervall max. 64 sec\n");
  230 
  231         at91_st_initclocks(dev, timer_softc);
  232         return (0);
  233 }
  234 
  235 static device_method_t at91_st_methods[] = {
  236         DEVMETHOD(device_probe, at91_st_probe),
  237         DEVMETHOD(device_attach, at91_st_attach),
  238         {0, 0},
  239 };
  240 
  241 static driver_t at91_st_driver = {
  242         "at91_st",
  243         at91_st_methods,
  244         sizeof(struct at91_st_softc),
  245 };
  246 static devclass_t at91_st_devclass;
  247 
  248 DRIVER_MODULE(at91_st, atmelarm, at91_st_driver, at91_st_devclass, 0, 0);
  249 
  250 static unsigned
  251 at91_st_get_timecount(struct timecounter *tc)
  252 {
  253         return (st_crtr());
  254 }
  255 
  256 /*
  257  * t below is in a weird unit.  The watchdog is set to 2^t
  258  * nanoseconds.  Since our watchdog timer can't really do that too
  259  * well, we approximate it by assuming that the timeout interval for
  260  * the lsb is 2^22 ns, which is 4.194ms.  This is an overestimation of
  261  * the actual time (3.906ms), but close enough for watchdogging.
  262  * These approximations, though a violation of the spec, improve the
  263  * performance of the application which typically specifies things as
  264  * WD_TO_32SEC.  In that last case, we'd wait 32s before the wdog
  265  * reset.  The spec says we should wait closer to 34s, but given how
  266  * it is likely to be used, and the extremely coarse nature time
  267  * interval, I think this is the best solution.
  268  */
  269 static void
  270 at91_st_watchdog(void *argp, u_int cmd, int *error)
  271 {
  272         uint32_t wdog;
  273         int t;
  274 
  275         t = cmd & WD_INTERVAL;
  276         if (t >= 22 && t <= 37) {
  277                 wdog = (1 << (t - 22)) | ST_WDMR_RSTEN;
  278                 *error = 0;
  279         } else {
  280                 wdog = 0;
  281         }
  282         WR4(ST_WDMR, wdog);
  283         WR4(ST_CR, ST_CR_WDRST);
  284 }
  285 
  286 static void
  287 at91_st_initclocks(device_t dev, struct at91_st_softc *sc)
  288 {
  289         int rel_value;
  290 
  291         /*
  292          * Real time counter increments every clock cycle, need to set before
  293          * initializing clocks so that DELAY works.
  294          */
  295         WR4(ST_RTMR, 1);
  296         /* disable watchdog timer */
  297         WR4(ST_WDMR, 0);
  298 
  299         rel_value = 32768 / hz;
  300         if (rel_value < 1)
  301                 rel_value = 1;
  302         if (32768 % hz) {
  303                 device_printf(dev, "Cannot get %d Hz clock; using %dHz\n", hz,
  304                     32768 / rel_value);
  305                 hz = 32768 / rel_value;
  306                 tick = 1000000 / hz;
  307         }
  308         WR4(ST_PIMR, rel_value);
  309 
  310         /* Enable PITS interrupts. */
  311         WR4(ST_IER, ST_SR_PITS);
  312         tc_init(&at91_st_timecounter);
  313 }

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FreeBSD/Linux Kernel Cross Reference sys/arm/at91/at91_st.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_st.c