The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_streg.h

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    1 /*-
    2  * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  */
   24 
   25 /* $FreeBSD: releng/6.2/sys/arm/at91/at91_streg.h 159907 2006-06-23 23:35:36Z cognet $ */
   26 
   27 #ifndef ARM_AT91_AT91STREG_H
   28 #define ARM_AT91_AT91STREG_H
   29 
   30 #define ST_CR           0x00 /* Control register */
   31 #define ST_PIMR         0x04 /* Period interval mode register */
   32 #define ST_WDMR         0x08 /* Watchdog mode register */
   33 #define ST_RTMR         0x0c /* Real-time mode register */
   34 #define ST_SR           0x10 /* Status register */
   35 #define ST_IER          0x14 /* Interrupt enable register */
   36 #define ST_IDR          0x18 /* Interrupt disable register */
   37 #define ST_IMR          0x1c /* Interrupt mask register */
   38 #define ST_RTAR         0x20 /* Real-time alarm register */
   39 #define ST_CRTR         0x24 /* Current real-time register */
   40 
   41 /* ST_CR */
   42 #define ST_CR_WDRST     (1U << 0) /* WDRST: Watchdog Timer Restart */
   43 
   44 /* ST_WDMR */
   45 #define ST_WDMR_EXTEN   (1U << 17) /* EXTEN: External Signal Assert Enable */
   46 #define ST_WDMR_RSTEN   (1U << 16) /* RSTEN: Reset Enable */
   47 
   48 /* ST_SR, ST_IER, ST_IDR, ST_IMR */
   49 #define ST_SR_PITS      (1U << 0) /* PITS: Period Interval Timer Status */
   50 #define ST_SR_WDOVF     (1U << 1) /* WDOVF: Watchdog Overflow */
   51 #define ST_SR_RTTINC    (1U << 2) /* RTTINC: Real-time Timer Increment */
   52 #define ST_SR_ALMS      (1U << 3) /* ALMS: Alarm Status */
   53 
   54 /* ST_CRTR */
   55 #define ST_CRTR_MASK    0xfffff /* 20-bit counter */
   56 
   57 #endif /* ARM_AT91_AT91STREG_H */

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