Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91_twi.c
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1 /*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/conf.h> 32 #include <sys/kernel.h> 33 #include <sys/lock.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <machine/bus.h> 40 41 #include <arm/at91/at91rm92reg.h> 42 #include <arm/at91/at91_twireg.h> 43 44 #include <dev/iicbus/iiconf.h> 45 #include <dev/iicbus/iicbus.h> 46 #include "iicbus_if.h" 47 48 #define TWI_SLOW_CLOCK 1500 49 #define TWI_FAST_CLOCK 45000 50 #define TWI_FASTEST_CLOCK 90000 51 52 struct at91_twi_softc 53 { 54 device_t dev; /* Myself */ 55 void *intrhand; /* Interrupt handle */ 56 struct resource *irq_res; /* IRQ resource */ 57 struct resource *mem_res; /* Memory resource */ 58 struct mtx sc_mtx; /* basically a perimeter lock */ 59 volatile uint32_t flags; 60 uint32_t cwgr; 61 int sc_started; 62 int twi_addr; 63 device_t iicbus; 64 }; 65 66 static inline uint32_t 67 RD4(struct at91_twi_softc *sc, bus_size_t off) 68 { 69 return bus_read_4(sc->mem_res, off); 70 } 71 72 static inline void 73 WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) 74 { 75 bus_write_4(sc->mem_res, off, val); 76 } 77 78 #define AT91_TWI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 79 #define AT91_TWI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 80 #define AT91_TWI_LOCK_INIT(_sc) \ 81 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 82 "twi", MTX_DEF) 83 #define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 84 #define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 85 #define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 86 #define TWI_DEF_CLK 100000 87 88 static devclass_t at91_twi_devclass; 89 90 /* bus entry points */ 91 92 static int at91_twi_probe(device_t dev); 93 static int at91_twi_attach(device_t dev); 94 static int at91_twi_detach(device_t dev); 95 static void at91_twi_intr(void *); 96 97 /* helper routines */ 98 static int at91_twi_activate(device_t dev); 99 static void at91_twi_deactivate(device_t dev); 100 101 static int 102 at91_twi_probe(device_t dev) 103 { 104 device_set_desc(dev, "TWI"); 105 return (0); 106 } 107 108 static int 109 at91_twi_attach(device_t dev) 110 { 111 struct at91_twi_softc *sc = device_get_softc(dev); 112 int err; 113 114 sc->dev = dev; 115 err = at91_twi_activate(dev); 116 if (err) 117 goto out; 118 119 AT91_TWI_LOCK_INIT(sc); 120 121 /* 122 * Activate the interrupt 123 */ 124 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 125 NULL, at91_twi_intr, sc, &sc->intrhand); 126 if (err) { 127 AT91_TWI_LOCK_DESTROY(sc); 128 goto out; 129 } 130 sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / TWI_FASTEST_CLOCK) | 131 TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) | 132 TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK)); 133 WR4(sc, TWI_CR, TWI_CR_SWRST); 134 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 135 WR4(sc, TWI_CWGR, sc->cwgr); 136 137 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) 138 device_printf(dev, "could not allocate iicbus instance\n"); 139 /* probe and attach the iicbus */ 140 bus_generic_attach(dev); 141 out:; 142 if (err) 143 at91_twi_deactivate(dev); 144 return (err); 145 } 146 147 static int 148 at91_twi_detach(device_t dev) 149 { 150 struct at91_twi_softc *sc; 151 int rv; 152 153 sc = device_get_softc(dev); 154 at91_twi_deactivate(dev); 155 if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0) 156 return (rv); 157 158 return (0); 159 } 160 161 static int 162 at91_twi_activate(device_t dev) 163 { 164 struct at91_twi_softc *sc; 165 int rid; 166 167 sc = device_get_softc(dev); 168 rid = 0; 169 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 170 RF_ACTIVE); 171 if (sc->mem_res == NULL) 172 goto errout; 173 rid = 0; 174 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 175 RF_ACTIVE); 176 if (sc->irq_res == NULL) 177 goto errout; 178 return (0); 179 errout: 180 at91_twi_deactivate(dev); 181 return (ENOMEM); 182 } 183 184 static void 185 at91_twi_deactivate(device_t dev) 186 { 187 struct at91_twi_softc *sc; 188 189 sc = device_get_softc(dev); 190 if (sc->intrhand) 191 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 192 sc->intrhand = 0; 193 bus_generic_detach(sc->dev); 194 if (sc->mem_res) 195 bus_release_resource(dev, SYS_RES_MEMORY, 196 rman_get_rid(sc->mem_res), sc->mem_res); 197 sc->mem_res = 0; 198 if (sc->irq_res) 199 bus_release_resource(dev, SYS_RES_IRQ, 200 rman_get_rid(sc->irq_res), sc->irq_res); 201 sc->irq_res = 0; 202 return; 203 } 204 205 static void 206 at91_twi_intr(void *xsc) 207 { 208 struct at91_twi_softc *sc = xsc; 209 uint32_t status; 210 211 status = RD4(sc, TWI_SR); 212 if (status == 0) 213 return; 214 sc->flags |= status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK); 215 if (status & TWI_SR_RXRDY) 216 sc->flags |= TWI_SR_RXRDY; 217 if (status & TWI_SR_TXRDY) 218 sc->flags |= TWI_SR_TXRDY; 219 if (status & TWI_SR_TXCOMP) 220 sc->flags |= TWI_SR_TXCOMP; 221 WR4(sc, TWI_IDR, status); 222 wakeup(sc); 223 return; 224 } 225 226 static int 227 at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit) 228 { 229 int err = 0; 230 int counter = 100000; 231 uint32_t sr; 232 233 while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 && 234 !(sr & TWI_SR_NACK)) 235 continue; 236 if (counter <= 0) 237 err = EBUSY; 238 else if (sr & TWI_SR_NACK) 239 err = ENXIO; // iic nack convention 240 return (err); 241 } 242 243 static int 244 at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 245 { 246 struct at91_twi_softc *sc; 247 int clk; 248 249 sc = device_get_softc(dev); 250 if (oldaddr) 251 *oldaddr = sc->twi_addr; 252 sc->twi_addr = addr; 253 254 /* 255 * speeds are for 1.5kb/s, 45kb/s and 90kb/s. 256 */ 257 switch (speed) { 258 case IIC_SLOW: 259 clk = TWI_SLOW_CLOCK; 260 break; 261 262 case IIC_FAST: 263 clk = TWI_FAST_CLOCK; 264 break; 265 266 case IIC_UNKNOWN: 267 case IIC_FASTEST: 268 default: 269 clk = TWI_FASTEST_CLOCK; 270 break; 271 } 272 sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) | 273 TWI_CWGR_CLDIV(TWI_CWGR_DIV(clk)); 274 WR4(sc, TWI_CR, TWI_CR_SWRST); 275 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 276 WR4(sc, TWI_CWGR, sc->cwgr); 277 printf("setting cwgr to %#x\n", sc->cwgr); 278 279 return 0; 280 } 281 282 static int 283 at91_twi_callback(device_t dev, int index, caddr_t *data) 284 { 285 int error = 0; 286 287 switch (index) { 288 case IIC_REQUEST_BUS: 289 break; 290 291 case IIC_RELEASE_BUS: 292 break; 293 294 default: 295 error = EINVAL; 296 } 297 298 return (error); 299 } 300 301 static int 302 at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 303 { 304 struct at91_twi_softc *sc; 305 int i, len, err; 306 uint32_t rdwr; 307 uint8_t *buf; 308 uint32_t sr; 309 310 sc = device_get_softc(dev); 311 err = 0; 312 AT91_TWI_LOCK(sc); 313 for (i = 0; i < nmsgs; i++) { 314 /* 315 * The linux atmel driver doesn't use the internal device 316 * address feature of twi. A separate i2c message needs to 317 * be written to use this. 318 * See http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html 319 * for details. Upon reflection, we could use this as an 320 * optimization, but it is unclear the code bloat will 321 * result in faster/better operations. 322 */ 323 rdwr = (msgs[i].flags & IIC_M_RD) ? TWI_MMR_MREAD : 0; 324 WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); 325 len = msgs[i].len; 326 buf = msgs[i].buf; 327 /* zero byte transfers aren't allowed */ 328 if (len == 0 || buf == NULL) { 329 err = EINVAL; 330 goto out; 331 } 332 if (len == 1) 333 WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP); 334 else 335 WR4(sc, TWI_CR, TWI_CR_START); 336 if (msgs[i].flags & IIC_M_RD) { 337 sr = RD4(sc, TWI_SR); 338 while (!(sr & TWI_SR_TXCOMP)) { 339 if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) { 340 len--; 341 *buf++ = RD4(sc, TWI_RHR) & 0xff; 342 if (len == 0 && msgs[i].len != 1) 343 WR4(sc, TWI_CR, TWI_CR_STOP); 344 } 345 } 346 if (len > 0 || (sr & TWI_SR_NACK)) { 347 err = ENXIO; // iic nack convention 348 goto out; 349 } 350 } else { 351 while (len--) { 352 if (len == 0 && msgs[i].len != 1) 353 WR4(sc, TWI_CR, TWI_CR_STOP); 354 if ((err = at91_twi_wait(sc, TWI_SR_TXRDY))) 355 goto out; 356 WR4(sc, TWI_THR, *buf++); 357 } 358 } 359 if ((err = at91_twi_wait(sc, TWI_SR_TXCOMP))) 360 break; 361 } 362 out:; 363 if (err) { 364 WR4(sc, TWI_CR, TWI_CR_SWRST); 365 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 366 WR4(sc, TWI_CWGR, sc->cwgr); 367 } 368 AT91_TWI_UNLOCK(sc); 369 return (err); 370 } 371 372 static device_method_t at91_twi_methods[] = { 373 /* Device interface */ 374 DEVMETHOD(device_probe, at91_twi_probe), 375 DEVMETHOD(device_attach, at91_twi_attach), 376 DEVMETHOD(device_detach, at91_twi_detach), 377 378 /* iicbus interface */ 379 DEVMETHOD(iicbus_callback, at91_twi_callback), 380 DEVMETHOD(iicbus_reset, at91_twi_rst_card), 381 DEVMETHOD(iicbus_transfer, at91_twi_transfer), 382 { 0, 0 } 383 }; 384 385 static driver_t at91_twi_driver = { 386 "at91_twi", 387 at91_twi_methods, 388 sizeof(struct at91_twi_softc), 389 }; 390 391 DRIVER_MODULE(at91_twi, atmelarm, at91_twi_driver, at91_twi_devclass, 0, 0); 392 DRIVER_MODULE(iicbus, at91_twi, iicbus_driver, iicbus_devclass, 0, 0); 393 MODULE_DEPEND(at91_twi, iicbus, 1, 1, 1);
Cache object: ffc2ab9abc04f230e85a95e545b1eb3c
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