1 /*-
2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91_usartreg.h,v 1.3 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef AT91USARTREG_H_
29 #define AT91USARTREG_H_
30
31 #define USART_CR 0x00 /* Control register */
32 #define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */
33 #define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */
34 #define USART_CR_RXEN (1UL << 4) /* Receiver Enable */
35 #define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */
36 #define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */
37 #define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */
38 #define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */
39 #define USART_CR_STTBRK (1UL << 9) /* Start Break */
40 #define USART_CR_STPBRK (1UL << 10) /* Stop Break */
41 #define USART_CR_STTTO (1UL << 11) /* Start Time-out */
42 #define USART_CR_SENDA (1UL << 12) /* Send Address */
43 #define USART_CR_RSTIT (1UL << 13) /* Reset Iterations */
44 #define USART_CR_RSTNACK (1UL << 14) /* Reset Non Acknowledge */
45 #define USART_CR_RETTO (1UL << 15) /* Rearm Time-out */
46 #define USART_CR_DTREN (1UL << 16) /* Data Terminal ready Enable */
47 #define USART_CR_DTRDIS (1UL << 17) /* Data Terminal ready Disable */
48 #define USART_CR_RTSEN (1UL << 18) /* Request to Send enable */
49 #define USART_CR_RTSDIS (1UL << 19) /* Request to Send Disable */
50
51 #define USART_MR 0x04 /* Mode register */
52 #define USART_MR_MODE_NORMAL 0 /* Normal/Async/3-wire rs-232 */
53 #define USART_MR_MODE_RS485 1 /* RS485 */
54 #define USART_MR_MODE_HWFLOW 2 /* Hardware flow control/handshake */
55 #define USART_MR_MODE_MODEM 3 /* Full modem protocol */
56 #define USART_MR_MODE_ISO7816T0 4 /* ISO7816 T=0 */
57 #define USART_MR_MODE_ISO7816T1 6 /* ISO7816 T=1 */
58 #define USART_MR_MODE_IRDA 8 /* IrDA mode */
59 #define USART_MR_USCLKS_MCK (0U << 4) /* use MCK for baudclock */
60 #define USART_MR_USCLKS_MCKDIV (1U << 4) /* use MCK/DIV for baudclock */
61 #define USART_MR_USCLKS_SCK (3U << 4) /* use SCK (ext) for baudclock */
62 #define USART_MR_CHRL_5BITS (0U << 6)
63 #define USART_MR_CHRL_6BITS (1U << 6)
64 #define USART_MR_CHRL_7BITS (2U << 6)
65 #define USART_MR_CHRL_8BITS (3U << 6)
66 #define USART_MR_SYNC (1U << 8) /* 1 -> sync 0 -> async */
67 #define USART_MR_PAR_EVEN (0U << 9)
68 #define USART_MR_PAR_ODD (1U << 9)
69 #define USART_MR_PAR_SPACE (2U << 9)
70 #define USART_MR_PAR_MARK (3U << 9)
71 #define USART_MR_PAR_NONE (4U << 9)
72 #define USART_MR_PAR_MULTIDROP (6U << 9)
73 #define USART_MR_NBSTOP_1 (0U << 12)
74 #define USART_MR_NBSTOP_1_5 (1U << 12)
75 #define USART_MR_NBSTOP_2 (2U << 12)
76 #define USART_MR_CHMODE_NORMAL (0U << 14)
77 #define USART_MR_CHMODE_ECHO (1U << 14)
78 #define USART_MR_CHMODE_LOOP (2U << 14)
79 #define USART_MR_CHMODE_REMLOOP (3U << 14)
80 #define USART_MR_MSBF (1U << 16)
81 #define USART_MR_MODE9 (1U << 17)
82 #define USART_MR_CKLO_SCK (1U << 18)
83 #define USART_MR_OVER16 0
84 #define USART_MR_OVER8 (1U << 19)
85 #define USART_MR_INACK (1U << 20) /* Inhibit NACK generation */
86 #define USART_MR_DSNACK (1U << 21) /* Disable Successive NACK */
87 #define USART_MR_MAXITERATION(x) ((x) << 24)
88 #define USART_MR_FILTER (1U << 28) /* Filters for Ir lines */
89
90 #define USART_IER 0x08 /* Interrupt enable register */
91 #define USART_IDR 0x0c /* Interrupt disable register */
92 #define USART_IMR 0x10 /* Interrupt mask register */
93 #define USART_CSR 0x14 /* Channel status register */
94
95 #define USART_CSR_RXRDY (1UL << 0) /* Receiver ready */
96 #define USART_CSR_TXRDY (1UL << 1) /* Transmitter ready */
97 #define USART_CSR_RXBRK (1UL << 2) /* Break received */
98 #define USART_CSR_ENDRX (1UL << 3) /* End of Transfer RX from PDC */
99 #define USART_CSR_ENDTX (1UL << 4) /* End of Transfer TX from PDC */
100 #define USART_CSR_OVRE (1UL << 5) /* Overrun error */
101 #define USART_CSR_FRAME (1UL << 6) /* Framing error */
102 #define USART_CSR_PARE (1UL << 7) /* Parity Error */
103 #define USART_CSR_TIMEOUT (1UL << 8) /* Timeout since start-timeout */
104 #define USART_CSR_TXEMPTY (1UL << 9) /* Transmitter empty */
105 #define USART_CSR_ITERATION (1UL << 10) /* max repetitions since RSIT */
106 #define USART_CSR_TXBUFE (1UL << 11) /* Buffer empty from PDC */
107 #define USART_CSR_RXBUFF (1UL << 12) /* Buffer full from PDC */
108 #define USART_CSR_NACK (1UL << 13) /* NACK since last RSTNACK */
109 #define USART_CSR_RIIC (1UL << 16) /* RI delta since last csr read */
110 #define USART_CSR_DSRIC (1UL << 17) /* DSR delta */
111 #define USART_CSR_DCDIC (1UL << 18) /* DCD delta */
112 #define USART_CSR_CTSIC (1UL << 19) /* CTS delta */
113 #define USART_CSR_RI (1UL << 20) /* RI status */
114 #define USART_CSR_DSR (1UL << 21) /* DSR status */
115 #define USART_CSR_DCD (1UL << 22) /* DCD status */
116 #define USART_CSR_CTS (1UL << 23) /* CTS status */
117
118 #define USART_RHR 0x18 /* Receiver holding register */
119 #define USART_THR 0x1c /* Transmitter holding register */
120 #define USART_BRGR 0x20 /* Baud rate generator register */
121 #define USART_RTOR 0x24 /* Receiver time-out register */
122 #define USART_TTR 0x28 /* Transmitter timeguard register */
123 /* 0x2c to 0x3c reserved */
124 #define USART_FDRR 0x40 /* FI DI ratio register */
125 #define USART_NER 0x44 /* Number of errors register */
126 /* 0x48 reserved */
127 #define USART_IFR 0x48 /* IrDA filter register */
128
129 #endif /* AT91RM92REG_H_ */
130 Cache object: efbe5181a079d2be3e6a6c9f3f8fba8c
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