1 /*-
2 * Copyright (c) 2005 Gallon Sylvestre. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * $FreeBSD: releng/9.0/sys/arm/at91/at91_wdtreg.h 213496 2010-10-06 22:25:21Z cognet $
28 */
29
30 #ifndef ARM_AT91_AT91WDTREG_H
31 #define ARM_AT91_AT91WDTREG_H
32
33 #ifndef WDT_CLOCK
34 #define WDT_CLOCK (32768)
35 #endif
36 #define WDT_DIV (128) /* Clock is slow clock / 128 */
37
38 #define WDT_CR 0x0 /* Control Register */
39 #define WDT_MR 0x4 /* Mode Register */
40 #define WDT_SR 0x8 /* Status Register */
41
42 /* WDT_CR */
43 #define WDT_KEY (0xa5<<24)
44 #define WDT_WDRSTT 0x1
45
46 /* WDT_MR */
47 #define WDT_WDV(x) (x & 0xfff) /* counter value*/
48 #define WDT_WDFIEN (1<<12) /* enable interrupt */
49 #define WDT_WDRSTEN (1<<13) /* enable reset */
50 #define WDT_WDRPROC (1<<14) /* processor reset */
51 #define WDT_WDDIS (1<<15) /* disable */
52 #define WDT_WDD(x) ((x & 0xfff) << 16) /* delta value */
53 #define WDT_WDDBGHLT (1<<28) /* halt in debug */
54 #define WDT_WDIDLEHLT (1<<29) /* halt in idle */
55
56 /* WDT_SR */
57 #define WDT_WDUNF 0x1
58 #define WDT_WDERR 0x2
59
60 #endif /* ARM_AT91_AT91WDTREG_H */
Cache object: 38fbb7fc4167bfca75b29def84bb41a2
|