1 /*-
2 * Copyright (c) 2005 Olivier Houchard. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /* $FreeBSD: src/sys/arm/at91/at91rm92reg.h,v 1.7 2008/11/25 00:13:26 imp Exp $ */
27
28 #ifndef AT91RM92REG_H_
29 #define AT91RM92REG_H_
30 /*
31 * Memory map, from datasheet :
32 * 0x00000000 - 0x0ffffffff : Internal Memories
33 * 0x10000000 - 0x1ffffffff : Chip Select 0
34 * 0x20000000 - 0x2ffffffff : Chip Select 1
35 * 0x30000000 - 0x3ffffffff : Chip Select 2
36 * 0x40000000 - 0x4ffffffff : Chip Select 3
37 * 0x50000000 - 0x5ffffffff : Chip Select 4
38 * 0x60000000 - 0x6ffffffff : Chip Select 5
39 * 0x70000000 - 0x7ffffffff : Chip Select 6
40 * 0x80000000 - 0x8ffffffff : Chip Select 7
41 * 0x90000000 - 0xeffffffff : Undefined (Abort)
42 * 0xf0000000 - 0xfffffffff : Peripherals
43 */
44
45 #define AT91RM92_BASE 0xd0000000
46 /* Usart */
47
48 #define AT91RM92_USART0_BASE 0xffc0000
49 #define AT91RM92_USART0_PDC 0xffc0100
50 #define AT91RM92_USART1_BASE 0xffc4000
51 #define AT91RM92_USART1_PDC 0xffc4100
52 #define AT91RM92_USART2_BASE 0xffc8000
53 #define AT91RM92_USART2_PDC 0xffc8100
54 #define AT91RM92_USART3_BASE 0xffcc000
55 #define AT91RM92_USART3_PDC 0xffcc100
56 #define AT91RM92_USART_SIZE 0x4000
57
58 /* System Registers */
59
60 #define AT91RM92_SYS_BASE 0xffff000
61 #define AT91RM92_SYS_SIZE 0x1000
62 /* Interrupt Controller */
63 #define IC_SMR (0) /* Source mode register */
64 #define IC_SVR (128) /* Source vector register */
65 #define IC_IVR (256) /* IRQ vector register */
66 #define IC_FVR (260) /* FIQ vector register */
67 #define IC_ISR (264) /* Interrupt status register */
68 #define IC_IPR (268) /* Interrupt pending register */
69 #define IC_IMR (272) /* Interrupt status register */
70 #define IC_CISR (276) /* Core interrupt status register */
71 #define IC_IECR (288) /* Interrupt enable command register */
72 #define IC_IDCR (292) /* Interrupt disable command register */
73 #define IC_ICCR (296) /* Interrupt clear command register */
74 #define IC_ISCR (300) /* Interrupt set command register */
75 #define IC_EOICR (304) /* End of interrupt command register */
76 #define IC_SPU (308) /* Spurious vector register */
77 #define IC_DCR (312) /* Debug control register */
78 #define IC_FFER (320) /* Fast forcing enable register */
79 #define IC_FFDR (324) /* Fast forcing disable register */
80 #define IC_FFSR (328) /* Fast forcing status register */
81
82 /* DBGU */
83
84 #define DBGU 0x200
85 #define DBGU_SIZE 0x200
86 #define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */
87 #define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */
88 #define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */
89
90 #define PIOA_PER (0x400) /* PIO Enable Register */
91 #define PIOA_PDR (0x400 + 4) /* PIO Disable Register */
92 #define PIOA_PSR (0x400 + 8) /* PIO status register */
93 #define PIOA_OER (0x400 + 16) /* Output enable register */
94 #define PIOA_ODR (0x400 + 20) /* Output disable register */
95 #define PIOA_OSR (0x400 + 24) /* Output status register */
96 #define PIOA_IFER (0x400 + 32) /* Input filter enable register */
97 #define PIOA_IFDR (0x400 + 36) /* Input filter disable register */
98 #define PIOA_IFSR (0x400 + 40) /* Input filter status register */
99 #define PIOA_SODR (0x400 + 48) /* Set output data register */
100 #define PIOA_CODR (0x400 + 52) /* Clear output data register */
101 #define PIOA_ODSR (0x400 + 56) /* Output data status register */
102 #define PIOA_PDSR (0x400 + 60) /* Pin data status register */
103 #define PIOA_IER (0x400 + 64) /* Interrupt enable register */
104 #define PIOA_IDR (0x400 + 68) /* Interrupt disable register */
105 #define PIOA_IMR (0x400 + 72) /* Interrupt mask register */
106 #define PIOA_ISR (0x400 + 76) /* Interrupt status register */
107 #define PIOA_MDER (0x400 + 80) /* Multi driver enable register */
108 #define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */
109 #define PIOA_MDSR (0x400 + 88) /* Multi driver status register */
110 #define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */
111 #define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */
112 #define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */
113 #define PIOA_ASR (0x400 + 112) /* Select A register */
114 #define PIOA_BSR (0x400 + 116) /* Select B register */
115 #define PIOA_ABSR (0x400 + 120) /* AB Select status register */
116 #define PIOA_OWER (0x400 + 160) /* Output Write enable register */
117 #define PIOA_OWDR (0x400 + 164) /* Output write disable register */
118 #define PIOA_OWSR (0x400 + 168) /* Output write status register */
119 #define PIOB_PER (0x400) /* PIO Enable Register */
120 #define PIOB_PDR (0x600 + 4) /* PIO Disable Register */
121 #define PIOB_PSR (0x600 + 8) /* PIO status register */
122 #define PIOB_OER (0x600 + 16) /* Output enable register */
123 #define PIOB_ODR (0x600 + 20) /* Output disable register */
124 #define PIOB_OSR (0x600 + 24) /* Output status register */
125 #define PIOB_IFER (0x600 + 32) /* Input filter enable register */
126 #define PIOB_IFDR (0x600 + 36) /* Input filter disable register */
127 #define PIOB_IFSR (0x600 + 40) /* Input filter status register */
128 #define PIOB_SODR (0x600 + 48) /* Set output data register */
129 #define PIOB_CODR (0x600 + 52) /* Clear output data register */
130 #define PIOB_ODSR (0x600 + 56) /* Output data status register */
131 #define PIOB_PDSR (0x600 + 60) /* Pin data status register */
132 #define PIOB_IER (0x600 + 64) /* Interrupt enable register */
133 #define PIOB_IDR (0x600 + 68) /* Interrupt disable register */
134 #define PIOB_IMR (0x600 + 72) /* Interrupt mask register */
135 #define PIOB_ISR (0x600 + 76) /* Interrupt status register */
136 #define PIOB_MDER (0x600 + 80) /* Multi driver enable register */
137 #define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */
138 #define PIOB_MDSR (0x600 + 88) /* Multi driver status register */
139 #define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */
140 #define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */
141 #define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */
142 #define PIOB_ASR (0x600 + 112) /* Select A register */
143 #define PIOB_BSR (0x600 + 116) /* Select B register */
144 #define PIOB_ABSR (0x600 + 120) /* AB Select status register */
145 #define PIOB_OWER (0x600 + 160) /* Output Write enable register */
146 #define PIOB_OWDR (0x600 + 164) /* Output write disable register */
147 #define PIOB_OWSR (0x600 + 168) /* Output write status register */
148 #define PIOC_PER (0x800) /* PIO Enable Register */
149 #define PIOC_PDR (0x800 + 4) /* PIO Disable Register */
150 #define PIOC_PSR (0x800 + 8) /* PIO status register */
151 #define PIOC_OER (0x800 + 16) /* Output enable register */
152 #define PIOC_ODR (0x800 + 20) /* Output disable register */
153 #define PIOC_OSR (0x800 + 24) /* Output status register */
154 #define PIOC_IFER (0x800 + 32) /* Input filter enable register */
155 #define PIOC_IFDR (0x800 + 36) /* Input filter disable register */
156 #define PIOC_IFSR (0x800 + 40) /* Input filter status register */
157 #define PIOC_SODR (0x800 + 48) /* Set output data register */
158 #define PIOC_CODR (0x800 + 52) /* Clear output data register */
159 #define PIOC_ODSR (0x800 + 56) /* Output data status register */
160 #define PIOC_PDSR (0x800 + 60) /* Pin data status register */
161 #define PIOC_IER (0x800 + 64) /* Interrupt enable register */
162 #define PIOC_IDR (0x800 + 68) /* Interrupt disable register */
163 #define PIOC_IMR (0x800 + 72) /* Interrupt mask register */
164 #define PIOC_ISR (0x800 + 76) /* Interrupt status register */
165 #define PIOC_MDER (0x800 + 80) /* Multi driver enable register */
166 #define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */
167 #define PIOC_MDSR (0x800 + 88) /* Multi driver status register */
168 #define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */
169 #define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */
170 #define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */
171 #define PIOC_ASR (0x800 + 112) /* Select A register */
172 #define PIOC_BSR (0x800 + 116) /* Select B register */
173 #define PIOC_ABSR (0x800 + 120) /* AB Select status register */
174 #define PIOC_OWER (0x800 + 160) /* Output Write enable register */
175 #define PIOC_OWDR (0x800 + 164) /* Output write disable register */
176 #define PIOC_OWSR (0x800 + 168) /* Output write status register */
177 #define PIOD_PER (0xa00) /* PIO Enable Register */
178 #define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */
179 #define PIOD_PSR (0xa00 + 8) /* PIO status register */
180 #define PIOD_OER (0xa00 + 16) /* Output enable register */
181 #define PIOD_ODR (0xa00 + 20) /* Output disable register */
182 #define PIOD_OSR (0xa00 + 24) /* Output status register */
183 #define PIOD_IFER (0xa00 + 32) /* Input filter enable register */
184 #define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */
185 #define PIOD_IFSR (0xa00 + 40) /* Input filter status register */
186 #define PIOD_SODR (0xa00 + 48) /* Set output data register */
187 #define PIOD_CODR (0xa00 + 52) /* Clear output data register */
188 #define PIOD_ODSR (0xa00 + 56) /* Output data status register */
189 #define PIOD_PDSR (0xa00 + 60) /* Pin data status register */
190 #define PIOD_IER (0xa00 + 64) /* Interrupt enable register */
191 #define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */
192 #define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */
193 #define PIOD_ISR (0xa00 + 76) /* Interrupt status register */
194 #define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */
195 #define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */
196 #define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */
197 #define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */
198 #define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */
199 #define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */
200 #define PIOD_ASR (0xa00 + 112) /* Select A register */
201 #define PIOD_BSR (0xa00 + 116) /* Select B register */
202 #define PIOD_ABSR (0xa00 + 120) /* AB Select status register */
203 #define PIOD_OWER (0xa00 + 160) /* Output Write enable register */
204 #define PIOD_OWDR (0xa00 + 164) /* Output write disable register */
205 #define PIOD_OWSR (0xa00 + 168) /* Output write status register */
206
207 /*
208 * PIO
209 */
210 #define AT91RM92_PIOA_BASE 0xffff400
211 #define AT91RM92_PIO_SIZE 0x200
212 #define AT91RM92_PIOB_BASE 0xffff600
213 #define AT91RM92_PIOC_BASE 0xffff800
214 #define AT91RM92_PIOD_BASE 0xffffa00
215
216 /*
217 * PMC
218 */
219 #define AT91RM92_PMC_BASE 0xffffc00
220 #define AT91RM92_PMC_SIZE 0x100
221
222 /* IRQs : */
223 /*
224 * 0: AIC
225 * 1: System peripheral (System timer, RTC, DBGU)
226 * 2: PIO Controller A
227 * 3: PIO Controller B
228 * 4: PIO Controller C
229 * 5: PIO Controller D
230 * 6: USART 0
231 * 7: USART 1
232 * 8: USART 2
233 * 9: USART 3
234 * 10: MMC Interface
235 * 11: USB device port
236 * 12: Two-wirte interface
237 * 13: SPI
238 * 14: SSC
239 * 15: SSC
240 * 16: SSC
241 * 17: Timer Counter 0
242 * 18: Timer Counter 1
243 * 19: Timer Counter 2
244 * 20: Timer Counter 3
245 * 21: Timer Counter 4
246 * 22: Timer Counter 6
247 * 23: USB Host port
248 * 24: Ethernet
249 * 25: AIC
250 * 26: AIC
251 * 27: AIC
252 * 28: AIC
253 * 29: AIC
254 * 30: AIC
255 * 31: AIC
256 */
257
258 #define AT91RM92_IRQ_SYSTEM 1
259 #define AT91RM92_IRQ_PIOA 2
260 #define AT91RM92_IRQ_PIOB 3
261 #define AT91RM92_IRQ_PIOC 4
262 #define AT91RM92_IRQ_PIOD 5
263 #define AT91RM92_IRQ_USART0 6
264 #define AT91RM92_IRQ_USART1 7
265 #define AT91RM92_IRQ_USART2 8
266 #define AT91RM92_IRQ_USART3 9
267 #define AT91RM92_IRQ_MCI 10
268 #define AT91RM92_IRQ_UDP 11
269 #define AT91RM92_IRQ_TWI 12
270 #define AT91RM92_IRQ_SPI 13
271 #define AT91RM92_IRQ_SSC0 14
272 #define AT91RM92_IRQ_SSC1 15
273 #define AT91RM92_IRQ_SSC2 16
274 #define AT91RM92_IRQ_TC0 17
275 #define AT91RM92_IRQ_TC1 18
276 #define AT91RM92_IRQ_TC2 19
277 #define AT91RM92_IRQ_TC3 20
278 #define AT91RM92_IRQ_TC4 21
279 #define AT91RM92_IRQ_TC5 22
280 #define AT91RM92_IRQ_UHP 23
281 #define AT91RM92_IRQ_EMAC 24
282 #define AT91RM92_IRQ_AIC_BASE 25
283
284 /* Timer */
285
286 #define AT91RM92_AIC_BASE 0xffff000
287 #define AT91RM92_AIC_SIZE 0x200
288
289 #define AT91RM92_DBGU_BASE 0xffff200
290 #define AT91RM92_DBGU_SIZE 0x200
291
292 #define AT91RM92_RTC_BASE 0xffffe00
293 #define AT91RM92_RTC_SIZE 0x100
294
295 #define AT91RM92_MC_BASE 0xfffff00
296 #define AT91RM92_MC_SIZE 0x100
297
298 #define AT91RM92_ST_BASE 0xffffd00
299 #define AT91RM92_ST_SIZE 0x100
300
301 #define AT91RM92_SPI_BASE 0xffe0000
302 #define AT91RM92_SPI_SIZE 0x4000
303 #define AT91RM92_SPI_PDC 0xffe0100
304
305 #define AT91RM92_SSC0_BASE 0xffd0000
306 #define AT91RM92_SSC0_PDC 0xffd0100
307
308 #define AT91RM92_SSC1_BASE 0xffd4000
309 #define AT91RM92_SSC1_PDC 0xffd4100
310
311 #define AT91RM92_SSC2_BASE 0xffd8000
312 #define AT91RM92_SSC2_PDC 0xffd8100
313
314 #define AT91RM92_SSC_SIZE 0x4000
315
316 #define AT91RM92_EMAC_BASE 0xffbc000
317 #define AT91RM92_EMAC_SIZE 0x4000
318
319 #define AT91RM92_TWI_BASE 0xffb8000
320 #define AT91RM92_TWI_SIZE 0x4000
321
322 #define AT91RM92_MCI_BASE 0xffb4000
323 #define AT91RM92_MCI_PDC 0xffb4100
324 #define AT91RM92_MCI_SIZE 0x4000
325
326 #define AT91RM92_UDP_BASE 0xffb0000
327 #define AT91RM92_UDP_SIZE 0x4000
328
329 #define AT91RM92_TC0_BASE 0xffa0000
330 #define AT91RM92_TC_SIZE 0x4000
331 #define AT91RM92_TC0C0_BASE 0xffa0000
332 #define AT91RM92_TC0C1_BASE 0xffa0040
333 #define AT91RM92_TC0C2_BASE 0xffa0080
334
335 #define AT91RM92_TC1_BASE 0xffa4000
336 #define AT91RM92_TC1C0_BASE 0xffa4000
337 #define AT91RM92_TC1C1_BASE 0xffa4040
338 #define AT91RM92_TC1C2_BASE 0xffa4080
339
340 #define AT91RM92_OHCI_BASE 0xdfe00000
341 #define AT91RM92_OHCI_PA_BASE 0x00300000
342 #define AT91RM92_OHCI_SIZE 0x00100000
343
344 #ifndef AT91C_MASTER_CLOCK
345 #define AT91C_MASTER_CLOCK 60000000
346 #endif
347
348 /* SDRAMC */
349
350 #define AT91RM92_SDRAMC_BASE 0xfffff90
351 #define AT91RM92_SDRAMC_MR 0x00
352 #define AT91RM92_SDRAMC_MR_MODE_NORMAL 0
353 #define AT91RM92_SDRAMC_MR_MODE_NOP 1
354 #define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2
355 #define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3
356 #define AT91RM92_SDRAMC_MR_MODE_REFRESH 4
357 #define AT91RM92_SDRAMC_MR_DBW_16 0x10
358 #define AT91RM92_SDRAMC_TR 0x04
359 #define AT91RM92_SDRAMC_CR 0x08
360 #define AT91RM92_SDRAMC_CR_NC_8 0x0
361 #define AT91RM92_SDRAMC_CR_NC_9 0x1
362 #define AT91RM92_SDRAMC_CR_NC_10 0x2
363 #define AT91RM92_SDRAMC_CR_NC_11 0x3
364 #define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003
365 #define AT91RM92_SDRAMC_CR_NR_11 0x0
366 #define AT91RM92_SDRAMC_CR_NR_12 0x4
367 #define AT91RM92_SDRAMC_CR_NR_13 0x8
368 #define AT91RM92_SDRAMC_CR_NR_RES 0xc
369 #define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c
370 #define AT91RM92_SDRAMC_CR_NB_2 0x00
371 #define AT91RM92_SDRAMC_CR_NB_4 0x10
372 #define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010
373 #define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060
374 #define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780
375 #define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800
376 #define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000
377 #define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000
378 #define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000
379 #define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000
380 #define AT91RM92_SDRAMC_SRR 0x0c
381 #define AT91RM92_SDRAMC_LPR 0x10
382 #define AT91RM92_SDRAMC_IER 0x14
383 #define AT91RM92_SDRAMC_IDR 0x18
384 #define AT91RM92_SDRAMC_IMR 0x1c
385 #define AT91RM92_SDRAMC_ISR 0x20
386 #define AT91RM92_SDRAMC_IER_RES 0x1
387
388 #endif /* AT91RM92REG_H_ */
389 Cache object: 1b6e971a7abb1a418e9be91844baf8ea
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