Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91sam9260reg.h
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1 /*- 2 * Copyright (c) 2010 Greg Ansley. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* $FreeBSD: releng/9.0/sys/arm/at91/at91sam9260reg.h 213498 2010-10-06 22:40:27Z cognet $ */ 27 28 #ifndef AT91SAM9260REG_H_ 29 #define AT91SAM9260REG_H_ 30 31 #ifndef AT91SAM9260_MASTER_CLOCK 32 #define AT91SAM9260_MASTER_CLOCK ((18432000 * 43)/6) 33 #endif 34 35 /* Chip Specific limits */ 36 #define SAM9260_PLL_A_MIN_IN_FREQ 1000000 /* 1 Mhz */ 37 #define SAM9260_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 38 #define SAM9260_PLL_A_MIN_OUT_FREQ 80000000 /* 80 Mhz */ 39 #define SAM9260_PLL_A_MAX_OUT_FREQ 240000000 /* 240 Mhz */ 40 #define SAM9260_PLL_A_MUL_SHIFT 16 41 #define SAM9260_PLL_A_MUL_MASK 0x3FF 42 #define SAM9260_PLL_A_DIV_SHIFT 0 43 #define SAM9260_PLL_A_DIV_MASK 0xFF 44 45 #define SAM9260_PLL_B_MIN_IN_FREQ 1000000 /* 1 Mhz */ 46 #define SAM9260_PLL_B_MAX_IN_FREQ 5000000 /* 5 Mhz */ 47 #define SAM9260_PLL_B_MIN_OUT_FREQ 70000000 /* 70 Mhz */ 48 #define SAM9260_PLL_B_MAX_OUT_FREQ 130000000 /* 130 Mhz */ 49 #define SAM9260_PLL_B_MUL_SHIFT 16 50 #define SAM9260_PLL_B_MUL_MASK 0x3FF 51 #define SAM9260_PLL_B_DIV_SHIFT 0 52 #define SAM9260_PLL_B_DIV_MASK 0xFF 53 54 /* 55 * Memory map, from datasheet : 56 * 0x00000000 - 0x0ffffffff : Internal Memories 57 * 0x10000000 - 0x1ffffffff : Chip Select 0 58 * 0x20000000 - 0x2ffffffff : Chip Select 1 59 * 0x30000000 - 0x3ffffffff : Chip Select 2 60 * 0x40000000 - 0x4ffffffff : Chip Select 3 61 * 0x50000000 - 0x5ffffffff : Chip Select 4 62 * 0x60000000 - 0x6ffffffff : Chip Select 5 63 * 0x70000000 - 0x7ffffffff : Chip Select 6 64 * 0x80000000 - 0x8ffffffff : Chip Select 7 65 * 0x90000000 - 0xeffffffff : Undefined (Abort) 66 * 0xf0000000 - 0xfffffffff : Peripherals 67 */ 68 69 #define AT91_CHIPSELECT_0 0x10000000 70 #define AT91_CHIPSELECT_1 0x20000000 71 #define AT91_CHIPSELECT_2 0x30000000 72 #define AT91_CHIPSELECT_3 0x40000000 73 #define AT91_CHIPSELECT_4 0x50000000 74 #define AT91_CHIPSELECT_5 0x60000000 75 #define AT91_CHIPSELECT_6 0x70000000 76 #define AT91_CHIPSELECT_7 0x80000000 77 78 79 #define AT91SAM9260_BASE 0xd0000000 80 81 82 #define AT91SAM9260_EMAC_BASE 0xffc4000 83 #define AT91SAM9260_EMAC_SIZE 0x4000 84 85 #define AT91SAM9260_RSTC_BASE 0xffffd00 86 #define AT91SAM9260_RSTC_SIZE 0x10 87 88 #define RSTC_CR 0 89 #define RSTC_PROCRST (1 << 0) 90 #define RSTC_PERRST (1 << 2) 91 #define RSTC_KEY (0xa5 << 24) 92 93 /* USART*/ 94 95 #define AT91SAM9260_USART_SIZE 0x4000 96 #define AT91SAM9260_USART0_BASE 0xffb0000 97 #define AT91SAM9260_USART0_PDC 0xffb0100 98 #define AT91SAM9260_USART0_SIZE AT91SAM9260_USART_SIZE 99 #define AT91SAM9260_USART1_BASE 0xffb4000 100 #define AT91SAM9260_USART1_PDC 0xffb4100 101 #define AT91SAM9260_USART1_SIZE AT91SAM9260_USART_SIZE 102 #define AT91SAM9260_USART2_BASE 0xffb8000 103 #define AT91SAM9260_USART2_PDC 0xffb8100 104 #define AT91SAM9260_USART2_SIZE AT91SAM9260_USART_SIZE 105 #define AT91SAM9260_USART3_BASE 0xffd0000 106 #define AT91SAM9260_USART3_PDC 0xffd0100 107 #define AT91SAM9260_USART3_SIZE AT91SAM9260_USART_SIZE 108 #define AT91SAM9260_USART4_BASE 0xffd4000 109 #define AT91SAM9260_USART4_PDC 0xffd4100 110 #define AT91SAM9260_USART4_SIZE AT91SAM9260_USART_SIZE 111 #define AT91SAM9260_USART5_BASE 0xffd8000 112 #define AT91SAM9260_USART5_PDC 0xffd8100 113 #define AT91SAM9260_USART5_SIZE AT91SAM9260_USART_SIZE 114 115 /*TC*/ 116 #define AT91SAM9260_TC0_BASE 0xffa0000 117 #define AT91SAM9260_TC0_SIZE 0x4000 118 #define AT91SAM9260_TC0C0_BASE 0xffa0000 119 #define AT91SAM9260_TC0C1_BASE 0xffa0040 120 #define AT91SAM9260_TC0C2_BASE 0xffa0080 121 122 #define AT91SAM9260_TC1_BASE 0xffdc000 123 #define AT91SAM9260_TC1_SIZE 0x4000 124 125 /*SPI*/ 126 127 #define AT91SAM9260_SPI0_BASE 0xffc8000 128 129 #define AT91SAM9260_SPI0_SIZE 0x4000 130 #define AT91SAM9260_IRQ_SPI0 12 131 132 #define AT91SAM9260_SPI1_BASE 0xffcc000 133 #define AT91SAM9260_SPI1_SIZE 0x4000 134 #define AT91SAM9260_IRQ_SPI1 13 135 136 /* System Registers */ 137 #define AT91SAM9260_SYS_BASE 0xffff000 138 #define AT91SAM9260_SYS_SIZE 0x1000 139 140 #define AT91SAM9260_MATRIX_BASE 0xfffee00 141 #define AT91SAM9260_MATRIX_SIZE 0x1000 142 #define AT91SAM9260_EBICSA 0x011C 143 144 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 145 146 #define AT91SAM9260_DBGU_BASE 0xffff200 147 #define AT91SAM9260_DBGU_SIZE 0x200 148 149 /* 150 * PIO 151 */ 152 #define AT91SAM9260_PIOA_BASE 0xffff400 153 #define AT91SAM9260_PIOA_SIZE 0x200 154 #define AT91SAM9260_PIOB_BASE 0xffff600 155 #define AT91SAM9260_PIOB_SIZE 0x200 156 #define AT91SAM9260_PIOC_BASE 0xffff800 157 #define AT91SAM9260_PIOC_SIZE 0x200 158 159 #define AT91RM92_PMC_BASE 0xffffc00 160 #define AT91RM92_PMC_SIZE 0x100 161 /* IRQs : */ 162 /* 163 * 0: AIC 164 * 1: System peripheral (System timer, RTC, DBGU) 165 * 2: PIO Controller A 166 * 3: PIO Controller B 167 * 4: PIO Controller C 168 * 5: ADC 169 * 6: USART 0 170 * 7: USART 1 171 * 8: USART 2 172 * 9: MMC Interface 173 * 10: USB device port 174 * 11: Two-wirte interface 175 * 12: SPI 0 176 * 13: SPI 1 177 * 14: SSC 178 * 15: - (reserved) 179 * 16: - (reserved) 180 * 17: Timer Counter 0 181 * 18: Timer Counter 1 182 * 19: Timer Counter 2 183 * 20: USB Host port 184 * 21: EMAC 185 * 22: ISI 186 * 23: USART 3 187 * 24: USART 4 188 * 25: USART 2 189 * 26: Timer Counter 3 190 * 27: Timer Counter 4 191 * 28: Timer Counter 5 192 * 29: AIC IRQ0 193 * 30: AIC IRQ1 194 * 31: AIC IRQ2 195 */ 196 197 #define AT91SAM9260_IRQ_SYSTEM 1 198 #define AT91SAM9260_IRQ_PIOA 2 199 #define AT91SAM9260_IRQ_PIOB 3 200 #define AT91SAM9260_IRQ_PIOC 4 201 #define AT91SAM9260_IRQ_USART0 6 202 #define AT91SAM9260_IRQ_USART1 7 203 #define AT91SAM9260_IRQ_USART2 8 204 #define AT91SAM9260_IRQ_MCI 9 205 #define AT91SAM9260_IRQ_UDP 10 206 #define AT91SAM9260_IRQ_TWI 11 207 #define AT91SAM9260_IRQ_SPI0 12 208 #define AT91SAM9260_IRQ_SPI1 13 209 #define AT91SAM9260_IRQ_SSC0 14 210 #define AT91SAM9260_IRQ_SSC1 15 211 #define AT91SAM9260_IRQ_SSC2 16 212 #define AT91SAM9260_IRQ_TC0 17 213 #define AT91SAM9260_IRQ_TC1 18 214 #define AT91SAM9260_IRQ_TC2 19 215 #define AT91SAM9260_IRQ_UHP 20 216 #define AT91SAM9260_IRQ_EMAC 21 217 #define AT91SAM9260_IRQ_USART3 23 218 #define AT91SAM9260_IRQ_USART4 24 219 #define AT91SAM9260_IRQ_USART5 25 220 #define AT91SAM9260_IRQ_AICBASE 29 221 222 /* Alias */ 223 #define AT91SAM9260_IRQ_DBGU AT91SAM9260_IRQ_SYSTEM 224 #define AT91SAM9260_IRQ_PMC AT91SAM9260_IRQ_SYSTEM 225 #define AT91SAM9260_IRQ_WDT AT91SAM9260_IRQ_SYSTEM 226 #define AT91SAM9260_IRQ_PIT AT91SAM9260_IRQ_SYSTEM 227 #define AT91SAM9260_IRQ_RSTC AT91SAM9260_IRQ_SYSTEM 228 #define AT91SAM9260_IRQ_OHCI AT91SAM9260_IRQ_UHP 229 #define AT91SAM9260_IRQ_NAND (-1) 230 231 #define AT91SAM9260_AIC_BASE 0xffff000 232 #define AT91SAM9260_AIC_SIZE 0x200 233 234 /* Timer */ 235 236 #define AT91SAM9260_WDT_BASE 0xffffd40 237 #define AT91SAM9260_WDT_SIZE 0x10 238 239 #define AT91SAM9260_PIT_BASE 0xffffd30 240 #define AT91SAM9260_PIT_SIZE 10 241 242 #define AT91SAM9260_SMC_BASE 0xfffec00 243 #define AT91SAM9260_SMC_SIZE 0x200 244 245 #define AT91SAM9260_PMC_BASE 0xffffc00 246 #define AT91SAM9260_PMC_SIZE 0x100 247 248 #define AT91SAM9260_UDP_BASE 0xffa4000 249 #define AT91SAM9260_UDP_SIZE 0x4000 250 251 #define AT91SAM9260_MCI_BASE 0xffa8000 252 #define AT91SAM9260_MCI_SIZE 0x4000 253 254 #define AT91SAM9260_TWI_BASE 0xffaC000 255 #define AT91SAM9260_TWI_SIZE 0x4000 256 257 /* XXX Needs to be carfully coordinated with 258 * other * soc's so phyical and vm address 259 * mapping are unique. XXX 260 */ 261 #define AT91SAM9260_OHCI_BASE 0xdfc00000 262 #define AT91SAM9260_OHCI_PA_BASE 0x00500000 263 #define AT91SAM9260_OHCI_SIZE 0x00100000 264 265 #define AT91SAM9260_NAND_BASE 0xe0000000 266 #define AT91SAM9260_NAND_PA_BASE 0x40000000 267 #define AT91SAM9260_NAND_SIZE 0x10000000 268 269 270 /* SDRAMC */ 271 #define AT91SAM9260_SDRAMC_BASE 0xfffea00 272 #define AT91SAM9260_SDRAMC_MR 0x00 273 #define AT91SAM9260_SDRAMC_MR_MODE_NORMAL 0 274 #define AT91SAM9260_SDRAMC_MR_MODE_NOP 1 275 #define AT91SAM9260_SDRAMC_MR_MODE_PRECHARGE 2 276 #define AT91SAM9260_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 277 #define AT91SAM9260_SDRAMC_MR_MODE_REFRESH 4 278 #define AT91SAM9260_SDRAMC_TR 0x04 279 #define AT91SAM9260_SDRAMC_CR 0x08 280 #define AT91SAM9260_SDRAMC_CR_NC_8 0x0 281 #define AT91SAM9260_SDRAMC_CR_NC_9 0x1 282 #define AT91SAM9260_SDRAMC_CR_NC_10 0x2 283 #define AT91SAM9260_SDRAMC_CR_NC_11 0x3 284 #define AT91SAM9260_SDRAMC_CR_NC_MASK 0x00000003 285 #define AT91SAM9260_SDRAMC_CR_NR_11 0x0 286 #define AT91SAM9260_SDRAMC_CR_NR_12 0x4 287 #define AT91SAM9260_SDRAMC_CR_NR_13 0x8 288 #define AT91SAM9260_SDRAMC_CR_NR_RES 0xc 289 #define AT91SAM9260_SDRAMC_CR_NR_MASK 0x0000000c 290 #define AT91SAM9260_SDRAMC_CR_NB_2 0x00 291 #define AT91SAM9260_SDRAMC_CR_NB_4 0x10 292 #define AT91SAM9260_SDRAMC_CR_DBW_16 0x80 293 #define AT91SAM9260_SDRAMC_CR_NB_MASK 0x00000010 294 #define AT91SAM9260_SDRAMC_CR_NCAS_MASK 0x00000060 295 #define AT91SAM9260_SDRAMC_CR_TWR_MASK 0x00000780 296 #define AT91SAM9260_SDRAMC_CR_TRC_MASK 0x00007800 297 #define AT91SAM9260_SDRAMC_CR_TRP_MASK 0x00078000 298 #define AT91SAM9260_SDRAMC_CR_TRCD_MASK 0x00780000 299 #define AT91SAM9260_SDRAMC_CR_TRAS_MASK 0x07800000 300 #define AT91SAM9260_SDRAMC_CR_TXSR_MASK 0x78000000 301 #define AT91SAM9260_SDRAMC_HSR 0x0c 302 #define AT91SAM9260_SDRAMC_LPR 0x10 303 #define AT91SAM9260_SDRAMC_IER 0x14 304 #define AT91SAM9260_SDRAMC_IDR 0x18 305 #define AT91SAM9260_SDRAMC_IMR 0x1c 306 #define AT91SAM9260_SDRAMC_ISR 0x20 307 #define AT91SAM9260_SDRAMC_MDR 0x24 308 309 #endif /* AT91SAM9260REG_H_*/ 310
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