Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/at91sam9g45reg.h
Version:
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1 /*- 2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * Copyright (c) 2012 Andrew Turner. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* $FreeBSD$ */ 29 30 #ifndef AT91SAM9G45REG_H_ 31 #define AT91SAM9G45REG_H_ 32 33 /* Chip Specific limits */ 34 #define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ 35 #define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 36 #define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ 37 #define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ 38 #define SAM9G45_PLL_A_MUL_SHIFT 16 39 #define SAM9G45_PLL_A_MUL_MASK 0xFF 40 #define SAM9G45_PLL_A_DIV_SHIFT 0 41 #define SAM9G45_PLL_A_DIV_MASK 0xFF 42 43 /* 44 * Memory map, from datasheet : 45 * 0x00000000 - 0x0ffffffff : Internal Memories 46 * 0x10000000 - 0x1ffffffff : Chip Select 0 47 * 0x20000000 - 0x2ffffffff : Chip Select 1 48 * 0x30000000 - 0x3ffffffff : Chip Select 2 49 * 0x40000000 - 0x4ffffffff : Chip Select 3 50 * 0x50000000 - 0x5ffffffff : Chip Select 4 51 * 0x60000000 - 0x6ffffffff : Chip Select 5 52 * 0x70000000 - 0x7ffffffff : DDR SDRC 0 53 * 0x80000000 - 0xeffffffff : Undefined (Abort) 54 * 0xf0000000 - 0xfffffffff : Peripherals 55 */ 56 57 #define AT91_CHIPSELECT_0 0x10000000 58 #define AT91_CHIPSELECT_1 0x20000000 59 #define AT91_CHIPSELECT_2 0x30000000 60 #define AT91_CHIPSELECT_3 0x40000000 61 #define AT91_CHIPSELECT_4 0x50000000 62 #define AT91_CHIPSELECT_5 0x60000000 63 64 65 #define AT91SAM9G45_EMAC_BASE 0xffbc000 66 #define AT91SAM9G45_EMAC_SIZE 0x4000 67 68 #define AT91SAM9G45_RSTC_BASE 0xffffd00 69 #define AT91SAM9G45_RSTC_SIZE 0x10 70 71 /* USART*/ 72 73 #define AT91SAM9G45_USART_SIZE 0x4000 74 #define AT91SAM9G45_USART0_BASE 0xff8c000 75 #define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE 76 #define AT91SAM9G45_USART1_BASE 0xff90000 77 #define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE 78 #define AT91SAM9G45_USART2_BASE 0xff94000 79 #define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE 80 #define AT91SAM9G45_USART3_BASE 0xff98000 81 #define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE 82 83 /*TC*/ 84 #define AT91SAM9G45_TC0_BASE 0xff7c000 85 #define AT91SAM9G45_TC0_SIZE 0x4000 86 #define AT91SAM9G45_TC0C0_BASE 0xff7c000 87 #define AT91SAM9G45_TC0C1_BASE 0xff7c040 88 #define AT91SAM9G45_TC0C2_BASE 0xff7c080 89 90 #define AT91SAM9G45_TC1_BASE 0xffd4000 91 #define AT91SAM9G45_TC1_SIZE 0x4000 92 #define AT91SAM9G45_TC1C0_BASE 0xffd4000 93 #define AT91SAM9G45_TC1C1_BASE 0xffd4040 94 #define AT91SAM9G45_TC1C2_BASE 0xffd4080 95 96 /*SPI*/ 97 98 #define AT91SAM9G45_SPI0_BASE 0xffa48000 99 #define AT91SAM9G45_SPI0_SIZE 0x4000 100 101 #define AT91SAM9G45_SPI1_BASE 0xffa8000 102 #define AT91SAM9G45_SPI1_SIZE 0x4000 103 104 /* System Registers */ 105 #define AT91SAM9G45_SYS_BASE 0xffff000 106 #define AT91SAM9G45_SYS_SIZE 0x1000 107 108 #define AT91SAM9G45_MATRIX_BASE 0xfffea00 109 #define AT91SAM9G45_MATRIX_SIZE 0x200 110 111 #define AT91SAM9G45_DBGU_BASE 0xfffee00 112 #define AT91SAM9G45_DBGU_SIZE 0x200 113 114 /* 115 * PIO 116 */ 117 #define AT91SAM9G45_PIOA_BASE 0xffff200 118 #define AT91SAM9G45_PIOA_SIZE 0x200 119 #define AT91SAM9G45_PIOB_BASE 0xffff400 120 #define AT91SAM9G45_PIOB_SIZE 0x200 121 #define AT91SAM9G45_PIOC_BASE 0xffff600 122 #define AT91SAM9G45_PIOC_SIZE 0x200 123 #define AT91SAM9G45_PIOD_BASE 0xffff800 124 #define AT91SAM9G45_PIOD_SIZE 0x200 125 #define AT91SAM9G45_PIOE_BASE 0xffffa00 126 #define AT91SAM9G45_PIOE_SIZE 0x200 127 128 #define AT91SAM9G45_PMC_BASE 0xffffc00 129 #define AT91SAM9G45_PMC_SIZE 0x100 130 131 /* IRQs : */ 132 /* 133 * 0: AIC 134 * 1: System peripheral (System timer, RTC, DBGU) 135 * 2: PIO Controller A 136 * 3: PIO Controller B 137 * 4: PIO Controller C 138 * 5: PIO Controller D/E 139 * 6: TRNG 140 * 7: USART 0 141 * 8: USART 1 142 * 9: USART 2 143 * 10: USART 3 144 * 11: Multimedia Card interface 0 145 * 12: Two-wirte interface 0 146 * 13: Two-wirte interface 1 147 * 14: SPI 0 148 * 15: SPI 1 149 * 16: SSC 0 150 * 17: SSC 0 151 * 18: Timer Counter 0, 2, 3, 4, 5 152 * 19: PWM 153 * 20: Touch Screen ADC 154 * 21: DMA 155 * 22: USB Host port 156 * 23: LCD 157 * 24: AC97 158 * 25: EMAC 159 * 26: Image Sensor Interface 160 * 27: USB Device High Speed 161 * 28: - 162 * 29: Multimedia Card interface 1 163 * 30: Reserved 164 * 31: AIC 165 */ 166 167 #define AT91SAM9G45_IRQ_SYSTEM 1 168 #define AT91SAM9G45_IRQ_PIOA 2 169 #define AT91SAM9G45_IRQ_PIOB 3 170 #define AT91SAM9G45_IRQ_PIOC 4 171 #define AT91SAM9G45_IRQ_PIOD 5 172 #define AT91SAM9G45_IRQ_PIOE 6 173 #define AT91SAM9G45_IRQ_USART0 7 174 #define AT91SAM9G45_IRQ_USART1 8 175 #define AT91SAM9G45_IRQ_USART2 9 176 #define AT91SAM9G45_IRQ_USART3 10 177 #define AT91SAM9G45_IRQ_HSMCI0 11 178 #define AT91SAM9G45_IRQ_TWI0 12 179 #define AT91SAM9G45_IRQ_TWI1 13 180 #define AT91SAM9G45_IRQ_SPI0 14 181 #define AT91SAM9G45_IRQ_SPI1 15 182 #define AT91SAM9G45_IRQ_SSC0 16 183 #define AT91SAM9G45_IRQ_SSC1 17 184 #define AT91SAM9G45_IRQ_TC0_TC5 18 185 #define AT91SAM9G45_IRQ_PWM 19 186 #define AT91SAM9G45_IRQ_TSADCC 20 187 #define AT91SAM9G45_IRQ_DMA 21 188 #define AT91SAM9G45_IRQ_UHP 22 189 #define AT91SAM9G45_IRQ_LCDC 23 190 #define AT91SAM9G45_IRQ_AC97C 24 191 #define AT91SAM9G45_IRQ_EMAC 25 192 #define AT91SAM9G45_IRQ_ISI 26 193 #define AT91SAM9G45_IRQ_UDPHS 27 194 /* Reserved 28 */ 195 #define AT91SAM9G45_IRQ_HSMCI1 29 196 /* Reserved 30 */ 197 #define AT91SAM9G45_IRQ_AICBASE 31 198 199 /* Alias */ 200 #define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM 201 #define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM 202 #define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM 203 #define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM 204 #define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM 205 #define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP 206 #define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5 207 #define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5 208 #define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5 209 #define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5 210 #define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5 211 #define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5 212 #define AT91SAM9G45_IRQ_NAND (-1) 213 214 #define AT91SAM9G45_AIC_BASE 0xffff000 215 #define AT91SAM9G45_AIC_SIZE 0x200 216 217 /* Timer */ 218 219 #define AT91SAM9G45_WDT_BASE 0xffffd40 220 #define AT91SAM9G45_WDT_SIZE 0x10 221 222 #define AT91SAM9G45_PIT_BASE 0xffffd30 223 #define AT91SAM9G45_PIT_SIZE 0x10 224 225 #define AT91SAM9G45_SMC_BASE 0xfffe800 226 #define AT91SAM9G45_SMC_SIZE 0x200 227 228 #define AT91SAM9G45_PMC_BASE 0xffffc00 229 #define AT91SAM9G45_PMC_SIZE 0x100 230 231 #define AT91SAM9G45_HSMCI0_BASE 0xff80000 232 #define AT91SAM9G45_HSMCI0_SIZE 0x4000 233 234 #define AT91SAM9G45_HSMCI1_BASE 0xffd0000 235 #define AT91SAM9G45_HSMCI1_SIZE 0x4000 236 237 #define AT91SAM9G45_TWI0_BASE 0xff84000 238 #define AT91SAM9G45_TWI0_SIZE 0x4000 239 #define AT91SAM9G45_TWI1_BASE 0xff88000 240 #define AT91SAM9G45_TWI1_SIZE 0x4000 241 242 /* XXX Needs to be carfully coordinated with 243 * other * soc's so phyical and vm address 244 * mapping are unique. XXX 245 */ 246 #define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000 247 #define AT91SAM9G45_OHCI_BASE 0x00700000 248 #define AT91SAM9G45_OHCI_SIZE 0x00100000 249 250 #define AT91SAM9G45_NAND_VA_BASE 0xe0000000 251 #define AT91SAM9G45_NAND_BASE 0x40000000 252 #define AT91SAM9G45_NAND_SIZE 0x10000000 253 254 255 /* DDRSDRC */ 256 #define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00 257 #define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600 258 #define AT91SAM9G45_DDRSDRC_MR 0x00 259 #define AT91SAM9G45_DDRSDRC_TR 0x04 260 #define AT91SAM9G45_DDRSDRC_CR 0x08 261 #define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0 262 #define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1 263 #define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2 264 #define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3 265 #define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003 266 #define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0 267 #define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4 268 #define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8 269 #define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc 270 #define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c 271 #define AT91SAM9G45_DDRSDRC_TPR0 0x0c 272 #define AT91SAM9G45_DDRSDRC_TPR1 0x10 273 #define AT91SAM9G45_DDRSDRC_TPR2 0x14 274 /* Reserved 0x18 */ 275 #define AT91SAM9G45_DDRSDRC_LPR 0x1c 276 #define AT91SAM9G45_DDRSDRC_MDR 0x20 277 #define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0 278 #define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1 279 #define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3 280 #define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6 281 #define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007 282 #define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10 283 #define AT91SAM9G45_DDRSDRC_DLL 0x24 284 #define AT91SAM9G45_DDRSDRC_HSR 0x2c 285 #define AT91SAM9G45_DDRSDRC_DELAY1R 0x40 286 #define AT91SAM9G45_DDRSDRC_DELAY2R 0x44 287 #define AT91SAM9G45_DDRSDRC_DELAY3R 0x48 288 #define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c 289 /* Reserved 0x50 - 0xe0 */ 290 #define AT91SAM9G45_DDRSDRC_WPMR 0xe4 291 #define AT91SAM9G45_DDRSDRC_WPSR 0xe8 292 293 #endif /* AT91SAM9G45REG_H_*/ 294
Cache object: 08243b24c9445ca87d7a22a25d498ac8
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