Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/at91/if_ate.c
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1 /*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2009 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* TODO 28 * 29 * 1) Turn on the clock in pmc? Turn off? 30 * 2) GPIO initializtion in board setup code. 31 */ 32 33 #include "opt_platform.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/malloc.h> 43 #include <sys/mbuf.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 50 #include <machine/bus.h> 51 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_arp.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_mib.h> 58 #include <net/if_types.h> 59 #include <net/if_var.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/ip.h> 66 #endif 67 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include "opt_at91.h" 75 #include <arm/at91/at91reg.h> 76 #include <arm/at91/at91var.h> 77 #include <arm/at91/if_atereg.h> 78 79 #ifdef FDT 80 #include <dev/fdt/fdt_common.h> 81 #include <dev/ofw/ofw_bus.h> 82 #include <dev/ofw/ofw_bus_subr.h> 83 #endif 84 85 #include "miibus_if.h" 86 87 /* 88 * Driver-specific flags. 89 */ 90 #define ATE_FLAG_DETACHING 0x01 91 #define ATE_FLAG_MULTICAST 0x02 92 93 /* 94 * Old EMAC assumes whole packet fits in one buffer; 95 * new EBACB assumes all receive buffers are 128 bytes 96 */ 97 #define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES) 98 99 /* 100 * EMACB has an 11 bit counter for Rx/Tx Descriptors 101 * for max total of 1024 decriptors each. 102 */ 103 #define ATE_MAX_RX_DESCR 1024 104 #define ATE_MAX_TX_DESCR 1024 105 106 /* How many buffers to allocate */ 107 #define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */ 108 109 /* How much memory to use for rx buffers */ 110 #define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128) 111 112 /* Actual number of descriptors we allocate */ 113 #define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR 114 #define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS 115 116 #if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR 117 #error "Can't have more TX buffers that descriptors" 118 #endif 119 #if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR 120 #error "Can't have more RX buffers that descriptors" 121 #endif 122 123 /* Wrap indexes the same way the hardware does */ 124 #define NEXT_RX_IDX(sc, cur) \ 125 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1)) 126 127 #define NEXT_TX_IDX(sc, cur) \ 128 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1)) 129 130 struct ate_softc 131 { 132 struct ifnet *ifp; /* ifnet pointer */ 133 struct mtx sc_mtx; /* Basically a perimeter lock */ 134 device_t dev; /* Myself */ 135 device_t miibus; /* My child miibus */ 136 struct resource *irq_res; /* IRQ resource */ 137 struct resource *mem_res; /* Memory resource */ 138 struct callout tick_ch; /* Tick callout */ 139 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 140 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 141 bus_dma_tag_t rx_tag; 142 bus_dma_tag_t rx_desc_tag; 143 bus_dmamap_t rx_desc_map; 144 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR]; 145 bus_addr_t rx_desc_phys; /* PA of rx descriptors */ 146 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */ 147 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */ 148 int rxhead; /* Current RX map/desc index */ 149 uint32_t rx_buf_size; /* Size of Rx buffers */ 150 151 bus_dma_tag_t tx_desc_tag; 152 bus_dmamap_t tx_desc_map; 153 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 154 bus_addr_t tx_desc_phys; /* PA of tx descriptors */ 155 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */ 156 int txhead; /* Current TX map/desc index */ 157 int txtail; /* Current TX map/desc index */ 158 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 159 void *intrhand; /* Interrupt handle */ 160 int flags; 161 int if_flags; 162 int use_rmii; 163 int is_emacb; /* SAM9x hardware version */ 164 }; 165 166 static inline uint32_t 167 RD4(struct ate_softc *sc, bus_size_t off) 168 { 169 170 return (bus_read_4(sc->mem_res, off)); 171 } 172 173 static inline void 174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 175 { 176 177 bus_write_4(sc->mem_res, off, val); 178 } 179 180 static inline void 181 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 182 { 183 184 bus_barrier(sc->mem_res, off, len, flags); 185 } 186 187 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 188 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 189 #define ATE_LOCK_INIT(_sc) \ 190 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 191 MTX_NETWORK_LOCK, MTX_DEF) 192 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 193 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 194 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 195 196 static devclass_t ate_devclass; 197 198 /* 199 * ifnet entry points. 200 */ 201 static void ateinit_locked(void *); 202 static void atestart_locked(struct ifnet *); 203 204 static void ateinit(void *); 205 static void atestart(struct ifnet *); 206 static void atestop(struct ate_softc *); 207 static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 208 209 /* 210 * Bus entry points. 211 */ 212 static int ate_probe(device_t dev); 213 static int ate_attach(device_t dev); 214 static int ate_detach(device_t dev); 215 static void ate_intr(void *); 216 217 /* 218 * Helper routines. 219 */ 220 static int ate_activate(device_t dev); 221 static void ate_deactivate(struct ate_softc *sc); 222 static int ate_ifmedia_upd(struct ifnet *ifp); 223 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 224 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 225 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 226 static void ate_rxfilter(struct ate_softc *sc); 227 228 static int ate_miibus_readreg(device_t dev, int phy, int reg); 229 230 static int ate_miibus_writereg(device_t dev, int phy, int reg, int data); 231 /* 232 * The AT91 family of products has the ethernet interface called EMAC. 233 * However, it isn't self identifying. It is anticipated that the parent bus 234 * code will take care to only add ate devices where they really are. As 235 * such, we do nothing here to identify the device and just set its name. 236 */ 237 static int 238 ate_probe(device_t dev) 239 { 240 #ifdef FDT 241 if (!ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb")) 242 return (ENXIO); 243 #endif 244 device_set_desc(dev, "EMAC"); 245 return (0); 246 } 247 248 static int 249 ate_attach(device_t dev) 250 { 251 struct ate_softc *sc; 252 struct ifnet *ifp = NULL; 253 struct sysctl_ctx_list *sctx; 254 struct sysctl_oid *soid; 255 u_char eaddr[ETHER_ADDR_LEN]; 256 uint32_t rnd; 257 int rid, err; 258 259 sc = device_get_softc(dev); 260 sc->dev = dev; 261 ATE_LOCK_INIT(sc); 262 263 rid = 0; 264 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 265 RF_ACTIVE); 266 if (sc->mem_res == NULL) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 err = ENOMEM; 269 goto out; 270 } 271 rid = 0; 272 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 273 RF_ACTIVE); 274 if (sc->irq_res == NULL) { 275 device_printf(dev, "could not allocate interrupt resources.\n"); 276 err = ENOMEM; 277 goto out; 278 } 279 280 /* New or old version, chooses buffer size. */ 281 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe(); 282 sc->rx_buf_size = RX_BUF_SIZE(sc); 283 284 err = ate_activate(dev); 285 if (err) 286 goto out; 287 288 /* Default to what boot rom did */ 289 if (!sc->is_emacb) 290 sc->use_rmii = 291 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 292 else 293 sc->use_rmii = 294 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 295 296 #ifdef AT91_ATE_USE_RMII 297 /* Compile time override */ 298 sc->use_rmii = 1; 299 #endif 300 /* Sysctls */ 301 sctx = device_get_sysctl_ctx(dev); 302 soid = device_get_sysctl_tree(dev); 303 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 304 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use"); 305 306 /* Calling atestop before ifp is set is OK. */ 307 ATE_LOCK(sc); 308 atestop(sc); 309 ATE_UNLOCK(sc); 310 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 311 312 if ((err = ate_get_mac(sc, eaddr)) != 0) { 313 /* No MAC address configured. Generate the random one. */ 314 if (bootverbose) 315 device_printf(dev, 316 "Generating random ethernet address.\n"); 317 rnd = arc4random(); 318 319 /* 320 * Set OUI to convenient locally assigned address. 'b' 321 * is 0x62, which has the locally assigned bit set, and 322 * the broadcast/multicast bit clear. 323 */ 324 eaddr[0] = 'b'; 325 eaddr[1] = 's'; 326 eaddr[2] = 'd'; 327 eaddr[3] = (rnd >> 16) & 0xff; 328 eaddr[4] = (rnd >> 8) & 0xff; 329 eaddr[5] = (rnd >> 0) & 0xff; 330 } 331 332 sc->ifp = ifp = if_alloc(IFT_ETHER); 333 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 334 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 335 if (err != 0) { 336 device_printf(dev, "attaching PHYs failed\n"); 337 goto out; 338 } 339 /* 340 * XXX: Clear the isolate bit, or we won't get up, 341 * at least on the HL201 342 */ 343 ate_miibus_writereg(dev, 0, 0, 0x3000); 344 345 ifp->if_softc = sc; 346 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 348 ifp->if_capabilities |= IFCAP_VLAN_MTU; 349 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 350 ifp->if_start = atestart; 351 ifp->if_ioctl = ateioctl; 352 ifp->if_init = ateinit; 353 ifp->if_baudrate = 10000000; 354 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 355 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 356 IFQ_SET_READY(&ifp->if_snd); 357 ifp->if_linkmib = &sc->mibdata; 358 ifp->if_linkmiblen = sizeof(sc->mibdata); 359 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 360 sc->if_flags = ifp->if_flags; 361 362 ether_ifattach(ifp, eaddr); 363 364 /* Activate the interrupt. */ 365 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 366 NULL, ate_intr, sc, &sc->intrhand); 367 if (err) { 368 device_printf(dev, "could not establish interrupt handler.\n"); 369 ether_ifdetach(ifp); 370 goto out; 371 } 372 373 out: 374 if (err) 375 ate_detach(dev); 376 return (err); 377 } 378 379 static int 380 ate_detach(device_t dev) 381 { 382 struct ate_softc *sc; 383 struct ifnet *ifp; 384 385 sc = device_get_softc(dev); 386 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 387 ifp = sc->ifp; 388 if (device_is_attached(dev)) { 389 ATE_LOCK(sc); 390 sc->flags |= ATE_FLAG_DETACHING; 391 atestop(sc); 392 ATE_UNLOCK(sc); 393 callout_drain(&sc->tick_ch); 394 ether_ifdetach(ifp); 395 } 396 if (sc->miibus != NULL) { 397 device_delete_child(dev, sc->miibus); 398 sc->miibus = NULL; 399 } 400 bus_generic_detach(sc->dev); 401 ate_deactivate(sc); 402 if (sc->intrhand != NULL) { 403 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 404 sc->intrhand = NULL; 405 } 406 if (ifp != NULL) { 407 if_free(ifp); 408 sc->ifp = NULL; 409 } 410 if (sc->mem_res != NULL) { 411 bus_release_resource(dev, SYS_RES_IOPORT, 412 rman_get_rid(sc->mem_res), sc->mem_res); 413 sc->mem_res = NULL; 414 } 415 if (sc->irq_res != NULL) { 416 bus_release_resource(dev, SYS_RES_IRQ, 417 rman_get_rid(sc->irq_res), sc->irq_res); 418 sc->irq_res = NULL; 419 } 420 ATE_LOCK_DESTROY(sc); 421 return (0); 422 } 423 424 static void 425 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 426 { 427 428 if (error != 0) 429 return; 430 *(bus_addr_t *)arg = segs[0].ds_addr; 431 } 432 433 static void 434 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 435 { 436 struct ate_softc *sc; 437 438 if (error != 0) 439 return; 440 sc = (struct ate_softc *)arg; 441 442 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 443 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr; 444 sc->rx_descs[sc->rxhead].status = 0; 445 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 446 } 447 448 static uint32_t 449 ate_mac_hash(const uint8_t *buf) 450 { 451 uint32_t index = 0; 452 for (int i = 0; i < 48; i++) { 453 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 454 } 455 return (index); 456 } 457 458 /* 459 * Compute the multicast filter for this device. 460 */ 461 static int 462 ate_setmcast(struct ate_softc *sc) 463 { 464 uint32_t index; 465 uint32_t mcaf[2]; 466 u_char *af = (u_char *) mcaf; 467 struct ifmultiaddr *ifma; 468 struct ifnet *ifp; 469 470 ifp = sc->ifp; 471 472 if ((ifp->if_flags & IFF_PROMISC) != 0) 473 return (0); 474 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 475 WR4(sc, ETH_HSL, 0xffffffff); 476 WR4(sc, ETH_HSH, 0xffffffff); 477 return (1); 478 } 479 480 /* Compute the multicast hash. */ 481 mcaf[0] = 0; 482 mcaf[1] = 0; 483 if_maddr_rlock(ifp); 484 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 485 if (ifma->ifma_addr->sa_family != AF_LINK) 486 continue; 487 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 488 ifma->ifma_addr)); 489 af[index >> 3] |= 1 << (index & 7); 490 } 491 if_maddr_runlock(ifp); 492 493 /* 494 * Write the hash to the hash register. This card can also 495 * accept unicast packets as well as multicast packets using this 496 * register for easier bridging operations, but we don't take 497 * advantage of that. Locks here are to avoid LOR with the 498 * if_maddr_rlock, but might not be strictly necessary. 499 */ 500 WR4(sc, ETH_HSL, mcaf[0]); 501 WR4(sc, ETH_HSH, mcaf[1]); 502 return (mcaf[0] || mcaf[1]); 503 } 504 505 static int 506 ate_activate(device_t dev) 507 { 508 struct ate_softc *sc; 509 int i; 510 511 sc = device_get_softc(dev); 512 513 /* Allocate DMA tags and maps for TX mbufs */ 514 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 516 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag)) 517 goto errout; 518 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 519 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i])) 520 goto errout; 521 } 522 523 524 /* DMA tag and map for the RX descriptors. */ 525 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 526 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 527 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1, 528 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 529 &sc->sc_mtx, &sc->rx_desc_tag)) 530 goto errout; 531 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 532 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 533 goto errout; 534 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 535 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 536 ate_getaddr, &sc->rx_desc_phys, 0) != 0) 537 goto errout; 538 539 /* Allocate DMA tags and maps for RX. buffers */ 540 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 541 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 542 sc->rx_buf_size, 1, sc->rx_buf_size, 0, 543 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag)) 544 goto errout; 545 546 /* 547 * Allocate our RX buffers. 548 * This chip has a RX structure that's filled in. 549 * XXX On MACB (SAM9 part) we should receive directly into mbuf 550 * to avoid the copy. XXX 551 */ 552 sc->rxhead = 0; 553 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size; 554 sc->rxhead++) { 555 if (bus_dmamem_alloc(sc->rx_tag, 556 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT, 557 &sc->rx_map[sc->rxhead]) != 0) 558 goto errout; 559 560 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead], 561 sc->rx_buf[sc->rxhead], sc->rx_buf_size, 562 ate_load_rx_buf, sc, 0) != 0) { 563 printf("bus_dmamem_load\n"); 564 goto errout; 565 } 566 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD); 567 } 568 569 /* 570 * For the last buffer, set the wrap bit so the controller 571 * restarts from the first descriptor. 572 */ 573 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT; 574 sc->rxhead = 0; 575 576 /* Flush the memory for the EMAC rx descriptor. */ 577 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 578 579 /* Write the descriptor queue address. */ 580 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 581 582 /* 583 * DMA tag and map for the TX descriptors. 584 */ 585 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 586 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 587 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1, 588 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex, 589 &sc->sc_mtx, &sc->tx_desc_tag) != 0) 590 goto errout; 591 592 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs, 593 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0) 594 goto errout; 595 596 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map, 597 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 598 ate_getaddr, &sc->tx_desc_phys, 0) != 0) 599 goto errout; 600 601 /* Initilize descriptors; mark all empty */ 602 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 603 sc->tx_descs[i].addr =0; 604 sc->tx_descs[i].status = ETHB_TX_USED; 605 sc->sent_mbuf[i] = NULL; 606 } 607 608 /* Mark last entry to cause wrap when indexing through */ 609 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status = 610 ETHB_TX_WRAP | ETHB_TX_USED; 611 612 /* Flush the memory for the EMAC tx descriptor. */ 613 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 614 615 sc->txhead = sc->txtail = 0; 616 if (sc->is_emacb) { 617 /* Write the descriptor queue address. */ 618 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 619 620 /* EMACB: Enable transceiver input clock */ 621 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 622 } 623 624 return (0); 625 626 errout: 627 return (ENOMEM); 628 } 629 630 static void 631 ate_deactivate(struct ate_softc *sc) 632 { 633 int i; 634 635 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 636 if (sc->mtag != NULL) { 637 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 638 if (sc->sent_mbuf[i] != NULL) { 639 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 640 BUS_DMASYNC_POSTWRITE); 641 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 642 m_freem(sc->sent_mbuf[i]); 643 } 644 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 645 sc->sent_mbuf[i] = NULL; 646 sc->tx_map[i] = NULL; 647 } 648 bus_dma_tag_destroy(sc->mtag); 649 } 650 if (sc->rx_desc_tag != NULL) { 651 if (sc->rx_descs != NULL) { 652 if (sc->rx_desc_phys != 0) { 653 bus_dmamap_sync(sc->rx_desc_tag, 654 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 655 bus_dmamap_unload(sc->rx_desc_tag, 656 sc->rx_desc_map); 657 sc->rx_desc_phys = 0; 658 } 659 } 660 } 661 if (sc->rx_tag != NULL) { 662 for (i = 0; sc->rx_buf[i] != NULL; i++) { 663 if (sc->rx_descs[i].addr != 0) { 664 bus_dmamap_sync(sc->rx_tag, 665 sc->rx_map[i], 666 BUS_DMASYNC_POSTREAD); 667 bus_dmamap_unload(sc->rx_tag, 668 sc->rx_map[i]); 669 sc->rx_descs[i].addr = 0; 670 } 671 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i], 672 sc->rx_map[i]); 673 sc->rx_buf[i] = NULL; 674 sc->rx_map[i] = NULL; 675 } 676 bus_dma_tag_destroy(sc->rx_tag); 677 } 678 if (sc->rx_desc_tag != NULL) { 679 if (sc->rx_descs != NULL) 680 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 681 sc->rx_desc_map); 682 bus_dma_tag_destroy(sc->rx_desc_tag); 683 sc->rx_descs = NULL; 684 sc->rx_desc_tag = NULL; 685 } 686 687 if (sc->is_emacb) 688 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 689 } 690 691 /* 692 * Change media according to request. 693 */ 694 static int 695 ate_ifmedia_upd(struct ifnet *ifp) 696 { 697 struct ate_softc *sc = ifp->if_softc; 698 struct mii_data *mii; 699 700 mii = device_get_softc(sc->miibus); 701 ATE_LOCK(sc); 702 mii_mediachg(mii); 703 ATE_UNLOCK(sc); 704 return (0); 705 } 706 707 /* 708 * Notify the world which media we're using. 709 */ 710 static void 711 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 712 { 713 struct ate_softc *sc = ifp->if_softc; 714 struct mii_data *mii; 715 716 mii = device_get_softc(sc->miibus); 717 ATE_LOCK(sc); 718 mii_pollstat(mii); 719 ifmr->ifm_active = mii->mii_media_active; 720 ifmr->ifm_status = mii->mii_media_status; 721 ATE_UNLOCK(sc); 722 } 723 724 static void 725 ate_stat_update(struct ate_softc *sc, int active) 726 { 727 uint32_t reg; 728 729 /* 730 * The speed and full/half-duplex state needs to be reflected 731 * in the ETH_CFG register. 732 */ 733 reg = RD4(sc, ETH_CFG); 734 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 735 if (IFM_SUBTYPE(active) != IFM_10_T) 736 reg |= ETH_CFG_SPD; 737 if (active & IFM_FDX) 738 reg |= ETH_CFG_FD; 739 WR4(sc, ETH_CFG, reg); 740 } 741 742 static void 743 ate_tick(void *xsc) 744 { 745 struct ate_softc *sc = xsc; 746 struct ifnet *ifp = sc->ifp; 747 struct mii_data *mii; 748 int active; 749 uint32_t c; 750 751 /* 752 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 753 * the MII if there's a link if this bit is clear. Not sure if we 754 * should do the same thing here or not. 755 */ 756 ATE_ASSERT_LOCKED(sc); 757 if (sc->miibus != NULL) { 758 mii = device_get_softc(sc->miibus); 759 active = mii->mii_media_active; 760 mii_tick(mii); 761 if (mii->mii_media_status & IFM_ACTIVE && 762 active != mii->mii_media_active) 763 ate_stat_update(sc, mii->mii_media_active); 764 } 765 766 /* 767 * Update the stats as best we can. When we're done, clear 768 * the status counters and start over. We're supposed to read these 769 * registers often enough that they won't overflow. Hopefully 770 * once a second is often enough. Some don't map well to 771 * the dot3Stats mib, so for those we just count them as general 772 * errors. Stats for iframes, ibutes, oframes and obytes are 773 * collected elsewhere. These registers zero on a read to prevent 774 * races. For all the collision stats, also update the collision 775 * stats for the interface. 776 */ 777 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 778 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 779 c = RD4(sc, ETH_SCOL); 780 ifp->if_collisions += c; 781 sc->mibdata.dot3StatsSingleCollisionFrames += c; 782 c = RD4(sc, ETH_MCOL); 783 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 784 ifp->if_collisions += c; 785 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 786 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 787 c = RD4(sc, ETH_LCOL); 788 sc->mibdata.dot3StatsLateCollisions += c; 789 ifp->if_collisions += c; 790 c = RD4(sc, ETH_ECOL); 791 sc->mibdata.dot3StatsExcessiveCollisions += c; 792 ifp->if_collisions += c; 793 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 794 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 795 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 796 797 /* 798 * Not sure where to lump these, so count them against the errors 799 * for the interface. 800 */ 801 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 802 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 803 RD4(sc, ETH_USF); 804 805 /* Schedule another timeout one second from now. */ 806 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 807 } 808 809 static void 810 ate_set_mac(struct ate_softc *sc, u_char *eaddr) 811 { 812 813 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 814 (eaddr[1] << 8) | eaddr[0]); 815 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 816 } 817 818 static int 819 ate_get_mac(struct ate_softc *sc, u_char *eaddr) 820 { 821 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 822 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 823 uint32_t low, high; 824 int i; 825 826 /* 827 * The boot loader may setup the MAC with an address(es), grab the 828 * first MAC address from the SA[1-4][HL] registers. 829 */ 830 for (i = 0; i < 4; i++) { 831 low = RD4(sc, sa_low_reg[i]); 832 high = RD4(sc, sa_high_reg[i]); 833 if ((low | (high & 0xffff)) != 0) { 834 eaddr[0] = low & 0xff; 835 eaddr[1] = (low >> 8) & 0xff; 836 eaddr[2] = (low >> 16) & 0xff; 837 eaddr[3] = (low >> 24) & 0xff; 838 eaddr[4] = high & 0xff; 839 eaddr[5] = (high >> 8) & 0xff; 840 return (0); 841 } 842 } 843 return (ENXIO); 844 } 845 846 static void 847 ate_intr(void *xsc) 848 { 849 struct ate_softc *sc = xsc; 850 struct ifnet *ifp = sc->ifp; 851 struct mbuf *mb; 852 eth_rx_desc_t *rxdhead; 853 uint32_t status, reg, idx; 854 int remain, count, done; 855 856 status = RD4(sc, ETH_ISR); 857 if (status == 0) 858 return; 859 860 if (status & ETH_ISR_RCOM) { 861 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 862 BUS_DMASYNC_POSTREAD); 863 864 rxdhead = &sc->rx_descs[sc->rxhead]; 865 while (rxdhead->addr & ETH_CPU_OWNER) { 866 if (!sc->is_emacb) { 867 /* 868 * Simulate SAM9 FIRST/LAST bits for RM9200. 869 * RM9200 EMAC has only on Rx buffer per packet. 870 * But sometime we are handed a zero lenght packet. 871 */ 872 if ((rxdhead->status & ETH_LEN_MASK) == 0) 873 rxdhead->status = 0; /* Mark error */ 874 else 875 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST; 876 } 877 878 if ((rxdhead->status & ETH_BUF_FIRST) == 0) { 879 /* Something went wrong during RX so 880 release back to EMAC all buffers of invalid packets. 881 */ 882 rxdhead->status = 0; 883 rxdhead->addr &= ~ETH_CPU_OWNER; 884 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 885 rxdhead = &sc->rx_descs[sc->rxhead]; 886 continue; 887 } 888 889 /* Find end of packet or start of next */ 890 idx = sc->rxhead; 891 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 892 idx = NEXT_RX_IDX(sc, idx); 893 894 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) && 895 ((sc->rx_descs[idx].status & 896 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 897 idx = NEXT_RX_IDX(sc, idx); 898 } 899 900 /* Packet NOT yet completely in memory; we are done */ 901 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 || 902 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 903 break; 904 905 /* Packets with no end descriptor are invalid. */ 906 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 907 rxdhead->status &= ~ETH_BUF_FIRST; 908 continue; 909 } 910 911 /* FCS is not coppied into mbuf. */ 912 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4; 913 914 /* Get an appropriately sized mbuf. */ 915 mb = m_get2(remain + ETHER_ALIGN, M_NOWAIT, MT_DATA, 916 M_PKTHDR); 917 if (mb == NULL) { 918 sc->ifp->if_iqdrops++; 919 rxdhead->status = 0; 920 continue; 921 } 922 mb->m_data += ETHER_ALIGN; 923 mb->m_pkthdr.rcvif = ifp; 924 925 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */ 926 927 /* Now we process the buffers that make up the packet */ 928 do { 929 930 /* Last buffer may just be 1-4 bytes of FCS so remain 931 * may be zero for last decriptor. */ 932 if (remain > 0) { 933 /* Make sure we get the current bytes */ 934 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], 935 BUS_DMASYNC_POSTREAD); 936 937 count = MIN(remain, sc->rx_buf_size); 938 939 /* XXX Performance robbing copy. Could 940 * recieve directly to mbufs if not an 941 * RM9200. And even then we could likely 942 * copy just the protocol headers. XXX */ 943 m_append(mb, count, sc->rx_buf[sc->rxhead]); 944 remain -= count; 945 } 946 947 done = (rxdhead->status & ETH_BUF_LAST) != 0; 948 949 /* Return the descriptor to the EMAC */ 950 rxdhead->status = 0; 951 rxdhead->addr &= ~ETH_CPU_OWNER; 952 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 953 BUS_DMASYNC_PREWRITE); 954 955 /* Move on to next descriptor with wrap */ 956 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 957 rxdhead = &sc->rx_descs[sc->rxhead]; 958 959 } while (!done); 960 961 ifp->if_ipackets++; 962 (*ifp->if_input)(ifp, mb); 963 } 964 } 965 966 967 if (status & ETH_ISR_TCOM) { 968 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 969 BUS_DMASYNC_POSTREAD); 970 971 ATE_LOCK(sc); 972 /* XXX TSR register should be cleared */ 973 if (!sc->is_emacb) { 974 /* Simulate Transmit descriptor table */ 975 976 /* First packet done */ 977 if (sc->txtail < sc->txhead) 978 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED; 979 980 /* Second Packet done */ 981 if (sc->txtail + 1 < sc->txhead && 982 RD4(sc, ETH_TSR) & ETH_TSR_IDLE) 983 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED; 984 } 985 986 while ((sc->tx_descs[sc->txtail].status & ETHB_TX_USED) && 987 sc->sent_mbuf[sc->txtail] != NULL) { 988 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 989 BUS_DMASYNC_POSTWRITE); 990 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 991 m_freem(sc->sent_mbuf[sc->txtail]); 992 sc->tx_descs[sc->txtail].addr = 0; 993 sc->sent_mbuf[sc->txtail] = NULL; 994 ifp->if_opackets++; 995 sc->txtail = NEXT_TX_IDX(sc, sc->txtail); 996 } 997 998 /* Flush descriptors to EMAC */ 999 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 1000 1001 /* 1002 * We're no longer busy, so clear the busy flag and call the 1003 * start routine to xmit more packets. 1004 */ 1005 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1006 atestart_locked(sc->ifp); 1007 ATE_UNLOCK(sc); 1008 } 1009 1010 if (status & ETH_ISR_RBNA) { 1011 /* Workaround RM9200 Errata #11 */ 1012 if (bootverbose) 1013 device_printf(sc->dev, "RBNA workaround\n"); 1014 reg = RD4(sc, ETH_CTL); 1015 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 1016 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 1017 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 1018 } 1019 1020 /* XXX need to work around SAM9260 errata 43.2.4.1: 1021 * disable the mac, reset tx buffer, enable mac on TUND */ 1022 } 1023 1024 /* 1025 * Reset and initialize the chip. 1026 */ 1027 static void 1028 ateinit_locked(void *xsc) 1029 { 1030 struct ate_softc *sc = xsc; 1031 struct ifnet *ifp = sc->ifp; 1032 struct mii_data *mii; 1033 uint8_t eaddr[ETHER_ADDR_LEN]; 1034 uint32_t reg; 1035 1036 ATE_ASSERT_LOCKED(sc); 1037 1038 /* 1039 * XXX TODO(3) 1040 * we need to turn on the EMAC clock in the pmc. With the 1041 * default boot loader, this is already turned on. However, we 1042 * need to think about how best to turn it on/off as the interface 1043 * is brought up/down, as well as dealing with the mii bus... 1044 * 1045 * We also need to multiplex the pins correctly (in board_xxx.c). 1046 */ 1047 1048 /* 1049 * There are two different ways that the mii bus is connected 1050 * to this chip mii or rmii. 1051 */ 1052 if (!sc->is_emacb) { 1053 /* RM9200 */ 1054 reg = RD4(sc, ETH_CFG); 1055 if (sc->use_rmii) 1056 reg |= ETH_CFG_RMII; 1057 else 1058 reg &= ~ETH_CFG_RMII; 1059 WR4(sc, ETH_CFG, reg); 1060 } else { 1061 /* SAM9 */ 1062 reg = ETHB_UIO_CLKE; 1063 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0; 1064 WR4(sc, ETHB_UIO, reg); 1065 } 1066 1067 ate_rxfilter(sc); 1068 1069 /* 1070 * Set the chip MAC address. 1071 */ 1072 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1073 ate_set_mac(sc, eaddr); 1074 1075 /* Make sure we know state of TX queue */ 1076 sc->txhead = sc->txtail = 0; 1077 if (sc->is_emacb) { 1078 /* Write the descriptor queue address. */ 1079 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 1080 } 1081 1082 /* 1083 * Turn on MACs and interrupt processing. 1084 */ 1085 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 1086 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 1087 1088 /* Enable big packets. */ 1089 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1090 1091 /* 1092 * Set 'running' flag, and clear output active flag 1093 * and attempt to start the output. 1094 */ 1095 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1096 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1097 1098 mii = device_get_softc(sc->miibus); 1099 mii_pollstat(mii); 1100 ate_stat_update(sc, mii->mii_media_active); 1101 atestart_locked(ifp); 1102 1103 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 1104 } 1105 1106 /* 1107 * Dequeue packets and transmit. 1108 */ 1109 static void 1110 atestart_locked(struct ifnet *ifp) 1111 { 1112 struct ate_softc *sc = ifp->if_softc; 1113 struct mbuf *m, *mdefrag; 1114 bus_dma_segment_t segs[1]; 1115 int nseg, e; 1116 1117 ATE_ASSERT_LOCKED(sc); 1118 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1119 return; 1120 1121 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) { 1122 /* 1123 * Check to see if there's room to put another packet into the 1124 * xmit queue. The old EMAC version has a ping-pong buffer for 1125 * xmit packets. We use OACTIVE to indicate "we can stuff more 1126 * into our buffers (clear) or not (set)." 1127 */ 1128 /* RM9200 has only two hardware entries */ 1129 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) { 1130 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1131 return; 1132 } 1133 1134 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1135 if (m == 0) 1136 break; 1137 1138 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m, 1139 segs, &nseg, 0); 1140 if (e == EFBIG) { 1141 mdefrag = m_defrag(m, M_NOWAIT); 1142 if (mdefrag == NULL) { 1143 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1144 return; 1145 } 1146 m = mdefrag; 1147 e = bus_dmamap_load_mbuf_sg(sc->mtag, 1148 sc->tx_map[sc->txhead], m, segs, &nseg, 0); 1149 } 1150 if (e != 0) { 1151 m_freem(m); 1152 continue; 1153 } 1154 1155 /* 1156 * There's a small race between the loop in ate_intr finishing 1157 * and the check above to see if the packet was finished, as well 1158 * as when atestart gets called via other paths. Lose the race 1159 * gracefully and free the mbuf... 1160 */ 1161 if (sc->sent_mbuf[sc->txhead] != NULL) { 1162 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 1163 BUS_DMASYNC_POSTWRITE); 1164 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 1165 m_free(sc->sent_mbuf[sc->txhead]); 1166 ifp->if_opackets++; 1167 } 1168 1169 sc->sent_mbuf[sc->txhead] = m; 1170 1171 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead], 1172 BUS_DMASYNC_PREWRITE); 1173 1174 /* Tell the hardware to xmit the packet. */ 1175 if (!sc->is_emacb) { 1176 WR4(sc, ETH_TAR, segs[0].ds_addr); 1177 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE); 1178 WR4(sc, ETH_TCR, segs[0].ds_len); 1179 } else { 1180 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1181 BUS_DMASYNC_POSTWRITE); 1182 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr; 1183 sc->tx_descs[sc->txhead].status = segs[0].ds_len | 1184 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) | 1185 ETHB_TX_BUF_LAST; 1186 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1187 BUS_DMASYNC_PREWRITE); 1188 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO); 1189 } 1190 sc->txhead = NEXT_TX_IDX(sc, sc->txhead); 1191 1192 /* Tap off here if there is a bpf listener. */ 1193 BPF_MTAP(ifp, m); 1194 } 1195 1196 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0) 1197 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1198 } 1199 1200 static void 1201 ateinit(void *xsc) 1202 { 1203 struct ate_softc *sc = xsc; 1204 1205 ATE_LOCK(sc); 1206 ateinit_locked(sc); 1207 ATE_UNLOCK(sc); 1208 } 1209 1210 static void 1211 atestart(struct ifnet *ifp) 1212 { 1213 struct ate_softc *sc = ifp->if_softc; 1214 1215 ATE_LOCK(sc); 1216 atestart_locked(ifp); 1217 ATE_UNLOCK(sc); 1218 } 1219 1220 /* 1221 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1222 * so be careful. 1223 */ 1224 static void 1225 atestop(struct ate_softc *sc) 1226 { 1227 struct ifnet *ifp; 1228 int i; 1229 1230 ATE_ASSERT_LOCKED(sc); 1231 ifp = sc->ifp; 1232 if (ifp) { 1233 //ifp->if_timer = 0; 1234 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1235 } 1236 1237 callout_stop(&sc->tick_ch); 1238 1239 /* 1240 * Enable some parts of the MAC that are needed always (like the 1241 * MII bus. This turns off the RE and TE bits, which will remain 1242 * off until ateinit() is called to turn them on. With RE and TE 1243 * turned off, there's no DMA to worry about after this write. 1244 */ 1245 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1246 1247 /* 1248 * Turn off all the configured options and revert to defaults. 1249 */ 1250 1251 /* Make sure thate the MDIO clk is less than 1252 * 2.5 Mhz. Can no longer default to /32 since 1253 * SAM9 family may have MCK > 80 Mhz */ 1254 if (at91_master_clock <= 2000000) 1255 WR4(sc, ETH_CFG, ETH_CFG_CLK_8); 1256 else if (at91_master_clock <= 4000000) 1257 WR4(sc, ETH_CFG, ETH_CFG_CLK_16); 1258 else if (at91_master_clock <= 800000) 1259 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1260 else 1261 WR4(sc, ETH_CFG, ETH_CFG_CLK_64); 1262 1263 /* 1264 * Turn off all the interrupts, and ack any pending ones by reading 1265 * the ISR. 1266 */ 1267 WR4(sc, ETH_IDR, 0xffffffff); 1268 RD4(sc, ETH_ISR); 1269 1270 /* 1271 * Clear out the Transmit and Receiver Status registers of any 1272 * errors they may be reporting 1273 */ 1274 WR4(sc, ETH_TSR, 0xffffffff); 1275 WR4(sc, ETH_RSR, 0xffffffff); 1276 1277 /* Release TX resources. */ 1278 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1279 if (sc->sent_mbuf[i] != NULL) { 1280 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1281 BUS_DMASYNC_POSTWRITE); 1282 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1283 m_freem(sc->sent_mbuf[i]); 1284 sc->sent_mbuf[i] = NULL; 1285 } 1286 } 1287 1288 /* Turn off transeiver input clock */ 1289 if (sc->is_emacb) 1290 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 1291 1292 /* 1293 * XXX we should power down the EMAC if it isn't in use, after 1294 * putting it into loopback mode. This saves about 400uA according 1295 * to the datasheet. 1296 */ 1297 } 1298 1299 static void 1300 ate_rxfilter(struct ate_softc *sc) 1301 { 1302 struct ifnet *ifp; 1303 uint32_t reg; 1304 int enabled; 1305 1306 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1307 ATE_ASSERT_LOCKED(sc); 1308 ifp = sc->ifp; 1309 1310 /* Wipe out old filter settings. */ 1311 reg = RD4(sc, ETH_CFG); 1312 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1313 reg |= ETH_CFG_NBC; 1314 sc->flags &= ~ATE_FLAG_MULTICAST; 1315 1316 /* Set new parameters. */ 1317 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1318 reg &= ~ETH_CFG_NBC; 1319 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1320 reg |= ETH_CFG_CAF; 1321 } else { 1322 enabled = ate_setmcast(sc); 1323 if (enabled != 0) { 1324 reg |= ETH_CFG_MTI; 1325 sc->flags |= ATE_FLAG_MULTICAST; 1326 } 1327 } 1328 WR4(sc, ETH_CFG, reg); 1329 } 1330 1331 static int 1332 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1333 { 1334 struct ate_softc *sc = ifp->if_softc; 1335 struct mii_data *mii; 1336 struct ifreq *ifr = (struct ifreq *)data; 1337 int drv_flags, flags; 1338 int mask, error, enabled; 1339 1340 error = 0; 1341 flags = ifp->if_flags; 1342 drv_flags = ifp->if_drv_flags; 1343 switch (cmd) { 1344 case SIOCSIFFLAGS: 1345 ATE_LOCK(sc); 1346 if ((flags & IFF_UP) != 0) { 1347 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1348 if (((flags ^ sc->if_flags) 1349 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1350 ate_rxfilter(sc); 1351 } else { 1352 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1353 ateinit_locked(sc); 1354 } 1355 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1356 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1357 atestop(sc); 1358 } 1359 sc->if_flags = flags; 1360 ATE_UNLOCK(sc); 1361 break; 1362 1363 case SIOCADDMULTI: 1364 case SIOCDELMULTI: 1365 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1366 ATE_LOCK(sc); 1367 enabled = ate_setmcast(sc); 1368 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1369 ate_rxfilter(sc); 1370 ATE_UNLOCK(sc); 1371 } 1372 break; 1373 1374 case SIOCSIFMEDIA: 1375 case SIOCGIFMEDIA: 1376 mii = device_get_softc(sc->miibus); 1377 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1378 break; 1379 case SIOCSIFCAP: 1380 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1381 if (mask & IFCAP_VLAN_MTU) { 1382 ATE_LOCK(sc); 1383 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1384 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1385 ifp->if_capenable |= IFCAP_VLAN_MTU; 1386 } else { 1387 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1388 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1389 } 1390 ATE_UNLOCK(sc); 1391 } 1392 default: 1393 error = ether_ioctl(ifp, cmd, data); 1394 break; 1395 } 1396 return (error); 1397 } 1398 1399 static void 1400 ate_child_detached(device_t dev, device_t child) 1401 { 1402 struct ate_softc *sc; 1403 1404 sc = device_get_softc(dev); 1405 if (child == sc->miibus) 1406 sc->miibus = NULL; 1407 } 1408 1409 /* 1410 * MII bus support routines. 1411 */ 1412 static int 1413 ate_miibus_readreg(device_t dev, int phy, int reg) 1414 { 1415 struct ate_softc *sc; 1416 int val; 1417 1418 /* 1419 * XXX if we implement agressive power savings, then we need 1420 * XXX to make sure that the clock to the emac is on here 1421 */ 1422 1423 sc = device_get_softc(dev); 1424 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1425 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1426 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1427 continue; 1428 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1429 1430 return (val); 1431 } 1432 1433 static int 1434 ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1435 { 1436 struct ate_softc *sc; 1437 1438 /* 1439 * XXX if we implement agressive power savings, then we need 1440 * XXX to make sure that the clock to the emac is on here 1441 */ 1442 1443 sc = device_get_softc(dev); 1444 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1445 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1446 continue; 1447 return (0); 1448 } 1449 1450 static device_method_t ate_methods[] = { 1451 /* Device interface */ 1452 DEVMETHOD(device_probe, ate_probe), 1453 DEVMETHOD(device_attach, ate_attach), 1454 DEVMETHOD(device_detach, ate_detach), 1455 1456 /* Bus interface */ 1457 DEVMETHOD(bus_child_detached, ate_child_detached), 1458 1459 /* MII interface */ 1460 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1461 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1462 1463 DEVMETHOD_END 1464 }; 1465 1466 static driver_t ate_driver = { 1467 "ate", 1468 ate_methods, 1469 sizeof(struct ate_softc), 1470 }; 1471 1472 #ifdef FDT 1473 DRIVER_MODULE(ate, simplebus, ate_driver, ate_devclass, NULL, NULL); 1474 #else 1475 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL); 1476 #endif 1477 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL); 1478 MODULE_DEPEND(ate, miibus, 1, 1, 1); 1479 MODULE_DEPEND(ate, ether, 1, 1, 1);
Cache object: caa45c79028436d822e69e4bc2c2aa99
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