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sys/arm/at91/if_ate.c
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1 /*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD: releng/8.1/sys/arm/at91/if_ate.c 205124 2010-03-13 16:37:17Z ticso $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <machine/bus.h> 47 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_mib.h> 54 #include <net/if_types.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/bpf.h> 64 #include <net/bpfdesc.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <arm/at91/if_atereg.h> 69 70 #include "miibus_if.h" 71 72 #define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73 #define ATE_MAX_RX_BUFFERS 64 74 75 /* 76 * Driver-specific flags. 77 */ 78 #define ATE_FLAG_DETACHING 0x01 79 #define ATE_FLAG_MULTICAST 0x02 80 81 struct ate_softc 82 { 83 struct ifnet *ifp; /* ifnet pointer */ 84 struct mtx sc_mtx; /* Basically a perimeter lock */ 85 device_t dev; /* Myself */ 86 device_t miibus; /* My child miibus */ 87 struct resource *irq_res; /* IRQ resource */ 88 struct resource *mem_res; /* Memory resource */ 89 struct callout tick_ch; /* Tick callout */ 90 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 91 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 92 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 93 bus_dma_tag_t rxtag; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 97 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 101 void *intrhand; /* Interrupt handle */ 102 int flags; 103 int if_flags; 104 int rx_buf_ptr; 105 int txcur; /* Current TX map pointer */ 106 int use_rmii; 107 }; 108 109 static inline uint32_t 110 RD4(struct ate_softc *sc, bus_size_t off) 111 { 112 113 return (bus_read_4(sc->mem_res, off)); 114 } 115 116 static inline void 117 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 118 { 119 120 bus_write_4(sc->mem_res, off, val); 121 } 122 123 static inline void 124 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 125 { 126 127 bus_barrier(sc->mem_res, off, len, flags); 128 } 129 130 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 131 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 132 #define ATE_LOCK_INIT(_sc) \ 133 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 134 MTX_NETWORK_LOCK, MTX_DEF) 135 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 136 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 137 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 138 139 static devclass_t ate_devclass; 140 141 /* 142 * ifnet entry points. 143 */ 144 static void ateinit_locked(void *); 145 static void atestart_locked(struct ifnet *); 146 147 static void ateinit(void *); 148 static void atestart(struct ifnet *); 149 static void atestop(struct ate_softc *); 150 static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 151 152 /* 153 * Bus entry points. 154 */ 155 static int ate_probe(device_t dev); 156 static int ate_attach(device_t dev); 157 static int ate_detach(device_t dev); 158 static void ate_intr(void *); 159 160 /* 161 * Helper routines. 162 */ 163 static int ate_activate(device_t dev); 164 static void ate_deactivate(struct ate_softc *sc); 165 static int ate_ifmedia_upd(struct ifnet *ifp); 166 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 167 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 168 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 169 static void ate_rxfilter(struct ate_softc *sc); 170 171 /* 172 * The AT91 family of products has the ethernet called EMAC. However, 173 * it isn't self identifying. It is anticipated that the parent bus 174 * code will take care to only add ate devices where they really are. As 175 * such, we do nothing here to identify the device and just set its name. 176 */ 177 static int 178 ate_probe(device_t dev) 179 { 180 181 device_set_desc(dev, "EMAC"); 182 return (0); 183 } 184 185 static int 186 ate_attach(device_t dev) 187 { 188 struct ate_softc *sc; 189 struct ifnet *ifp = NULL; 190 struct sysctl_ctx_list *sctx; 191 struct sysctl_oid *soid; 192 u_char eaddr[ETHER_ADDR_LEN]; 193 uint32_t rnd; 194 int rid, err; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 ATE_LOCK_INIT(sc); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 237 238 if ((err = ate_get_mac(sc, eaddr)) != 0) { 239 /* 240 * No MAC address configured. Generate the random one. 241 */ 242 if (bootverbose) 243 device_printf(dev, 244 "Generating random ethernet address.\n"); 245 rnd = arc4random(); 246 247 /* 248 * Set OUI to convenient locally assigned address. 'b' 249 * is 0x62, which has the locally assigned bit set, and 250 * the broadcast/multicast bit clear. 251 */ 252 eaddr[0] = 'b'; 253 eaddr[1] = 's'; 254 eaddr[2] = 'd'; 255 eaddr[3] = (rnd >> 16) & 0xff; 256 eaddr[4] = (rnd >> 8) & 0xff; 257 eaddr[5] = rnd & 0xff; 258 } 259 260 sc->ifp = ifp = if_alloc(IFT_ETHER); 261 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 262 device_printf(dev, "Cannot find my PHY.\n"); 263 err = ENXIO; 264 goto out; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_capabilities |= IFCAP_VLAN_MTU; 271 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 272 ifp->if_start = atestart; 273 ifp->if_ioctl = ateioctl; 274 ifp->if_init = ateinit; 275 ifp->if_baudrate = 10000000; 276 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 277 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 278 IFQ_SET_READY(&ifp->if_snd); 279 ifp->if_timer = 0; 280 ifp->if_linkmib = &sc->mibdata; 281 ifp->if_linkmiblen = sizeof(sc->mibdata); 282 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 283 sc->if_flags = ifp->if_flags; 284 285 ether_ifattach(ifp, eaddr); 286 287 /* 288 * Activate the interrupt. 289 */ 290 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 291 NULL, ate_intr, sc, &sc->intrhand); 292 if (err) { 293 device_printf(dev, "could not establish interrupt handler.\n"); 294 ether_ifdetach(ifp); 295 goto out; 296 } 297 298 out: 299 if (err) 300 ate_detach(dev); 301 return (err); 302 } 303 304 static int 305 ate_detach(device_t dev) 306 { 307 struct ate_softc *sc; 308 struct ifnet *ifp; 309 310 sc = device_get_softc(dev); 311 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 312 ifp = sc->ifp; 313 if (device_is_attached(dev)) { 314 ATE_LOCK(sc); 315 sc->flags |= ATE_FLAG_DETACHING; 316 atestop(sc); 317 ATE_UNLOCK(sc); 318 callout_drain(&sc->tick_ch); 319 ether_ifdetach(ifp); 320 } 321 if (sc->miibus != NULL) { 322 device_delete_child(dev, sc->miibus); 323 sc->miibus = NULL; 324 } 325 bus_generic_detach(sc->dev); 326 ate_deactivate(sc); 327 if (sc->intrhand != NULL) { 328 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 329 sc->intrhand = NULL; 330 } 331 if (ifp != NULL) { 332 if_free(ifp); 333 sc->ifp = NULL; 334 } 335 if (sc->mem_res != NULL) { 336 bus_release_resource(dev, SYS_RES_IOPORT, 337 rman_get_rid(sc->mem_res), sc->mem_res); 338 sc->mem_res = NULL; 339 } 340 if (sc->irq_res != NULL) { 341 bus_release_resource(dev, SYS_RES_IRQ, 342 rman_get_rid(sc->irq_res), sc->irq_res); 343 sc->irq_res = NULL; 344 } 345 ATE_LOCK_DESTROY(sc); 346 return (0); 347 } 348 349 static void 350 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 351 { 352 struct ate_softc *sc; 353 354 if (error != 0) 355 return; 356 sc = (struct ate_softc *)arg; 357 sc->rx_desc_phys = segs[0].ds_addr; 358 } 359 360 static void 361 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 362 { 363 struct ate_softc *sc; 364 int i; 365 366 if (error != 0) 367 return; 368 sc = (struct ate_softc *)arg; 369 i = sc->rx_buf_ptr; 370 371 /* 372 * For the last buffer, set the wrap bit so the controller 373 * restarts from the first descriptor. 374 */ 375 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 376 if (i == ATE_MAX_RX_BUFFERS - 1) 377 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 378 else 379 sc->rx_descs[i].addr = segs[0].ds_addr; 380 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 381 sc->rx_descs[i].status = 0; 382 /* Flush the memory in the mbuf */ 383 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 384 } 385 386 static uint32_t 387 ate_mac_hash(const uint8_t *buf) 388 { 389 uint32_t index = 0; 390 for (int i = 0; i < 48; i++) { 391 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 392 } 393 return (index); 394 } 395 396 /* 397 * Compute the multicast filter for this device using the standard 398 * algorithm. I wonder why this isn't in ether somewhere as a lot 399 * of different MAC chips use this method (or the reverse the bits) 400 * method. 401 */ 402 static int 403 ate_setmcast(struct ate_softc *sc) 404 { 405 uint32_t index; 406 uint32_t mcaf[2]; 407 u_char *af = (u_char *) mcaf; 408 struct ifmultiaddr *ifma; 409 struct ifnet *ifp; 410 411 ifp = sc->ifp; 412 413 if ((ifp->if_flags & IFF_PROMISC) != 0) 414 return (0); 415 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 416 WR4(sc, ETH_HSL, 0xffffffff); 417 WR4(sc, ETH_HSH, 0xffffffff); 418 return (1); 419 } 420 421 /* 422 * Compute the multicast hash. 423 */ 424 mcaf[0] = 0; 425 mcaf[1] = 0; 426 if_maddr_rlock(ifp); 427 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 428 if (ifma->ifma_addr->sa_family != AF_LINK) 429 continue; 430 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 431 ifma->ifma_addr)); 432 af[index >> 3] |= 1 << (index & 7); 433 } 434 if_maddr_runlock(ifp); 435 436 /* 437 * Write the hash to the hash register. This card can also 438 * accept unicast packets as well as multicast packets using this 439 * register for easier bridging operations, but we don't take 440 * advantage of that. Locks here are to avoid LOR with the 441 * if_maddr_rlock, but might not be strictly necessary. 442 */ 443 WR4(sc, ETH_HSL, mcaf[0]); 444 WR4(sc, ETH_HSH, mcaf[1]); 445 return (mcaf[0] || mcaf[1]); 446 } 447 448 static int 449 ate_activate(device_t dev) 450 { 451 struct ate_softc *sc; 452 int err, i; 453 454 sc = device_get_softc(dev); 455 456 /* 457 * Allocate DMA tags and maps. 458 */ 459 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 460 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 461 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 462 if (err != 0) 463 goto errout; 464 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 465 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 466 if (err != 0) 467 goto errout; 468 } 469 470 /* 471 * Allocate DMA tags and maps for RX. 472 */ 473 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 474 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 475 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 476 if (err != 0) 477 goto errout; 478 479 /* 480 * DMA tag and map for the RX descriptors. 481 */ 482 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 483 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 484 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 485 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 486 &sc->sc_mtx, &sc->rx_desc_tag); 487 if (err != 0) 488 goto errout; 489 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 490 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 491 goto errout; 492 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 493 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 494 ate_getaddr, sc, 0) != 0) 495 goto errout; 496 497 /* 498 * Allocate our RX buffers. This chip has a RX structure that's filled 499 * in. 500 */ 501 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 502 sc->rx_buf_ptr = i; 503 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 504 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 505 goto errout; 506 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 507 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 508 goto errout; 509 } 510 sc->rx_buf_ptr = 0; 511 /* Flush the memory for the EMAC rx descriptor. */ 512 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 513 /* Write the descriptor queue address. */ 514 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 515 return (0); 516 517 errout: 518 return (ENOMEM); 519 } 520 521 static void 522 ate_deactivate(struct ate_softc *sc) 523 { 524 int i; 525 526 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 527 if (sc->mtag != NULL) { 528 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 529 if (sc->sent_mbuf[i] != NULL) { 530 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 531 BUS_DMASYNC_POSTWRITE); 532 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 533 m_freem(sc->sent_mbuf[i]); 534 } 535 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 536 sc->sent_mbuf[i] = NULL; 537 sc->tx_map[i] = NULL; 538 } 539 bus_dma_tag_destroy(sc->mtag); 540 } 541 if (sc->rx_desc_tag != NULL) { 542 if (sc->rx_descs != NULL) { 543 if (sc->rx_desc_phys != 0) { 544 bus_dmamap_sync(sc->rx_desc_tag, 545 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 546 bus_dmamap_unload(sc->rx_desc_tag, 547 sc->rx_desc_map); 548 sc->rx_desc_phys = 0; 549 } 550 } 551 } 552 if (sc->rxtag != NULL) { 553 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 554 if (sc->rx_buf[i] != NULL) { 555 if (sc->rx_descs[i].addr != 0) { 556 bus_dmamap_sync(sc->rxtag, 557 sc->rx_map[i], 558 BUS_DMASYNC_POSTREAD); 559 bus_dmamap_unload(sc->rxtag, 560 sc->rx_map[i]); 561 sc->rx_descs[i].addr = 0; 562 } 563 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 564 sc->rx_map[i]); 565 sc->rx_buf[i] = NULL; 566 sc->rx_map[i] = NULL; 567 } 568 } 569 bus_dma_tag_destroy(sc->rxtag); 570 } 571 if (sc->rx_desc_tag != NULL) { 572 if (sc->rx_descs != NULL) 573 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 574 sc->rx_desc_map); 575 bus_dma_tag_destroy(sc->rx_desc_tag); 576 sc->rx_descs = NULL; 577 sc->rx_desc_tag = NULL; 578 } 579 } 580 581 /* 582 * Change media according to request. 583 */ 584 static int 585 ate_ifmedia_upd(struct ifnet *ifp) 586 { 587 struct ate_softc *sc = ifp->if_softc; 588 struct mii_data *mii; 589 590 mii = device_get_softc(sc->miibus); 591 ATE_LOCK(sc); 592 mii_mediachg(mii); 593 ATE_UNLOCK(sc); 594 return (0); 595 } 596 597 /* 598 * Notify the world which media we're using. 599 */ 600 static void 601 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 602 { 603 struct ate_softc *sc = ifp->if_softc; 604 struct mii_data *mii; 605 606 mii = device_get_softc(sc->miibus); 607 ATE_LOCK(sc); 608 mii_pollstat(mii); 609 ifmr->ifm_active = mii->mii_media_active; 610 ifmr->ifm_status = mii->mii_media_status; 611 ATE_UNLOCK(sc); 612 } 613 614 static void 615 ate_stat_update(struct ate_softc *sc, int active) 616 { 617 uint32_t reg; 618 619 /* 620 * The speed and full/half-duplex state needs to be reflected 621 * in the ETH_CFG register. 622 */ 623 reg = RD4(sc, ETH_CFG); 624 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 625 if (IFM_SUBTYPE(active) != IFM_10_T) 626 reg |= ETH_CFG_SPD; 627 if (active & IFM_FDX) 628 reg |= ETH_CFG_FD; 629 WR4(sc, ETH_CFG, reg); 630 } 631 632 static void 633 ate_tick(void *xsc) 634 { 635 struct ate_softc *sc = xsc; 636 struct ifnet *ifp = sc->ifp; 637 struct mii_data *mii; 638 int active; 639 uint32_t c; 640 641 /* 642 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 643 * the MII if there's a link if this bit is clear. Not sure if we 644 * should do the same thing here or not. 645 */ 646 ATE_ASSERT_LOCKED(sc); 647 if (sc->miibus != NULL) { 648 mii = device_get_softc(sc->miibus); 649 active = mii->mii_media_active; 650 mii_tick(mii); 651 if (mii->mii_media_status & IFM_ACTIVE && 652 active != mii->mii_media_active) 653 ate_stat_update(sc, mii->mii_media_active); 654 } 655 656 /* 657 * Update the stats as best we can. When we're done, clear 658 * the status counters and start over. We're supposed to read these 659 * registers often enough that they won't overflow. Hopefully 660 * once a second is often enough. Some don't map well to 661 * the dot3Stats mib, so for those we just count them as general 662 * errors. Stats for iframes, ibutes, oframes and obytes are 663 * collected elsewhere. These registers zero on a read to prevent 664 * races. For all the collision stats, also update the collision 665 * stats for the interface. 666 */ 667 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 668 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 669 c = RD4(sc, ETH_SCOL); 670 ifp->if_collisions += c; 671 sc->mibdata.dot3StatsSingleCollisionFrames += c; 672 c = RD4(sc, ETH_MCOL); 673 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 674 ifp->if_collisions += c; 675 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 676 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 677 c = RD4(sc, ETH_LCOL); 678 sc->mibdata.dot3StatsLateCollisions += c; 679 ifp->if_collisions += c; 680 c = RD4(sc, ETH_ECOL); 681 sc->mibdata.dot3StatsExcessiveCollisions += c; 682 ifp->if_collisions += c; 683 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 684 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 685 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 686 687 /* 688 * Not sure where to lump these, so count them against the errors 689 * for the interface. 690 */ 691 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 692 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 693 RD4(sc, ETH_USF); 694 695 /* 696 * Schedule another timeout one second from now. 697 */ 698 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 699 } 700 701 static void 702 ate_set_mac(struct ate_softc *sc, u_char *eaddr) 703 { 704 705 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 706 (eaddr[1] << 8) | eaddr[0]); 707 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 708 } 709 710 static int 711 ate_get_mac(struct ate_softc *sc, u_char *eaddr) 712 { 713 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 714 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 715 uint32_t low, high; 716 int i; 717 718 /* 719 * The boot loader setup the MAC with an address, if one is set in 720 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 721 */ 722 for (i = 0; i < 4; i++) { 723 low = RD4(sc, sa_low_reg[i]); 724 high = RD4(sc, sa_high_reg[i]); 725 if ((low | (high & 0xffff)) != 0) { 726 eaddr[0] = low & 0xff; 727 eaddr[1] = (low >> 8) & 0xff; 728 eaddr[2] = (low >> 16) & 0xff; 729 eaddr[3] = (low >> 24) & 0xff; 730 eaddr[4] = high & 0xff; 731 eaddr[5] = (high >> 8) & 0xff; 732 return (0); 733 } 734 } 735 return (ENXIO); 736 } 737 738 static void 739 ate_intr(void *xsc) 740 { 741 struct ate_softc *sc = xsc; 742 struct ifnet *ifp = sc->ifp; 743 struct mbuf *mb; 744 void *bp; 745 uint32_t status, reg, rx_stat; 746 int i; 747 748 status = RD4(sc, ETH_ISR); 749 if (status == 0) 750 return; 751 if (status & ETH_ISR_RCOM) { 752 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 753 BUS_DMASYNC_POSTREAD); 754 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 755 i = sc->rx_buf_ptr; 756 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 757 bp = sc->rx_buf[i]; 758 rx_stat = sc->rx_descs[i].status; 759 if ((rx_stat & ETH_LEN_MASK) == 0) { 760 if (bootverbose) 761 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 762 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 763 BUS_DMASYNC_PREWRITE); 764 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 765 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 766 BUS_DMASYNC_POSTWRITE); 767 continue; 768 } 769 /* Flush memory for mbuf so we don't get stale bytes */ 770 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 771 BUS_DMASYNC_POSTREAD); 772 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 773 774 /* 775 * The length returned by the device includes the 776 * ethernet CRC calculation for the packet, but 777 * ifnet drivers are supposed to discard it. 778 */ 779 mb = m_devget(sc->rx_buf[i], 780 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 781 ETHER_ALIGN, ifp, NULL); 782 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 783 BUS_DMASYNC_PREWRITE); 784 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 785 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 786 BUS_DMASYNC_POSTWRITE); 787 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 788 BUS_DMASYNC_PREREAD); 789 if (mb != NULL) { 790 ifp->if_ipackets++; 791 (*ifp->if_input)(ifp, mb); 792 } 793 794 } 795 } 796 if (status & ETH_ISR_TCOM) { 797 ATE_LOCK(sc); 798 /* XXX TSR register should be cleared */ 799 if (sc->sent_mbuf[0]) { 800 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 801 BUS_DMASYNC_POSTWRITE); 802 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 803 m_freem(sc->sent_mbuf[0]); 804 ifp->if_opackets++; 805 sc->sent_mbuf[0] = NULL; 806 } 807 if (sc->sent_mbuf[1]) { 808 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 809 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 810 BUS_DMASYNC_POSTWRITE); 811 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 812 m_freem(sc->sent_mbuf[1]); 813 ifp->if_opackets++; 814 sc->txcur = 0; 815 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 816 } else { 817 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 818 sc->sent_mbuf[1] = NULL; 819 sc->txcur = 1; 820 } 821 } else { 822 sc->sent_mbuf[0] = NULL; 823 sc->txcur = 0; 824 } 825 /* 826 * We're no longer busy, so clear the busy flag and call the 827 * start routine to xmit more packets. 828 */ 829 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 830 atestart_locked(sc->ifp); 831 ATE_UNLOCK(sc); 832 } 833 if (status & ETH_ISR_RBNA) { 834 /* Workaround Errata #11 */ 835 if (bootverbose) 836 device_printf(sc->dev, "RBNA workaround\n"); 837 reg = RD4(sc, ETH_CTL); 838 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 839 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 840 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 841 } 842 } 843 844 /* 845 * Reset and initialize the chip. 846 */ 847 static void 848 ateinit_locked(void *xsc) 849 { 850 struct ate_softc *sc = xsc; 851 struct ifnet *ifp = sc->ifp; 852 struct mii_data *mii; 853 uint8_t eaddr[ETHER_ADDR_LEN]; 854 uint32_t reg; 855 856 ATE_ASSERT_LOCKED(sc); 857 858 /* 859 * XXX TODO(3) 860 * we need to turn on the EMAC clock in the pmc. With the 861 * default boot loader, this is already turned on. However, we 862 * need to think about how best to turn it on/off as the interface 863 * is brought up/down, as well as dealing with the mii bus... 864 * 865 * We also need to multiplex the pins correctly. 866 */ 867 868 /* 869 * There are two different ways that the mii bus is connected 870 * to this chip. Select the right one based on a compile-time 871 * option. 872 */ 873 reg = RD4(sc, ETH_CFG); 874 if (sc->use_rmii) 875 reg |= ETH_CFG_RMII; 876 else 877 reg &= ~ETH_CFG_RMII; 878 WR4(sc, ETH_CFG, reg); 879 880 ate_rxfilter(sc); 881 882 /* 883 * Set the chip MAC address. 884 */ 885 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 886 ate_set_mac(sc, eaddr); 887 888 /* 889 * Turn on MACs and interrupt processing. 890 */ 891 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 892 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 893 894 /* Enable big packets. */ 895 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 896 897 /* 898 * Set 'running' flag, and clear output active flag 899 * and attempt to start the output. 900 */ 901 ifp->if_drv_flags |= IFF_DRV_RUNNING; 902 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 903 904 mii = device_get_softc(sc->miibus); 905 mii_pollstat(mii); 906 ate_stat_update(sc, mii->mii_media_active); 907 atestart_locked(ifp); 908 909 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 910 } 911 912 /* 913 * Dequeue packets and transmit. 914 */ 915 static void 916 atestart_locked(struct ifnet *ifp) 917 { 918 struct ate_softc *sc = ifp->if_softc; 919 struct mbuf *m, *mdefrag; 920 bus_dma_segment_t segs[1]; 921 int nseg, e; 922 923 ATE_ASSERT_LOCKED(sc); 924 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 925 return; 926 927 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 928 /* 929 * Check to see if there's room to put another packet into the 930 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 931 * packets. We use OACTIVE to indicate "we can stuff more into 932 * our buffers (clear) or not (set)." 933 */ 934 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 935 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 936 return; 937 } 938 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 939 if (m == 0) { 940 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 941 return; 942 } 943 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 944 segs, &nseg, 0); 945 if (e == EFBIG) { 946 mdefrag = m_defrag(m, M_DONTWAIT); 947 if (mdefrag == NULL) { 948 IFQ_DRV_PREPEND(&ifp->if_snd, m); 949 return; 950 } 951 m = mdefrag; 952 e = bus_dmamap_load_mbuf_sg(sc->mtag, 953 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 954 } 955 if (e != 0) { 956 m_freem(m); 957 continue; 958 } 959 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 960 BUS_DMASYNC_PREWRITE); 961 962 /* 963 * Tell the hardware to xmit the packet. 964 */ 965 WR4(sc, ETH_TAR, segs[0].ds_addr); 966 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 967 WR4(sc, ETH_TCR, segs[0].ds_len); 968 969 /* 970 * Tap off here if there is a bpf listener. 971 */ 972 BPF_MTAP(ifp, m); 973 974 sc->sent_mbuf[sc->txcur] = m; 975 sc->txcur++; 976 } 977 } 978 979 static void 980 ateinit(void *xsc) 981 { 982 struct ate_softc *sc = xsc; 983 984 ATE_LOCK(sc); 985 ateinit_locked(sc); 986 ATE_UNLOCK(sc); 987 } 988 989 static void 990 atestart(struct ifnet *ifp) 991 { 992 struct ate_softc *sc = ifp->if_softc; 993 994 ATE_LOCK(sc); 995 atestart_locked(ifp); 996 ATE_UNLOCK(sc); 997 } 998 999 /* 1000 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1001 * so be careful. 1002 */ 1003 static void 1004 atestop(struct ate_softc *sc) 1005 { 1006 struct ifnet *ifp; 1007 int i; 1008 1009 ATE_ASSERT_LOCKED(sc); 1010 ifp = sc->ifp; 1011 if (ifp) { 1012 ifp->if_timer = 0; 1013 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1014 } 1015 1016 callout_stop(&sc->tick_ch); 1017 1018 /* 1019 * Enable some parts of the MAC that are needed always (like the 1020 * MII bus. This turns off the RE and TE bits, which will remain 1021 * off until ateinit() is called to turn them on. With RE and TE 1022 * turned off, there's no DMA to worry about after this write. 1023 */ 1024 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1025 1026 /* 1027 * Turn off all the configured options and revert to defaults. 1028 */ 1029 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1030 1031 /* 1032 * Turn off all the interrupts, and ack any pending ones by reading 1033 * the ISR. 1034 */ 1035 WR4(sc, ETH_IDR, 0xffffffff); 1036 RD4(sc, ETH_ISR); 1037 1038 /* 1039 * Clear out the Transmit and Receiver Status registers of any 1040 * errors they may be reporting 1041 */ 1042 WR4(sc, ETH_TSR, 0xffffffff); 1043 WR4(sc, ETH_RSR, 0xffffffff); 1044 1045 /* 1046 * Release TX resources. 1047 */ 1048 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1049 if (sc->sent_mbuf[i] != NULL) { 1050 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1051 BUS_DMASYNC_POSTWRITE); 1052 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1053 m_freem(sc->sent_mbuf[i]); 1054 sc->sent_mbuf[i] = NULL; 1055 } 1056 } 1057 1058 /* 1059 * XXX we should power down the EMAC if it isn't in use, after 1060 * putting it into loopback mode. This saves about 400uA according 1061 * to the datasheet. 1062 */ 1063 } 1064 1065 static void 1066 ate_rxfilter(struct ate_softc *sc) 1067 { 1068 struct ifnet *ifp; 1069 uint32_t reg; 1070 int enabled; 1071 1072 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1073 ATE_ASSERT_LOCKED(sc); 1074 ifp = sc->ifp; 1075 1076 /* 1077 * Wipe out old filter settings. 1078 */ 1079 reg = RD4(sc, ETH_CFG); 1080 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1081 reg |= ETH_CFG_NBC; 1082 sc->flags &= ~ATE_FLAG_MULTICAST; 1083 1084 /* 1085 * Set new parameters. 1086 */ 1087 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1088 reg &= ~ETH_CFG_NBC; 1089 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1090 reg |= ETH_CFG_CAF; 1091 } else { 1092 enabled = ate_setmcast(sc); 1093 if (enabled != 0) { 1094 reg |= ETH_CFG_MTI; 1095 sc->flags |= ATE_FLAG_MULTICAST; 1096 } 1097 } 1098 WR4(sc, ETH_CFG, reg); 1099 } 1100 1101 static int 1102 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1103 { 1104 struct ate_softc *sc = ifp->if_softc; 1105 struct mii_data *mii; 1106 struct ifreq *ifr = (struct ifreq *)data; 1107 int drv_flags, flags; 1108 int mask, error, enabled; 1109 1110 error = 0; 1111 flags = ifp->if_flags; 1112 drv_flags = ifp->if_drv_flags; 1113 switch (cmd) { 1114 case SIOCSIFFLAGS: 1115 ATE_LOCK(sc); 1116 if ((flags & IFF_UP) != 0) { 1117 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1118 if (((flags ^ sc->if_flags) 1119 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1120 ate_rxfilter(sc); 1121 } else { 1122 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1123 ateinit_locked(sc); 1124 } 1125 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1126 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1127 atestop(sc); 1128 } 1129 sc->if_flags = flags; 1130 ATE_UNLOCK(sc); 1131 break; 1132 1133 case SIOCADDMULTI: 1134 case SIOCDELMULTI: 1135 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1136 ATE_LOCK(sc); 1137 enabled = ate_setmcast(sc); 1138 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1139 ate_rxfilter(sc); 1140 ATE_UNLOCK(sc); 1141 } 1142 break; 1143 1144 case SIOCSIFMEDIA: 1145 case SIOCGIFMEDIA: 1146 mii = device_get_softc(sc->miibus); 1147 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1148 break; 1149 case SIOCSIFCAP: 1150 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1151 if (mask & IFCAP_VLAN_MTU) { 1152 ATE_LOCK(sc); 1153 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1154 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1155 ifp->if_capenable |= IFCAP_VLAN_MTU; 1156 } else { 1157 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1158 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1159 } 1160 ATE_UNLOCK(sc); 1161 } 1162 default: 1163 error = ether_ioctl(ifp, cmd, data); 1164 break; 1165 } 1166 return (error); 1167 } 1168 1169 static void 1170 ate_child_detached(device_t dev, device_t child) 1171 { 1172 struct ate_softc *sc; 1173 1174 sc = device_get_softc(dev); 1175 if (child == sc->miibus) 1176 sc->miibus = NULL; 1177 } 1178 1179 /* 1180 * MII bus support routines. 1181 */ 1182 static int 1183 ate_miibus_readreg(device_t dev, int phy, int reg) 1184 { 1185 struct ate_softc *sc; 1186 int val; 1187 1188 /* 1189 * XXX if we implement agressive power savings, then we need 1190 * XXX to make sure that the clock to the emac is on here 1191 */ 1192 1193 sc = device_get_softc(dev); 1194 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1195 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1196 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1197 continue; 1198 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1199 1200 return (val); 1201 } 1202 1203 static int 1204 ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1205 { 1206 struct ate_softc *sc; 1207 1208 /* 1209 * XXX if we implement agressive power savings, then we need 1210 * XXX to make sure that the clock to the emac is on here 1211 */ 1212 1213 sc = device_get_softc(dev); 1214 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1215 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1216 continue; 1217 return (0); 1218 } 1219 1220 static device_method_t ate_methods[] = { 1221 /* Device interface */ 1222 DEVMETHOD(device_probe, ate_probe), 1223 DEVMETHOD(device_attach, ate_attach), 1224 DEVMETHOD(device_detach, ate_detach), 1225 1226 /* Bus interface */ 1227 DEVMETHOD(bus_child_detached, ate_child_detached), 1228 1229 /* MII interface */ 1230 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1231 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1232 1233 { 0, 0 } 1234 }; 1235 1236 static driver_t ate_driver = { 1237 "ate", 1238 ate_methods, 1239 sizeof(struct ate_softc), 1240 }; 1241 1242 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1243 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1244 MODULE_DEPEND(ate, miibus, 1, 1, 1); 1245 MODULE_DEPEND(ate, ether, 1, 1, 1);
Cache object: d9fefa2397be787415094443c28f484d
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