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sys/arm/at91/if_ate.c
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1 /*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/mbuf.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <machine/bus.h> 47 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_mib.h> 54 #include <net/if_types.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #endif 62 63 #include <net/bpf.h> 64 #include <net/bpfdesc.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <arm/at91/if_atereg.h> 69 70 #include "miibus_if.h" 71 72 #define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73 #define ATE_MAX_RX_BUFFERS 64 74 75 /* 76 * Driver-specific flags. 77 */ 78 #define ATE_FLAG_DETACHING 0x01 79 #define ATE_FLAG_MULTICAST 0x02 80 81 struct ate_softc 82 { 83 struct ifnet *ifp; /* ifnet pointer */ 84 struct mtx sc_mtx; /* Basically a perimeter lock */ 85 device_t dev; /* Myself */ 86 device_t miibus; /* My child miibus */ 87 struct resource *irq_res; /* IRQ resource */ 88 struct resource *mem_res; /* Memory resource */ 89 struct callout tick_ch; /* Tick callout */ 90 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 91 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 92 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 93 bus_dma_tag_t rxtag; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 97 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 101 void *intrhand; /* Interrupt handle */ 102 int flags; 103 int if_flags; 104 int rx_buf_ptr; 105 int txcur; /* Current TX map pointer */ 106 int use_rmii; 107 }; 108 109 static inline uint32_t 110 RD4(struct ate_softc *sc, bus_size_t off) 111 { 112 113 return (bus_read_4(sc->mem_res, off)); 114 } 115 116 static inline void 117 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 118 { 119 120 bus_write_4(sc->mem_res, off, val); 121 } 122 123 static inline void 124 BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 125 { 126 127 bus_barrier(sc->mem_res, off, len, flags); 128 } 129 130 #define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 131 #define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 132 #define ATE_LOCK_INIT(_sc) \ 133 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 134 MTX_NETWORK_LOCK, MTX_DEF) 135 #define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 136 #define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 137 #define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 138 139 static devclass_t ate_devclass; 140 141 /* 142 * ifnet entry points. 143 */ 144 static void ateinit_locked(void *); 145 static void atestart_locked(struct ifnet *); 146 147 static void ateinit(void *); 148 static void atestart(struct ifnet *); 149 static void atestop(struct ate_softc *); 150 static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 151 152 /* 153 * Bus entry points. 154 */ 155 static int ate_probe(device_t dev); 156 static int ate_attach(device_t dev); 157 static int ate_detach(device_t dev); 158 static void ate_intr(void *); 159 160 /* 161 * Helper routines. 162 */ 163 static int ate_activate(device_t dev); 164 static void ate_deactivate(struct ate_softc *sc); 165 static int ate_ifmedia_upd(struct ifnet *ifp); 166 static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 167 static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 168 static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 169 static void ate_rxfilter(struct ate_softc *sc); 170 171 /* 172 * The AT91 family of products has the ethernet called EMAC. However, 173 * it isn't self identifying. It is anticipated that the parent bus 174 * code will take care to only add ate devices where they really are. As 175 * such, we do nothing here to identify the device and just set its name. 176 */ 177 static int 178 ate_probe(device_t dev) 179 { 180 181 device_set_desc(dev, "EMAC"); 182 return (0); 183 } 184 185 static int 186 ate_attach(device_t dev) 187 { 188 struct ate_softc *sc; 189 struct ifnet *ifp = NULL; 190 struct sysctl_ctx_list *sctx; 191 struct sysctl_oid *soid; 192 u_char eaddr[ETHER_ADDR_LEN]; 193 uint32_t rnd; 194 int rid, err; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 ATE_LOCK_INIT(sc); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 237 238 if ((err = ate_get_mac(sc, eaddr)) != 0) { 239 /* 240 * No MAC address configured. Generate the random one. 241 */ 242 if (bootverbose) 243 device_printf(dev, 244 "Generating random ethernet address.\n"); 245 rnd = arc4random(); 246 247 /* 248 * Set OUI to convenient locally assigned address. 'b' 249 * is 0x62, which has the locally assigned bit set, and 250 * the broadcast/multicast bit clear. 251 */ 252 eaddr[0] = 'b'; 253 eaddr[1] = 's'; 254 eaddr[2] = 'd'; 255 eaddr[3] = (rnd >> 16) & 0xff; 256 eaddr[4] = (rnd >> 8) & 0xff; 257 eaddr[5] = rnd & 0xff; 258 } 259 260 sc->ifp = ifp = if_alloc(IFT_ETHER); 261 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 262 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 263 if (err != 0) { 264 device_printf(dev, "attaching PHYs failed\n"); 265 goto out; 266 } 267 268 ifp->if_softc = sc; 269 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 271 ifp->if_capabilities |= IFCAP_VLAN_MTU; 272 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 273 ifp->if_start = atestart; 274 ifp->if_ioctl = ateioctl; 275 ifp->if_init = ateinit; 276 ifp->if_baudrate = 10000000; 277 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 278 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 279 IFQ_SET_READY(&ifp->if_snd); 280 ifp->if_timer = 0; 281 ifp->if_linkmib = &sc->mibdata; 282 ifp->if_linkmiblen = sizeof(sc->mibdata); 283 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 284 sc->if_flags = ifp->if_flags; 285 286 ether_ifattach(ifp, eaddr); 287 288 /* 289 * Activate the interrupt. 290 */ 291 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 292 NULL, ate_intr, sc, &sc->intrhand); 293 if (err) { 294 device_printf(dev, "could not establish interrupt handler.\n"); 295 ether_ifdetach(ifp); 296 goto out; 297 } 298 299 out: 300 if (err) 301 ate_detach(dev); 302 return (err); 303 } 304 305 static int 306 ate_detach(device_t dev) 307 { 308 struct ate_softc *sc; 309 struct ifnet *ifp; 310 311 sc = device_get_softc(dev); 312 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 313 ifp = sc->ifp; 314 if (device_is_attached(dev)) { 315 ATE_LOCK(sc); 316 sc->flags |= ATE_FLAG_DETACHING; 317 atestop(sc); 318 ATE_UNLOCK(sc); 319 callout_drain(&sc->tick_ch); 320 ether_ifdetach(ifp); 321 } 322 if (sc->miibus != NULL) { 323 device_delete_child(dev, sc->miibus); 324 sc->miibus = NULL; 325 } 326 bus_generic_detach(sc->dev); 327 ate_deactivate(sc); 328 if (sc->intrhand != NULL) { 329 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 330 sc->intrhand = NULL; 331 } 332 if (ifp != NULL) { 333 if_free(ifp); 334 sc->ifp = NULL; 335 } 336 if (sc->mem_res != NULL) { 337 bus_release_resource(dev, SYS_RES_IOPORT, 338 rman_get_rid(sc->mem_res), sc->mem_res); 339 sc->mem_res = NULL; 340 } 341 if (sc->irq_res != NULL) { 342 bus_release_resource(dev, SYS_RES_IRQ, 343 rman_get_rid(sc->irq_res), sc->irq_res); 344 sc->irq_res = NULL; 345 } 346 ATE_LOCK_DESTROY(sc); 347 return (0); 348 } 349 350 static void 351 ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 352 { 353 struct ate_softc *sc; 354 355 if (error != 0) 356 return; 357 sc = (struct ate_softc *)arg; 358 sc->rx_desc_phys = segs[0].ds_addr; 359 } 360 361 static void 362 ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 363 { 364 struct ate_softc *sc; 365 int i; 366 367 if (error != 0) 368 return; 369 sc = (struct ate_softc *)arg; 370 i = sc->rx_buf_ptr; 371 372 /* 373 * For the last buffer, set the wrap bit so the controller 374 * restarts from the first descriptor. 375 */ 376 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 377 if (i == ATE_MAX_RX_BUFFERS - 1) 378 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 379 else 380 sc->rx_descs[i].addr = segs[0].ds_addr; 381 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 382 sc->rx_descs[i].status = 0; 383 /* Flush the memory in the mbuf */ 384 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 385 } 386 387 static uint32_t 388 ate_mac_hash(const uint8_t *buf) 389 { 390 uint32_t index = 0; 391 for (int i = 0; i < 48; i++) { 392 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 393 } 394 return (index); 395 } 396 397 /* 398 * Compute the multicast filter for this device using the standard 399 * algorithm. I wonder why this isn't in ether somewhere as a lot 400 * of different MAC chips use this method (or the reverse the bits) 401 * method. 402 */ 403 static int 404 ate_setmcast(struct ate_softc *sc) 405 { 406 uint32_t index; 407 uint32_t mcaf[2]; 408 u_char *af = (u_char *) mcaf; 409 struct ifmultiaddr *ifma; 410 struct ifnet *ifp; 411 412 ifp = sc->ifp; 413 414 if ((ifp->if_flags & IFF_PROMISC) != 0) 415 return (0); 416 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 417 WR4(sc, ETH_HSL, 0xffffffff); 418 WR4(sc, ETH_HSH, 0xffffffff); 419 return (1); 420 } 421 422 /* 423 * Compute the multicast hash. 424 */ 425 mcaf[0] = 0; 426 mcaf[1] = 0; 427 if_maddr_rlock(ifp); 428 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 429 if (ifma->ifma_addr->sa_family != AF_LINK) 430 continue; 431 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 432 ifma->ifma_addr)); 433 af[index >> 3] |= 1 << (index & 7); 434 } 435 if_maddr_runlock(ifp); 436 437 /* 438 * Write the hash to the hash register. This card can also 439 * accept unicast packets as well as multicast packets using this 440 * register for easier bridging operations, but we don't take 441 * advantage of that. Locks here are to avoid LOR with the 442 * if_maddr_rlock, but might not be strictly necessary. 443 */ 444 WR4(sc, ETH_HSL, mcaf[0]); 445 WR4(sc, ETH_HSH, mcaf[1]); 446 return (mcaf[0] || mcaf[1]); 447 } 448 449 static int 450 ate_activate(device_t dev) 451 { 452 struct ate_softc *sc; 453 int err, i; 454 455 sc = device_get_softc(dev); 456 457 /* 458 * Allocate DMA tags and maps. 459 */ 460 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 461 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 462 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 463 if (err != 0) 464 goto errout; 465 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 466 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 467 if (err != 0) 468 goto errout; 469 } 470 471 /* 472 * Allocate DMA tags and maps for RX. 473 */ 474 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 475 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 476 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 477 if (err != 0) 478 goto errout; 479 480 /* 481 * DMA tag and map for the RX descriptors. 482 */ 483 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 484 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 485 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 486 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 487 &sc->sc_mtx, &sc->rx_desc_tag); 488 if (err != 0) 489 goto errout; 490 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 491 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 492 goto errout; 493 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 494 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 495 ate_getaddr, sc, 0) != 0) 496 goto errout; 497 498 /* 499 * Allocate our RX buffers. This chip has a RX structure that's filled 500 * in. 501 */ 502 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 503 sc->rx_buf_ptr = i; 504 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 505 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 506 goto errout; 507 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 508 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 509 goto errout; 510 } 511 sc->rx_buf_ptr = 0; 512 /* Flush the memory for the EMAC rx descriptor. */ 513 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 514 /* Write the descriptor queue address. */ 515 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 516 return (0); 517 518 errout: 519 return (ENOMEM); 520 } 521 522 static void 523 ate_deactivate(struct ate_softc *sc) 524 { 525 int i; 526 527 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 528 if (sc->mtag != NULL) { 529 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 530 if (sc->sent_mbuf[i] != NULL) { 531 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 532 BUS_DMASYNC_POSTWRITE); 533 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 534 m_freem(sc->sent_mbuf[i]); 535 } 536 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 537 sc->sent_mbuf[i] = NULL; 538 sc->tx_map[i] = NULL; 539 } 540 bus_dma_tag_destroy(sc->mtag); 541 } 542 if (sc->rx_desc_tag != NULL) { 543 if (sc->rx_descs != NULL) { 544 if (sc->rx_desc_phys != 0) { 545 bus_dmamap_sync(sc->rx_desc_tag, 546 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 547 bus_dmamap_unload(sc->rx_desc_tag, 548 sc->rx_desc_map); 549 sc->rx_desc_phys = 0; 550 } 551 } 552 } 553 if (sc->rxtag != NULL) { 554 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 555 if (sc->rx_buf[i] != NULL) { 556 if (sc->rx_descs[i].addr != 0) { 557 bus_dmamap_sync(sc->rxtag, 558 sc->rx_map[i], 559 BUS_DMASYNC_POSTREAD); 560 bus_dmamap_unload(sc->rxtag, 561 sc->rx_map[i]); 562 sc->rx_descs[i].addr = 0; 563 } 564 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 565 sc->rx_map[i]); 566 sc->rx_buf[i] = NULL; 567 sc->rx_map[i] = NULL; 568 } 569 } 570 bus_dma_tag_destroy(sc->rxtag); 571 } 572 if (sc->rx_desc_tag != NULL) { 573 if (sc->rx_descs != NULL) 574 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 575 sc->rx_desc_map); 576 bus_dma_tag_destroy(sc->rx_desc_tag); 577 sc->rx_descs = NULL; 578 sc->rx_desc_tag = NULL; 579 } 580 } 581 582 /* 583 * Change media according to request. 584 */ 585 static int 586 ate_ifmedia_upd(struct ifnet *ifp) 587 { 588 struct ate_softc *sc = ifp->if_softc; 589 struct mii_data *mii; 590 591 mii = device_get_softc(sc->miibus); 592 ATE_LOCK(sc); 593 mii_mediachg(mii); 594 ATE_UNLOCK(sc); 595 return (0); 596 } 597 598 /* 599 * Notify the world which media we're using. 600 */ 601 static void 602 ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 603 { 604 struct ate_softc *sc = ifp->if_softc; 605 struct mii_data *mii; 606 607 mii = device_get_softc(sc->miibus); 608 ATE_LOCK(sc); 609 mii_pollstat(mii); 610 ifmr->ifm_active = mii->mii_media_active; 611 ifmr->ifm_status = mii->mii_media_status; 612 ATE_UNLOCK(sc); 613 } 614 615 static void 616 ate_stat_update(struct ate_softc *sc, int active) 617 { 618 uint32_t reg; 619 620 /* 621 * The speed and full/half-duplex state needs to be reflected 622 * in the ETH_CFG register. 623 */ 624 reg = RD4(sc, ETH_CFG); 625 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 626 if (IFM_SUBTYPE(active) != IFM_10_T) 627 reg |= ETH_CFG_SPD; 628 if (active & IFM_FDX) 629 reg |= ETH_CFG_FD; 630 WR4(sc, ETH_CFG, reg); 631 } 632 633 static void 634 ate_tick(void *xsc) 635 { 636 struct ate_softc *sc = xsc; 637 struct ifnet *ifp = sc->ifp; 638 struct mii_data *mii; 639 int active; 640 uint32_t c; 641 642 /* 643 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 644 * the MII if there's a link if this bit is clear. Not sure if we 645 * should do the same thing here or not. 646 */ 647 ATE_ASSERT_LOCKED(sc); 648 if (sc->miibus != NULL) { 649 mii = device_get_softc(sc->miibus); 650 active = mii->mii_media_active; 651 mii_tick(mii); 652 if (mii->mii_media_status & IFM_ACTIVE && 653 active != mii->mii_media_active) 654 ate_stat_update(sc, mii->mii_media_active); 655 } 656 657 /* 658 * Update the stats as best we can. When we're done, clear 659 * the status counters and start over. We're supposed to read these 660 * registers often enough that they won't overflow. Hopefully 661 * once a second is often enough. Some don't map well to 662 * the dot3Stats mib, so for those we just count them as general 663 * errors. Stats for iframes, ibutes, oframes and obytes are 664 * collected elsewhere. These registers zero on a read to prevent 665 * races. For all the collision stats, also update the collision 666 * stats for the interface. 667 */ 668 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 669 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 670 c = RD4(sc, ETH_SCOL); 671 ifp->if_collisions += c; 672 sc->mibdata.dot3StatsSingleCollisionFrames += c; 673 c = RD4(sc, ETH_MCOL); 674 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 675 ifp->if_collisions += c; 676 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 677 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 678 c = RD4(sc, ETH_LCOL); 679 sc->mibdata.dot3StatsLateCollisions += c; 680 ifp->if_collisions += c; 681 c = RD4(sc, ETH_ECOL); 682 sc->mibdata.dot3StatsExcessiveCollisions += c; 683 ifp->if_collisions += c; 684 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 685 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 686 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 687 688 /* 689 * Not sure where to lump these, so count them against the errors 690 * for the interface. 691 */ 692 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 693 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 694 RD4(sc, ETH_USF); 695 696 /* 697 * Schedule another timeout one second from now. 698 */ 699 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 700 } 701 702 static void 703 ate_set_mac(struct ate_softc *sc, u_char *eaddr) 704 { 705 706 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 707 (eaddr[1] << 8) | eaddr[0]); 708 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 709 } 710 711 static int 712 ate_get_mac(struct ate_softc *sc, u_char *eaddr) 713 { 714 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 715 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 716 uint32_t low, high; 717 int i; 718 719 /* 720 * The boot loader setup the MAC with an address, if one is set in 721 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 722 */ 723 for (i = 0; i < 4; i++) { 724 low = RD4(sc, sa_low_reg[i]); 725 high = RD4(sc, sa_high_reg[i]); 726 if ((low | (high & 0xffff)) != 0) { 727 eaddr[0] = low & 0xff; 728 eaddr[1] = (low >> 8) & 0xff; 729 eaddr[2] = (low >> 16) & 0xff; 730 eaddr[3] = (low >> 24) & 0xff; 731 eaddr[4] = high & 0xff; 732 eaddr[5] = (high >> 8) & 0xff; 733 return (0); 734 } 735 } 736 return (ENXIO); 737 } 738 739 static void 740 ate_intr(void *xsc) 741 { 742 struct ate_softc *sc = xsc; 743 struct ifnet *ifp = sc->ifp; 744 struct mbuf *mb; 745 void *bp; 746 uint32_t status, reg, rx_stat; 747 int i; 748 749 status = RD4(sc, ETH_ISR); 750 if (status == 0) 751 return; 752 if (status & ETH_ISR_RCOM) { 753 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 754 BUS_DMASYNC_POSTREAD); 755 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 756 i = sc->rx_buf_ptr; 757 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 758 bp = sc->rx_buf[i]; 759 rx_stat = sc->rx_descs[i].status; 760 if ((rx_stat & ETH_LEN_MASK) == 0) { 761 if (bootverbose) 762 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 763 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 764 BUS_DMASYNC_PREWRITE); 765 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 766 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 767 BUS_DMASYNC_POSTWRITE); 768 continue; 769 } 770 /* Flush memory for mbuf so we don't get stale bytes */ 771 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 772 BUS_DMASYNC_POSTREAD); 773 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 774 775 /* 776 * The length returned by the device includes the 777 * ethernet CRC calculation for the packet, but 778 * ifnet drivers are supposed to discard it. 779 */ 780 mb = m_devget(sc->rx_buf[i], 781 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 782 ETHER_ALIGN, ifp, NULL); 783 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 784 BUS_DMASYNC_PREWRITE); 785 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 786 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 787 BUS_DMASYNC_POSTWRITE); 788 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 789 BUS_DMASYNC_PREREAD); 790 if (mb != NULL) { 791 ifp->if_ipackets++; 792 (*ifp->if_input)(ifp, mb); 793 } 794 795 } 796 } 797 if (status & ETH_ISR_TCOM) { 798 ATE_LOCK(sc); 799 /* XXX TSR register should be cleared */ 800 if (sc->sent_mbuf[0]) { 801 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 802 BUS_DMASYNC_POSTWRITE); 803 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 804 m_freem(sc->sent_mbuf[0]); 805 ifp->if_opackets++; 806 sc->sent_mbuf[0] = NULL; 807 } 808 if (sc->sent_mbuf[1]) { 809 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 810 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 811 BUS_DMASYNC_POSTWRITE); 812 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 813 m_freem(sc->sent_mbuf[1]); 814 ifp->if_opackets++; 815 sc->txcur = 0; 816 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 817 } else { 818 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 819 sc->sent_mbuf[1] = NULL; 820 sc->txcur = 1; 821 } 822 } else { 823 sc->sent_mbuf[0] = NULL; 824 sc->txcur = 0; 825 } 826 /* 827 * We're no longer busy, so clear the busy flag and call the 828 * start routine to xmit more packets. 829 */ 830 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 831 atestart_locked(sc->ifp); 832 ATE_UNLOCK(sc); 833 } 834 if (status & ETH_ISR_RBNA) { 835 /* Workaround Errata #11 */ 836 if (bootverbose) 837 device_printf(sc->dev, "RBNA workaround\n"); 838 reg = RD4(sc, ETH_CTL); 839 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 840 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 841 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 842 } 843 } 844 845 /* 846 * Reset and initialize the chip. 847 */ 848 static void 849 ateinit_locked(void *xsc) 850 { 851 struct ate_softc *sc = xsc; 852 struct ifnet *ifp = sc->ifp; 853 struct mii_data *mii; 854 uint8_t eaddr[ETHER_ADDR_LEN]; 855 uint32_t reg; 856 857 ATE_ASSERT_LOCKED(sc); 858 859 /* 860 * XXX TODO(3) 861 * we need to turn on the EMAC clock in the pmc. With the 862 * default boot loader, this is already turned on. However, we 863 * need to think about how best to turn it on/off as the interface 864 * is brought up/down, as well as dealing with the mii bus... 865 * 866 * We also need to multiplex the pins correctly. 867 */ 868 869 /* 870 * There are two different ways that the mii bus is connected 871 * to this chip. Select the right one based on a compile-time 872 * option. 873 */ 874 reg = RD4(sc, ETH_CFG); 875 if (sc->use_rmii) 876 reg |= ETH_CFG_RMII; 877 else 878 reg &= ~ETH_CFG_RMII; 879 WR4(sc, ETH_CFG, reg); 880 881 ate_rxfilter(sc); 882 883 /* 884 * Set the chip MAC address. 885 */ 886 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 887 ate_set_mac(sc, eaddr); 888 889 /* 890 * Turn on MACs and interrupt processing. 891 */ 892 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 893 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 894 895 /* Enable big packets. */ 896 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 897 898 /* 899 * Set 'running' flag, and clear output active flag 900 * and attempt to start the output. 901 */ 902 ifp->if_drv_flags |= IFF_DRV_RUNNING; 903 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 904 905 mii = device_get_softc(sc->miibus); 906 mii_pollstat(mii); 907 ate_stat_update(sc, mii->mii_media_active); 908 atestart_locked(ifp); 909 910 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 911 } 912 913 /* 914 * Dequeue packets and transmit. 915 */ 916 static void 917 atestart_locked(struct ifnet *ifp) 918 { 919 struct ate_softc *sc = ifp->if_softc; 920 struct mbuf *m, *mdefrag; 921 bus_dma_segment_t segs[1]; 922 int nseg, e; 923 924 ATE_ASSERT_LOCKED(sc); 925 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 926 return; 927 928 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 929 /* 930 * Check to see if there's room to put another packet into the 931 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 932 * packets. We use OACTIVE to indicate "we can stuff more into 933 * our buffers (clear) or not (set)." 934 */ 935 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 936 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 937 return; 938 } 939 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 940 if (m == 0) { 941 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 942 return; 943 } 944 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 945 segs, &nseg, 0); 946 if (e == EFBIG) { 947 mdefrag = m_defrag(m, M_DONTWAIT); 948 if (mdefrag == NULL) { 949 IFQ_DRV_PREPEND(&ifp->if_snd, m); 950 return; 951 } 952 m = mdefrag; 953 e = bus_dmamap_load_mbuf_sg(sc->mtag, 954 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 955 } 956 if (e != 0) { 957 m_freem(m); 958 continue; 959 } 960 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 961 BUS_DMASYNC_PREWRITE); 962 963 /* 964 * Tell the hardware to xmit the packet. 965 */ 966 WR4(sc, ETH_TAR, segs[0].ds_addr); 967 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 968 WR4(sc, ETH_TCR, segs[0].ds_len); 969 970 /* 971 * Tap off here if there is a bpf listener. 972 */ 973 BPF_MTAP(ifp, m); 974 975 sc->sent_mbuf[sc->txcur] = m; 976 sc->txcur++; 977 } 978 } 979 980 static void 981 ateinit(void *xsc) 982 { 983 struct ate_softc *sc = xsc; 984 985 ATE_LOCK(sc); 986 ateinit_locked(sc); 987 ATE_UNLOCK(sc); 988 } 989 990 static void 991 atestart(struct ifnet *ifp) 992 { 993 struct ate_softc *sc = ifp->if_softc; 994 995 ATE_LOCK(sc); 996 atestart_locked(ifp); 997 ATE_UNLOCK(sc); 998 } 999 1000 /* 1001 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1002 * so be careful. 1003 */ 1004 static void 1005 atestop(struct ate_softc *sc) 1006 { 1007 struct ifnet *ifp; 1008 int i; 1009 1010 ATE_ASSERT_LOCKED(sc); 1011 ifp = sc->ifp; 1012 if (ifp) { 1013 ifp->if_timer = 0; 1014 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1015 } 1016 1017 callout_stop(&sc->tick_ch); 1018 1019 /* 1020 * Enable some parts of the MAC that are needed always (like the 1021 * MII bus. This turns off the RE and TE bits, which will remain 1022 * off until ateinit() is called to turn them on. With RE and TE 1023 * turned off, there's no DMA to worry about after this write. 1024 */ 1025 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1026 1027 /* 1028 * Turn off all the configured options and revert to defaults. 1029 */ 1030 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1031 1032 /* 1033 * Turn off all the interrupts, and ack any pending ones by reading 1034 * the ISR. 1035 */ 1036 WR4(sc, ETH_IDR, 0xffffffff); 1037 RD4(sc, ETH_ISR); 1038 1039 /* 1040 * Clear out the Transmit and Receiver Status registers of any 1041 * errors they may be reporting 1042 */ 1043 WR4(sc, ETH_TSR, 0xffffffff); 1044 WR4(sc, ETH_RSR, 0xffffffff); 1045 1046 /* 1047 * Release TX resources. 1048 */ 1049 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1050 if (sc->sent_mbuf[i] != NULL) { 1051 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1052 BUS_DMASYNC_POSTWRITE); 1053 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1054 m_freem(sc->sent_mbuf[i]); 1055 sc->sent_mbuf[i] = NULL; 1056 } 1057 } 1058 1059 /* 1060 * XXX we should power down the EMAC if it isn't in use, after 1061 * putting it into loopback mode. This saves about 400uA according 1062 * to the datasheet. 1063 */ 1064 } 1065 1066 static void 1067 ate_rxfilter(struct ate_softc *sc) 1068 { 1069 struct ifnet *ifp; 1070 uint32_t reg; 1071 int enabled; 1072 1073 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1074 ATE_ASSERT_LOCKED(sc); 1075 ifp = sc->ifp; 1076 1077 /* 1078 * Wipe out old filter settings. 1079 */ 1080 reg = RD4(sc, ETH_CFG); 1081 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1082 reg |= ETH_CFG_NBC; 1083 sc->flags &= ~ATE_FLAG_MULTICAST; 1084 1085 /* 1086 * Set new parameters. 1087 */ 1088 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1089 reg &= ~ETH_CFG_NBC; 1090 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1091 reg |= ETH_CFG_CAF; 1092 } else { 1093 enabled = ate_setmcast(sc); 1094 if (enabled != 0) { 1095 reg |= ETH_CFG_MTI; 1096 sc->flags |= ATE_FLAG_MULTICAST; 1097 } 1098 } 1099 WR4(sc, ETH_CFG, reg); 1100 } 1101 1102 static int 1103 ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1104 { 1105 struct ate_softc *sc = ifp->if_softc; 1106 struct mii_data *mii; 1107 struct ifreq *ifr = (struct ifreq *)data; 1108 int drv_flags, flags; 1109 int mask, error, enabled; 1110 1111 error = 0; 1112 flags = ifp->if_flags; 1113 drv_flags = ifp->if_drv_flags; 1114 switch (cmd) { 1115 case SIOCSIFFLAGS: 1116 ATE_LOCK(sc); 1117 if ((flags & IFF_UP) != 0) { 1118 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1119 if (((flags ^ sc->if_flags) 1120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1121 ate_rxfilter(sc); 1122 } else { 1123 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1124 ateinit_locked(sc); 1125 } 1126 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1127 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1128 atestop(sc); 1129 } 1130 sc->if_flags = flags; 1131 ATE_UNLOCK(sc); 1132 break; 1133 1134 case SIOCADDMULTI: 1135 case SIOCDELMULTI: 1136 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1137 ATE_LOCK(sc); 1138 enabled = ate_setmcast(sc); 1139 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1140 ate_rxfilter(sc); 1141 ATE_UNLOCK(sc); 1142 } 1143 break; 1144 1145 case SIOCSIFMEDIA: 1146 case SIOCGIFMEDIA: 1147 mii = device_get_softc(sc->miibus); 1148 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1149 break; 1150 case SIOCSIFCAP: 1151 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1152 if (mask & IFCAP_VLAN_MTU) { 1153 ATE_LOCK(sc); 1154 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1155 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1156 ifp->if_capenable |= IFCAP_VLAN_MTU; 1157 } else { 1158 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1159 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1160 } 1161 ATE_UNLOCK(sc); 1162 } 1163 default: 1164 error = ether_ioctl(ifp, cmd, data); 1165 break; 1166 } 1167 return (error); 1168 } 1169 1170 static void 1171 ate_child_detached(device_t dev, device_t child) 1172 { 1173 struct ate_softc *sc; 1174 1175 sc = device_get_softc(dev); 1176 if (child == sc->miibus) 1177 sc->miibus = NULL; 1178 } 1179 1180 /* 1181 * MII bus support routines. 1182 */ 1183 static int 1184 ate_miibus_readreg(device_t dev, int phy, int reg) 1185 { 1186 struct ate_softc *sc; 1187 int val; 1188 1189 /* 1190 * XXX if we implement agressive power savings, then we need 1191 * XXX to make sure that the clock to the emac is on here 1192 */ 1193 1194 sc = device_get_softc(dev); 1195 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1196 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1197 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1198 continue; 1199 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1200 1201 return (val); 1202 } 1203 1204 static int 1205 ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1206 { 1207 struct ate_softc *sc; 1208 1209 /* 1210 * XXX if we implement agressive power savings, then we need 1211 * XXX to make sure that the clock to the emac is on here 1212 */ 1213 1214 sc = device_get_softc(dev); 1215 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1216 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1217 continue; 1218 return (0); 1219 } 1220 1221 static device_method_t ate_methods[] = { 1222 /* Device interface */ 1223 DEVMETHOD(device_probe, ate_probe), 1224 DEVMETHOD(device_attach, ate_attach), 1225 DEVMETHOD(device_detach, ate_detach), 1226 1227 /* Bus interface */ 1228 DEVMETHOD(bus_child_detached, ate_child_detached), 1229 1230 /* MII interface */ 1231 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1232 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1233 1234 { 0, 0 } 1235 }; 1236 1237 static driver_t ate_driver = { 1238 "ate", 1239 ate_methods, 1240 sizeof(struct ate_softc), 1241 }; 1242 1243 DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1244 DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1245 MODULE_DEPEND(ate, miibus, 1, 1, 1); 1246 MODULE_DEPEND(ate, ether, 1, 1, 1);
Cache object: ccb54bfb3e51e929fd9d9887daf65fc9
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