The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/at91/if_macbreg.h

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    1 /*
    2  * $FreeBSD$
    3  */
    4 
    5 #ifndef MACB_REG_H
    6 #define MACB_REG_H
    7 
    8 #define EMAC_NCR                0x00
    9 #define EMAC_NCFGR              0x04
   10 #define EMAC_TSR                0x14
   11 #define EMAC_RSR                0x20
   12 #define EMAC_ISR                0x24
   13 #define EMAC_IER                0x28
   14 #define EMAC_IDR                0x2C
   15 #define EMAC_IMR                0x30
   16 
   17 
   18 
   19 #define EMAC_RBQP               0x18
   20 #define EMAC_TBQP               0x1C
   21 
   22 #define EMAC_HRB                0x90
   23 #define EMAC_HRT                0x94
   24 
   25 #define EMAC_SA1B               0x98
   26 #define EMAC_SA1T               0x9C
   27 
   28 #define EMAC_USRIO              0xC0
   29 
   30 #define EMAC_MAN                0x34            /* EMAC PHY Maintenance Register */
   31 #define EMAC_SR         0x08            /* EMAC STatus Register */
   32 #define EMAC_SR_LINK    (1U << 0)       /* Reserved! */
   33 #define EMAC_SR_MDIO    (1U << 1)       /* MDIO pin status */
   34 #define EMAC_SR_IDLE    (1U << 2)       /* IDLE (PHY logic) */
   35 
   36 #define RX_ENABLE               (1 << 2)
   37 #define TX_ENABLE               (1 << 3)
   38 #define MPE_ENABLE              (1 << 4)
   39 
   40 
   41 /* EMAC_MAN */
   42 #define EMAC_MAN_BITS   0x40020000      /* HIGH and CODE bits */
   43 #define EMAC_MAN_READ   (2U << 28)
   44 #define EMAC_MAN_WRITE  (1U << 28)
   45 #define EMAC_MAN_PHYA_BIT 23
   46 #define EMAC_MAN_REGA_BIT 18
   47 #define EMAC_MAN_VALUE_MASK     0xffffU
   48 #define EMAC_MAN_REG_WR(phy, reg, val) \
   49                 (EMAC_MAN_BITS | EMAC_MAN_WRITE | ((phy) << EMAC_MAN_PHYA_BIT) | \
   50                 ((reg) << EMAC_MAN_REGA_BIT) | ((val) & EMAC_MAN_VALUE_MASK))
   51 
   52 #define EMAC_MAN_REG_RD(phy, reg) \
   53                 (EMAC_MAN_BITS | EMAC_MAN_READ | ((phy) << EMAC_MAN_PHYA_BIT) | \
   54                 ((reg) << EMAC_MAN_REGA_BIT))
   55 
   56 #define RCOMP_INTERRUPT         (1 << 1)
   57 #define RXUBR_INTERRUPT         (1 << 2)
   58 #define TUBR_INTERRUPT          (1 << 3)
   59 #define TUND_INTERRUPT          (1 << 4)
   60 #define RLE_INTERRUPT           (1 << 5)
   61 #define TXERR_INTERRUPT         (1 << 6)
   62 #define ROVR_INTERRUPT          (1 << 10)
   63 #define HRESP_INTERRUPT         (1 << 11)
   64 #define TCOMP_INTERRUPT         (1 << 7)
   65 
   66 #define CLEAR_STAT              (1 << 5)
   67 
   68 #define TRANSMIT_START          (1 << 9)
   69 #define TRANSMIT_STOP           (1 << 10)
   70 
   71 /*Transmit status register flags*/
   72 #define TSR_UND                 (1 << 6)
   73 #define TSR_COMP                (1 << 5)
   74 #define TSR_BEX                 (1 << 4)
   75 #define TSR_TGO                 (1 << 3)
   76 #define TSR_RLE                 (1 << 2)
   77 #define TSR_COL                 (1 << 1)
   78 #define TSR_UBR                 (1 << 0)
   79 
   80 #define CFG_SPD         (1 << 0)
   81 #define CFG_FD          (1 << 1)
   82 #define CFG_CAF         (1 << 4)
   83 #define CFG_NBC         (1 << 5)
   84 #define CFG_MTI         (1 << 6)
   85 #define CFG_UNI         (1 << 7)
   86 #define CFG_BIG         (1 << 8)
   87 
   88 #define CFG_CLK_8               (0)
   89 #define CFG_CLK_16              (1)
   90 #define CFG_CLK_32              (2)
   91 #define CFG_CLK_64              (3)
   92 
   93 #define CFG_PAE         (1 << 13)
   94 
   95 #define CFG_RBOF_0      (0 << 14)
   96 #define CFG_RBOF_1      (1 << 14)
   97 #define CFG_RBOF_2      (2 << 14)
   98 #define CFG_RBOF_3      (3 << 14)
   99 
  100 #define CFG_DRFCS       (1 << 17)
  101 
  102 #define USRIO_CLOCK     (1 << 1)
  103 
  104 
  105 
  106 #endif

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