1 /*-
2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: src/sys/arm/at91/uart_dev_at91usart.c,v 1.18 2008/11/25 00:13:26 imp Exp $");
31
32 #include "opt_comconsole.h"
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/cons.h>
39 #include <sys/tty.h>
40 #include <machine/bus.h>
41
42 #include <dev/uart/uart.h>
43 #include <dev/uart/uart_cpu.h>
44 #include <dev/uart/uart_bus.h>
45 #include <arm/at91/at91rm92reg.h>
46 #include <arm/at91/at91_usartreg.h>
47 #include <arm/at91/at91_pdcreg.h>
48
49 #include "uart_if.h"
50
51 #define DEFAULT_RCLK AT91C_MASTER_CLOCK
52 #define USART_BUFFER_SIZE 128
53
54 /*
55 * High-level UART interface.
56 */
57 struct at91_usart_rx {
58 bus_addr_t pa;
59 uint8_t buffer[USART_BUFFER_SIZE];
60 bus_dmamap_t map;
61 };
62
63 struct at91_usart_softc {
64 struct uart_softc base;
65 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
66 bus_dmamap_t tx_map;
67 uint32_t flags;
68 #define HAS_TIMEOUT 1
69 struct at91_usart_rx ping_pong[2];
70 struct at91_usart_rx *ping;
71 struct at91_usart_rx *pong;
72 };
73
74 #define RD4(bas, reg) \
75 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
76 #define WR4(bas, reg, value) \
77 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
78
79 #define SIGCHG(c, i, s, d) \
80 do { \
81 if (c) { \
82 i |= (i & s) ? s : s | d; \
83 } else { \
84 i = (i & s) ? (i & ~s) | d : i; \
85 } \
86 } while (0);
87
88 #define BAUD2DIVISOR(b) \
89 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
90
91 /*
92 * Low-level UART interface.
93 */
94 static int at91_usart_probe(struct uart_bas *bas);
95 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
96 static void at91_usart_term(struct uart_bas *bas);
97 static void at91_usart_putc(struct uart_bas *bas, int);
98 static int at91_usart_rxready(struct uart_bas *bas);
99 static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
100
101 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
102
103 static int
104 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
105 int stopbits, int parity)
106 {
107 uint32_t mr;
108
109 /*
110 * Assume 3-write RS-232 configuration.
111 * XXX Not sure how uart will present the other modes to us, so
112 * XXX they are unimplemented. maybe ioctl?
113 */
114 mr = USART_MR_MODE_NORMAL;
115 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
116
117 /*
118 * Or in the databits requested
119 */
120 if (databits < 9)
121 mr &= ~USART_MR_MODE9;
122 switch (databits) {
123 case 5:
124 mr |= USART_MR_CHRL_5BITS;
125 break;
126 case 6:
127 mr |= USART_MR_CHRL_6BITS;
128 break;
129 case 7:
130 mr |= USART_MR_CHRL_7BITS;
131 break;
132 case 8:
133 mr |= USART_MR_CHRL_8BITS;
134 break;
135 case 9:
136 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
137 break;
138 default:
139 return (EINVAL);
140 }
141
142 /*
143 * Or in the parity
144 */
145 switch (parity) {
146 case UART_PARITY_NONE:
147 mr |= USART_MR_PAR_NONE;
148 break;
149 case UART_PARITY_ODD:
150 mr |= USART_MR_PAR_ODD;
151 break;
152 case UART_PARITY_EVEN:
153 mr |= USART_MR_PAR_EVEN;
154 break;
155 case UART_PARITY_MARK:
156 mr |= USART_MR_PAR_MARK;
157 break;
158 case UART_PARITY_SPACE:
159 mr |= USART_MR_PAR_SPACE;
160 break;
161 default:
162 return (EINVAL);
163 }
164
165 /*
166 * Or in the stop bits. Note: The hardware supports 1.5 stop
167 * bits in async mode, but there's no way to specify that
168 * AFAICT. Instead, rely on the convention documented at
169 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
170 * states that 1.5 stop bits are used for 5 bit bytes and
171 * 2 stop bits only for longer bytes.
172 */
173 if (stopbits == 1)
174 mr |= USART_MR_NBSTOP_1;
175 else if (databits > 5)
176 mr |= USART_MR_NBSTOP_2;
177 else
178 mr |= USART_MR_NBSTOP_1_5;
179
180 /*
181 * We want normal plumbing mode too, none of this fancy
182 * loopback or echo mode.
183 */
184 mr |= USART_MR_CHMODE_NORMAL;
185
186 mr &= ~USART_MR_MSBF; /* lsb first */
187 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
188
189 WR4(bas, USART_MR, mr);
190
191 /*
192 * Set the baud rate
193 */
194 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
195
196 /* XXX Need to take possible synchronous mode into account */
197 return (0);
198 }
199
200 static struct uart_ops at91_usart_ops = {
201 .probe = at91_usart_probe,
202 .init = at91_usart_init,
203 .term = at91_usart_term,
204 .putc = at91_usart_putc,
205 .rxready = at91_usart_rxready,
206 .getc = at91_usart_getc,
207 };
208
209 static int
210 at91_usart_probe(struct uart_bas *bas)
211 {
212 /* We know that this is always here */
213 return (0);
214 }
215
216 /*
217 * Initialize this device for use as a console.
218 */
219 static void
220 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
221 int parity)
222 {
223
224 at91_usart_param(bas, baudrate, databits, stopbits, parity);
225
226 /* Reset the rx and tx buffers and turn on rx and tx */
227 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
228 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
229 WR4(bas, USART_IDR, 0xffffffff);
230 }
231
232 /*
233 * Free resources now that we're no longer the console. This appears to
234 * be never called, and I'm unsure quite what to do if I am called.
235 */
236 static void
237 at91_usart_term(struct uart_bas *bas)
238 {
239 /* XXX */
240 }
241
242 /*
243 * Put a character of console output (so we do it here polling rather than
244 * interrutp driven).
245 */
246 static void
247 at91_usart_putc(struct uart_bas *bas, int c)
248 {
249
250 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
251 continue;
252 WR4(bas, USART_THR, c);
253 }
254
255 /*
256 * Check for a character available.
257 */
258 static int
259 at91_usart_rxready(struct uart_bas *bas)
260 {
261
262 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
263 }
264
265 /*
266 * Block waiting for a character.
267 */
268 static int
269 at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
270 {
271 int c;
272
273 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
274 continue;
275 c = RD4(bas, USART_RHR);
276 c &= 0xff;
277 return (c);
278 }
279
280 static int at91_usart_bus_probe(struct uart_softc *sc);
281 static int at91_usart_bus_attach(struct uart_softc *sc);
282 static int at91_usart_bus_flush(struct uart_softc *, int);
283 static int at91_usart_bus_getsig(struct uart_softc *);
284 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
285 static int at91_usart_bus_ipend(struct uart_softc *);
286 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
287 static int at91_usart_bus_receive(struct uart_softc *);
288 static int at91_usart_bus_setsig(struct uart_softc *, int);
289 static int at91_usart_bus_transmit(struct uart_softc *);
290
291 static kobj_method_t at91_usart_methods[] = {
292 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
293 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
294 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
295 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
296 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
297 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
298 KOBJMETHOD(uart_param, at91_usart_bus_param),
299 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
300 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
301 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
302
303 { 0, 0 }
304 };
305
306 int
307 at91_usart_bus_probe(struct uart_softc *sc)
308 {
309 return (0);
310 }
311
312 #ifndef SKYEYE_WORKAROUNDS
313 static void
314 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
315 {
316 if (error != 0)
317 return;
318 *(bus_addr_t *)arg = segs[0].ds_addr;
319 }
320 #endif
321
322 static int
323 at91_usart_bus_attach(struct uart_softc *sc)
324 {
325 #ifndef SKYEYE_WORKAROUNDS
326 int err;
327 int i;
328 #endif
329 uint32_t cr;
330 struct at91_usart_softc *atsc;
331
332 atsc = (struct at91_usart_softc *)sc;
333
334 /*
335 * See if we have a TIMEOUT bit. We disable all interrupts as
336 * a side effect. Boot loaders may have enabled them. Since
337 * a TIMEOUT interrupt can't happen without other setup, the
338 * apparent race here can't actually happen.
339 */
340 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
341 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
342 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
343 atsc->flags |= HAS_TIMEOUT;
344 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
345
346 sc->sc_txfifosz = USART_BUFFER_SIZE;
347 sc->sc_rxfifosz = USART_BUFFER_SIZE;
348 sc->sc_hwiflow = 0;
349
350 #ifndef SKYEYE_WORKAROUNDS
351 /*
352 * Allocate DMA tags and maps
353 */
354 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
355 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
356 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL,
357 NULL, &atsc->dmatag);
358 if (err != 0)
359 goto errout;
360 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
361 if (err != 0)
362 goto errout;
363 if (atsc->flags & HAS_TIMEOUT) {
364 for (i = 0; i < 2; i++) {
365 err = bus_dmamap_create(atsc->dmatag, 0,
366 &atsc->ping_pong[i].map);
367 if (err != 0)
368 goto errout;
369 err = bus_dmamap_load(atsc->dmatag,
370 atsc->ping_pong[i].map,
371 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
372 at91_getaddr, &atsc->ping_pong[i].pa, 0);
373 if (err != 0)
374 goto errout;
375 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
376 BUS_DMASYNC_PREREAD);
377 }
378 atsc->ping = &atsc->ping_pong[0];
379 atsc->pong = &atsc->ping_pong[1];
380 }
381 #endif
382
383 /*
384 * Prime the pump with the RX buffer. We use two 64 byte bounce
385 * buffers here to avoid data overflow.
386 */
387
388 /* Turn on rx and tx */
389 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
390 WR4(&sc->sc_bas, USART_CR, cr);
391 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
392
393 /*
394 * Setup the PDC to receive data. We use the ping-pong buffers
395 * so that we can more easily bounce between the two and so that
396 * we get an interrupt 1/2 way through the software 'fifo' we have
397 * to avoid overruns.
398 */
399 if (atsc->flags & HAS_TIMEOUT) {
400 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
401 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
402 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
403 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
404 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
405
406 /* Set the receive timeout to be 1.5 character times. */
407 WR4(&sc->sc_bas, USART_RTOR, 12);
408 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
409 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
410 USART_CSR_RXBUFF | USART_CSR_ENDRX);
411 } else {
412 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
413 }
414 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
415 #ifndef SKYEYE_WORKAROUNDS
416 errout:;
417 // XXX bad
418 return (err);
419 #else
420 return (0);
421 #endif
422 }
423
424 static int
425 at91_usart_bus_transmit(struct uart_softc *sc)
426 {
427 #ifndef SKYEYE_WORKAROUNDS
428 bus_addr_t addr;
429 #endif
430 struct at91_usart_softc *atsc;
431
432 atsc = (struct at91_usart_softc *)sc;
433 #ifndef SKYEYE_WORKAROUNDS
434 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
435 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
436 return (EAGAIN);
437 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
438 #endif
439
440 uart_lock(sc->sc_hwmtx);
441 sc->sc_txbusy = 1;
442 #ifndef SKYEYE_WORKAROUNDS
443 /*
444 * Setup the PDC to transfer the data and interrupt us when it
445 * is done. We've already requested the interrupt.
446 */
447 WR4(&sc->sc_bas, PDC_TPR, addr);
448 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
449 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
450 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
451 uart_unlock(sc->sc_hwmtx);
452 #else
453 for (int i = 0; i < sc->sc_txdatasz; i++)
454 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
455 /*
456 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
457 * transfer is done, so simulate it.
458 */
459 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
460 #endif
461 return (0);
462 }
463 static int
464 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
465 {
466 uint32_t new, old, cr;
467 struct uart_bas *bas;
468
469 do {
470 old = sc->sc_hwsig;
471 new = old;
472 if (sig & SER_DDTR)
473 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
474 if (sig & SER_DRTS)
475 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
476 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
477 bas = &sc->sc_bas;
478 uart_lock(sc->sc_hwmtx);
479 cr = 0;
480 if (new & SER_DTR)
481 cr |= USART_CR_DTREN;
482 else
483 cr |= USART_CR_DTRDIS;
484 if (new & SER_RTS)
485 cr |= USART_CR_RTSEN;
486 else
487 cr |= USART_CR_RTSDIS;
488 WR4(bas, USART_CR, cr);
489 uart_unlock(sc->sc_hwmtx);
490 return (0);
491 }
492 static int
493 at91_usart_bus_receive(struct uart_softc *sc)
494 {
495
496 return (0);
497 }
498 static int
499 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
500 int stopbits, int parity)
501 {
502
503 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
504 parity));
505 }
506
507 static __inline void
508 at91_rx_put(struct uart_softc *sc, int key)
509 {
510 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
511 int kdb_brk;
512
513 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
514 if ((kdb_brk = kdb_alt_break(key, &sc->sc_altbrk)) != 0) {
515 switch (kdb_brk) {
516 case KDB_REQ_DEBUGGER:
517 kdb_enter(KDB_WHY_BREAK,
518 "Break sequence on console");
519 break;
520 case KDB_REQ_PANIC:
521 kdb_panic("Panic sequence on console");
522 break;
523 case KDB_REQ_REBOOT:
524 kdb_reboot();
525 break;
526 }
527 }
528 }
529 #endif
530 uart_rx_put(sc, key);
531 }
532
533 static int
534 at91_usart_bus_ipend(struct uart_softc *sc)
535 {
536 int csr = RD4(&sc->sc_bas, USART_CSR);
537 int ipend = 0, i, len;
538 struct at91_usart_softc *atsc;
539 struct at91_usart_rx *p;
540
541 atsc = (struct at91_usart_softc *)sc;
542 if (csr & USART_CSR_ENDTX) {
543 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
544 BUS_DMASYNC_POSTWRITE);
545 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
546 }
547 uart_lock(sc->sc_hwmtx);
548 if (csr & USART_CSR_TXRDY) {
549 if (sc->sc_txbusy)
550 ipend |= SER_INT_TXIDLE;
551 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
552 }
553 if (csr & USART_CSR_ENDTX) {
554 if (sc->sc_txbusy)
555 ipend |= SER_INT_TXIDLE;
556 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
557 }
558
559 /*
560 * Due to the contraints of the DMA engine present in the
561 * atmel chip, I can't just say I have a rx interrupt pending
562 * and do all the work elsewhere. I need to look at the CSR
563 * bits right now and do things based on them to avoid races.
564 */
565 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
566 // Have a buffer overflow. Copy all data from both
567 // ping and pong. Insert overflow character. Reset
568 // ping and pong and re-enable the PDC to receive
569 // characters again.
570 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
571 BUS_DMASYNC_POSTREAD);
572 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
573 BUS_DMASYNC_POSTREAD);
574 for (i = 0; i < sc->sc_rxfifosz; i++)
575 at91_rx_put(sc, atsc->ping->buffer[i]);
576 for (i = 0; i < sc->sc_rxfifosz; i++)
577 at91_rx_put(sc, atsc->pong->buffer[i]);
578 uart_rx_put(sc, UART_STAT_OVERRUN);
579 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
580 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
581 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
582 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
583 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
584 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
585 ipend |= SER_INT_RXREADY;
586 }
587 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
588 // Shuffle data from 'ping' of ping pong buffer, but
589 // leave current 'pong' in place, as it has become the
590 // new 'ping'. We need to copy data and setup the old
591 // 'ping' as the new 'pong' when we're done.
592 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
593 BUS_DMASYNC_POSTREAD);
594 for (i = 0; i < sc->sc_rxfifosz; i++)
595 at91_rx_put(sc, atsc->ping->buffer[i]);
596 p = atsc->ping;
597 atsc->ping = atsc->pong;
598 atsc->pong = p;
599 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
600 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
601 ipend |= SER_INT_RXREADY;
602 }
603 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
604 // We have one partial buffer. We need to stop the
605 // PDC, get the number of characters left and from
606 // that compute number of valid characters. We then
607 // need to reset ping and pong and reenable the PDC.
608 // Not sure if there's a race here at fast baud rates
609 // we need to worry about.
610 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
611 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
612 BUS_DMASYNC_POSTREAD);
613 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
614 for (i = 0; i < len; i++)
615 at91_rx_put(sc, atsc->ping->buffer[i]);
616 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
617 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
618 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
619 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
620 ipend |= SER_INT_RXREADY;
621 }
622 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
623 // We have another charater in a device that doesn't support
624 // timeouts, so we do it one character at a time.
625 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
626 ipend |= SER_INT_RXREADY;
627 }
628
629 if (csr & USART_CSR_RXBRK) {
630 unsigned int cr = USART_CR_RSTSTA;
631
632 ipend |= SER_INT_BREAK;
633 WR4(&sc->sc_bas, USART_CR, cr);
634 }
635 uart_unlock(sc->sc_hwmtx);
636 return (ipend);
637 }
638 static int
639 at91_usart_bus_flush(struct uart_softc *sc, int what)
640 {
641 return (0);
642 }
643
644 static int
645 at91_usart_bus_getsig(struct uart_softc *sc)
646 {
647 uint32_t new, sig;
648 uint8_t csr;
649
650 uart_lock(sc->sc_hwmtx);
651 csr = RD4(&sc->sc_bas, USART_CSR);
652 sig = 0;
653 if (csr & USART_CSR_CTS)
654 sig |= SER_CTS;
655 if (csr & USART_CSR_DCD)
656 sig |= SER_DCD;
657 if (csr & USART_CSR_DSR)
658 sig |= SER_DSR;
659 if (csr & USART_CSR_RI)
660 sig |= SER_RI;
661 new = sig & ~SER_MASK_DELTA;
662 sc->sc_hwsig = new;
663 uart_unlock(sc->sc_hwmtx);
664 return (sig);
665 }
666
667 static int
668 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
669 {
670 switch (request) {
671 case UART_IOCTL_BREAK:
672 case UART_IOCTL_IFLOW:
673 case UART_IOCTL_OFLOW:
674 break;
675 case UART_IOCTL_BAUD:
676 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
677 return (0);
678 }
679 return (EINVAL);
680 }
681
682 struct uart_class at91_usart_class = {
683 "at91_usart",
684 at91_usart_methods,
685 sizeof(struct at91_usart_softc),
686 .uc_ops = &at91_usart_ops,
687 .uc_range = 8,
688 .uc_rclk = DEFAULT_RCLK
689 };
690 Cache object: ebfe665e2393bdfc2ca60594dfe587d2
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