1 /*-
2 * Copyright (c) 2005 M. Warner Losh
3 * Copyright (c) 2005 Olivier Houchard
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/cons.h>
37 #include <sys/tty.h>
38 #include <machine/bus.h>
39
40 #include <dev/uart/uart.h>
41 #include <dev/uart/uart_cpu.h>
42 #include <dev/uart/uart_bus.h>
43 #include <arm/at91/at91rm92reg.h>
44 #include <arm/at91/at91_usartreg.h>
45 #include <arm/at91/at91_pdcreg.h>
46 #include <arm/at91/at91var.h>
47
48 #include "uart_if.h"
49
50 #define DEFAULT_RCLK at91_master_clock
51 #define USART_BUFFER_SIZE 128
52
53 /*
54 * High-level UART interface.
55 */
56 struct at91_usart_rx {
57 bus_addr_t pa;
58 uint8_t buffer[USART_BUFFER_SIZE];
59 bus_dmamap_t map;
60 };
61
62 struct at91_usart_softc {
63 struct uart_softc base;
64 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
65 bus_dmamap_t tx_map;
66 uint32_t flags;
67 #define HAS_TIMEOUT 1
68 struct at91_usart_rx ping_pong[2];
69 struct at91_usart_rx *ping;
70 struct at91_usart_rx *pong;
71 };
72
73 #define RD4(bas, reg) \
74 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
75 #define WR4(bas, reg, value) \
76 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
77
78 #define SIGCHG(c, i, s, d) \
79 do { \
80 if (c) { \
81 i |= (i & s) ? s : s | d; \
82 } else { \
83 i = (i & s) ? (i & ~s) | d : i; \
84 } \
85 } while (0);
86
87 #define BAUD2DIVISOR(b) \
88 ((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
89
90 /*
91 * Low-level UART interface.
92 */
93 static int at91_usart_probe(struct uart_bas *bas);
94 static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
95 static void at91_usart_term(struct uart_bas *bas);
96 static void at91_usart_putc(struct uart_bas *bas, int);
97 static int at91_usart_rxready(struct uart_bas *bas);
98 static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
99
100 extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
101
102 static int
103 at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
104 int stopbits, int parity)
105 {
106 uint32_t mr;
107
108 /*
109 * Assume 3-write RS-232 configuration.
110 * XXX Not sure how uart will present the other modes to us, so
111 * XXX they are unimplemented. maybe ioctl?
112 */
113 mr = USART_MR_MODE_NORMAL;
114 mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
115
116 /*
117 * Or in the databits requested
118 */
119 if (databits < 9)
120 mr &= ~USART_MR_MODE9;
121 switch (databits) {
122 case 5:
123 mr |= USART_MR_CHRL_5BITS;
124 break;
125 case 6:
126 mr |= USART_MR_CHRL_6BITS;
127 break;
128 case 7:
129 mr |= USART_MR_CHRL_7BITS;
130 break;
131 case 8:
132 mr |= USART_MR_CHRL_8BITS;
133 break;
134 case 9:
135 mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
136 break;
137 default:
138 return (EINVAL);
139 }
140
141 /*
142 * Or in the parity
143 */
144 switch (parity) {
145 case UART_PARITY_NONE:
146 mr |= USART_MR_PAR_NONE;
147 break;
148 case UART_PARITY_ODD:
149 mr |= USART_MR_PAR_ODD;
150 break;
151 case UART_PARITY_EVEN:
152 mr |= USART_MR_PAR_EVEN;
153 break;
154 case UART_PARITY_MARK:
155 mr |= USART_MR_PAR_MARK;
156 break;
157 case UART_PARITY_SPACE:
158 mr |= USART_MR_PAR_SPACE;
159 break;
160 default:
161 return (EINVAL);
162 }
163
164 /*
165 * Or in the stop bits. Note: The hardware supports 1.5 stop
166 * bits in async mode, but there's no way to specify that
167 * AFAICT. Instead, rely on the convention documented at
168 * http://www.lammertbies.nl/comm/info/RS-232_specs.html which
169 * states that 1.5 stop bits are used for 5 bit bytes and
170 * 2 stop bits only for longer bytes.
171 */
172 if (stopbits == 1)
173 mr |= USART_MR_NBSTOP_1;
174 else if (databits > 5)
175 mr |= USART_MR_NBSTOP_2;
176 else
177 mr |= USART_MR_NBSTOP_1_5;
178
179 /*
180 * We want normal plumbing mode too, none of this fancy
181 * loopback or echo mode.
182 */
183 mr |= USART_MR_CHMODE_NORMAL;
184
185 mr &= ~USART_MR_MSBF; /* lsb first */
186 mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
187
188 WR4(bas, USART_MR, mr);
189
190 /*
191 * Set the baud rate
192 */
193 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
194
195 /* XXX Need to take possible synchronous mode into account */
196 return (0);
197 }
198
199 static struct uart_ops at91_usart_ops = {
200 .probe = at91_usart_probe,
201 .init = at91_usart_init,
202 .term = at91_usart_term,
203 .putc = at91_usart_putc,
204 .rxready = at91_usart_rxready,
205 .getc = at91_usart_getc,
206 };
207
208 static int
209 at91_usart_probe(struct uart_bas *bas)
210 {
211 /* We know that this is always here */
212 return (0);
213 }
214
215 /*
216 * Initialize this device for use as a console.
217 */
218 static void
219 at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
220 int parity)
221 {
222
223 at91_usart_param(bas, baudrate, databits, stopbits, parity);
224
225 /* Reset the rx and tx buffers and turn on rx and tx */
226 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
227 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
228 WR4(bas, USART_IDR, 0xffffffff);
229 }
230
231 /*
232 * Free resources now that we're no longer the console. This appears to
233 * be never called, and I'm unsure quite what to do if I am called.
234 */
235 static void
236 at91_usart_term(struct uart_bas *bas)
237 {
238 /* XXX */
239 }
240
241 /*
242 * Put a character of console output (so we do it here polling rather than
243 * interrutp driven).
244 */
245 static void
246 at91_usart_putc(struct uart_bas *bas, int c)
247 {
248
249 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
250 continue;
251 WR4(bas, USART_THR, c);
252 }
253
254 /*
255 * Check for a character available.
256 */
257 static int
258 at91_usart_rxready(struct uart_bas *bas)
259 {
260
261 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
262 }
263
264 /*
265 * Block waiting for a character.
266 */
267 static int
268 at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
269 {
270 int c;
271
272 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
273 continue;
274 c = RD4(bas, USART_RHR);
275 c &= 0xff;
276 return (c);
277 }
278
279 static int at91_usart_bus_probe(struct uart_softc *sc);
280 static int at91_usart_bus_attach(struct uart_softc *sc);
281 static int at91_usart_bus_flush(struct uart_softc *, int);
282 static int at91_usart_bus_getsig(struct uart_softc *);
283 static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
284 static int at91_usart_bus_ipend(struct uart_softc *);
285 static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
286 static int at91_usart_bus_receive(struct uart_softc *);
287 static int at91_usart_bus_setsig(struct uart_softc *, int);
288 static int at91_usart_bus_transmit(struct uart_softc *);
289
290 static kobj_method_t at91_usart_methods[] = {
291 KOBJMETHOD(uart_probe, at91_usart_bus_probe),
292 KOBJMETHOD(uart_attach, at91_usart_bus_attach),
293 KOBJMETHOD(uart_flush, at91_usart_bus_flush),
294 KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
295 KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
296 KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
297 KOBJMETHOD(uart_param, at91_usart_bus_param),
298 KOBJMETHOD(uart_receive, at91_usart_bus_receive),
299 KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
300 KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
301
302 { 0, 0 }
303 };
304
305 int
306 at91_usart_bus_probe(struct uart_softc *sc)
307 {
308
309 sc->sc_txfifosz = USART_BUFFER_SIZE;
310 sc->sc_rxfifosz = USART_BUFFER_SIZE;
311 sc->sc_hwiflow = 0;
312 return (0);
313 }
314
315 #ifndef SKYEYE_WORKAROUNDS
316 static void
317 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
318 {
319 if (error != 0)
320 return;
321 *(bus_addr_t *)arg = segs[0].ds_addr;
322 }
323 #endif
324
325 static int
326 at91_usart_bus_attach(struct uart_softc *sc)
327 {
328 #ifndef SKYEYE_WORKAROUNDS
329 int err;
330 int i;
331 #endif
332 uint32_t cr;
333 struct at91_usart_softc *atsc;
334
335 atsc = (struct at91_usart_softc *)sc;
336
337 /*
338 * See if we have a TIMEOUT bit. We disable all interrupts as
339 * a side effect. Boot loaders may have enabled them. Since
340 * a TIMEOUT interrupt can't happen without other setup, the
341 * apparent race here can't actually happen.
342 */
343 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
344 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
345 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
346 atsc->flags |= HAS_TIMEOUT;
347 WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
348
349 #ifndef SKYEYE_WORKAROUNDS
350 /*
351 * Allocate DMA tags and maps
352 */
353 err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
354 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
355 USART_BUFFER_SIZE, 1, USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL,
356 NULL, &atsc->dmatag);
357 if (err != 0)
358 goto errout;
359 err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
360 if (err != 0)
361 goto errout;
362 if (atsc->flags & HAS_TIMEOUT) {
363 for (i = 0; i < 2; i++) {
364 err = bus_dmamap_create(atsc->dmatag, 0,
365 &atsc->ping_pong[i].map);
366 if (err != 0)
367 goto errout;
368 err = bus_dmamap_load(atsc->dmatag,
369 atsc->ping_pong[i].map,
370 atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
371 at91_getaddr, &atsc->ping_pong[i].pa, 0);
372 if (err != 0)
373 goto errout;
374 bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
375 BUS_DMASYNC_PREREAD);
376 }
377 atsc->ping = &atsc->ping_pong[0];
378 atsc->pong = &atsc->ping_pong[1];
379 }
380 #endif
381
382 /*
383 * Prime the pump with the RX buffer. We use two 64 byte bounce
384 * buffers here to avoid data overflow.
385 */
386
387 /* Turn on rx and tx */
388 cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
389 WR4(&sc->sc_bas, USART_CR, cr);
390 WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
391
392 /*
393 * Setup the PDC to receive data. We use the ping-pong buffers
394 * so that we can more easily bounce between the two and so that
395 * we get an interrupt 1/2 way through the software 'fifo' we have
396 * to avoid overruns.
397 */
398 if (atsc->flags & HAS_TIMEOUT) {
399 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
400 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
401 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
402 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
403 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
404
405 /* Set the receive timeout to be 1.5 character times. */
406 WR4(&sc->sc_bas, USART_RTOR, 12);
407 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
408 WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
409 USART_CSR_RXBUFF | USART_CSR_ENDRX);
410 } else {
411 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
412 }
413 WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
414 #ifndef SKYEYE_WORKAROUNDS
415 errout:
416 // XXX bad
417 return (err);
418 #else
419 return (0);
420 #endif
421 }
422
423 static int
424 at91_usart_bus_transmit(struct uart_softc *sc)
425 {
426 #ifndef SKYEYE_WORKAROUNDS
427 bus_addr_t addr;
428 #endif
429 struct at91_usart_softc *atsc;
430
431 atsc = (struct at91_usart_softc *)sc;
432 #ifndef SKYEYE_WORKAROUNDS
433 if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
434 sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
435 return (EAGAIN);
436 bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
437 #endif
438
439 uart_lock(sc->sc_hwmtx);
440 sc->sc_txbusy = 1;
441 #ifndef SKYEYE_WORKAROUNDS
442 /*
443 * Setup the PDC to transfer the data and interrupt us when it
444 * is done. We've already requested the interrupt.
445 */
446 WR4(&sc->sc_bas, PDC_TPR, addr);
447 WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
448 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
449 WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
450 uart_unlock(sc->sc_hwmtx);
451 #else
452 for (int i = 0; i < sc->sc_txdatasz; i++)
453 at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
454 /*
455 * XXX: Gross hack : Skyeye doesn't raise an interrupt once the
456 * transfer is done, so simulate it.
457 */
458 WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
459 #endif
460 return (0);
461 }
462 static int
463 at91_usart_bus_setsig(struct uart_softc *sc, int sig)
464 {
465 uint32_t new, old, cr;
466 struct uart_bas *bas;
467
468 do {
469 old = sc->sc_hwsig;
470 new = old;
471 if (sig & SER_DDTR)
472 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
473 if (sig & SER_DRTS)
474 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
475 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
476 bas = &sc->sc_bas;
477 uart_lock(sc->sc_hwmtx);
478 cr = 0;
479 if (new & SER_DTR)
480 cr |= USART_CR_DTREN;
481 else
482 cr |= USART_CR_DTRDIS;
483 if (new & SER_RTS)
484 cr |= USART_CR_RTSEN;
485 else
486 cr |= USART_CR_RTSDIS;
487 WR4(bas, USART_CR, cr);
488 uart_unlock(sc->sc_hwmtx);
489 return (0);
490 }
491 static int
492 at91_usart_bus_receive(struct uart_softc *sc)
493 {
494
495 return (0);
496 }
497 static int
498 at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
499 int stopbits, int parity)
500 {
501
502 return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
503 parity));
504 }
505
506 static __inline void
507 at91_rx_put(struct uart_softc *sc, int key)
508 {
509
510 #if defined(KDB)
511 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
512 kdb_alt_break(key, &sc->sc_altbrk);
513 #endif
514 uart_rx_put(sc, key);
515 }
516
517 static int
518 at91_usart_bus_ipend(struct uart_softc *sc)
519 {
520 int csr = RD4(&sc->sc_bas, USART_CSR);
521 int ipend = 0, i, len;
522 struct at91_usart_softc *atsc;
523 struct at91_usart_rx *p;
524
525 atsc = (struct at91_usart_softc *)sc;
526 if (csr & USART_CSR_ENDTX) {
527 bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
528 BUS_DMASYNC_POSTWRITE);
529 bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
530 }
531 uart_lock(sc->sc_hwmtx);
532 if (csr & USART_CSR_TXRDY) {
533 if (sc->sc_txbusy)
534 ipend |= SER_INT_TXIDLE;
535 WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
536 }
537 if (csr & USART_CSR_ENDTX) {
538 if (sc->sc_txbusy)
539 ipend |= SER_INT_TXIDLE;
540 WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
541 }
542
543 /*
544 * Due to the contraints of the DMA engine present in the
545 * atmel chip, I can't just say I have a rx interrupt pending
546 * and do all the work elsewhere. I need to look at the CSR
547 * bits right now and do things based on them to avoid races.
548 */
549 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
550 // Have a buffer overflow. Copy all data from both
551 // ping and pong. Insert overflow character. Reset
552 // ping and pong and re-enable the PDC to receive
553 // characters again.
554 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
555 BUS_DMASYNC_POSTREAD);
556 bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
557 BUS_DMASYNC_POSTREAD);
558 for (i = 0; i < sc->sc_rxfifosz; i++)
559 at91_rx_put(sc, atsc->ping->buffer[i]);
560 for (i = 0; i < sc->sc_rxfifosz; i++)
561 at91_rx_put(sc, atsc->pong->buffer[i]);
562 uart_rx_put(sc, UART_STAT_OVERRUN);
563 csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
564 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
565 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
566 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
567 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
568 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
569 ipend |= SER_INT_RXREADY;
570 }
571 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
572 // Shuffle data from 'ping' of ping pong buffer, but
573 // leave current 'pong' in place, as it has become the
574 // new 'ping'. We need to copy data and setup the old
575 // 'ping' as the new 'pong' when we're done.
576 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
577 BUS_DMASYNC_POSTREAD);
578 for (i = 0; i < sc->sc_rxfifosz; i++)
579 at91_rx_put(sc, atsc->ping->buffer[i]);
580 p = atsc->ping;
581 atsc->ping = atsc->pong;
582 atsc->pong = p;
583 WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
584 WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
585 ipend |= SER_INT_RXREADY;
586 }
587 if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
588 // We have one partial buffer. We need to stop the
589 // PDC, get the number of characters left and from
590 // that compute number of valid characters. We then
591 // need to reset ping and pong and reenable the PDC.
592 // Not sure if there's a race here at fast baud rates
593 // we need to worry about.
594 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
595 bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
596 BUS_DMASYNC_POSTREAD);
597 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
598 for (i = 0; i < len; i++)
599 at91_rx_put(sc, atsc->ping->buffer[i]);
600 WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
601 WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
602 WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
603 WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
604 ipend |= SER_INT_RXREADY;
605 }
606 if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
607 // We have another charater in a device that doesn't support
608 // timeouts, so we do it one character at a time.
609 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
610 ipend |= SER_INT_RXREADY;
611 }
612
613 if (csr & USART_CSR_RXBRK) {
614 unsigned int cr = USART_CR_RSTSTA;
615
616 ipend |= SER_INT_BREAK;
617 WR4(&sc->sc_bas, USART_CR, cr);
618 }
619 uart_unlock(sc->sc_hwmtx);
620 return (ipend);
621 }
622 static int
623 at91_usart_bus_flush(struct uart_softc *sc, int what)
624 {
625 return (0);
626 }
627
628 static int
629 at91_usart_bus_getsig(struct uart_softc *sc)
630 {
631 uint32_t new, sig;
632 uint8_t csr;
633
634 uart_lock(sc->sc_hwmtx);
635 csr = RD4(&sc->sc_bas, USART_CSR);
636 sig = 0;
637 if (csr & USART_CSR_CTS)
638 sig |= SER_CTS;
639 if (csr & USART_CSR_DCD)
640 sig |= SER_DCD;
641 if (csr & USART_CSR_DSR)
642 sig |= SER_DSR;
643 if (csr & USART_CSR_RI)
644 sig |= SER_RI;
645 new = sig & ~SER_MASK_DELTA;
646 sc->sc_hwsig = new;
647 uart_unlock(sc->sc_hwmtx);
648 return (sig);
649 }
650
651 static int
652 at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
653 {
654 switch (request) {
655 case UART_IOCTL_BREAK:
656 case UART_IOCTL_IFLOW:
657 case UART_IOCTL_OFLOW:
658 break;
659 case UART_IOCTL_BAUD:
660 WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
661 return (0);
662 }
663 return (EINVAL);
664 }
665
666 struct uart_class at91_usart_class = {
667 "at91_usart",
668 at91_usart_methods,
669 sizeof(struct at91_usart_softc),
670 .uc_ops = &at91_usart_ops,
671 .uc_range = 8
672 };
Cache object: 5ad9dddec17ed625b806f3faf79dcbd5
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