Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/broadcom/bcm2835/bcm2835_bsc.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Tsubai Masanari. 5 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 6 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org> 7 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC. 37 * 38 * This controller can only perform complete transfers, it does not provide 39 * low-level control over sending start/repeat-start/stop sequences on the bus. 40 * In addition, bugs in the silicon make it somewhat difficult to perform a 41 * repeat-start, and limit the repeat-start to a read following a write on 42 * the same slave device. (The i2c protocol allows a repeat start to change 43 * direction or not, and change slave address or not at any time.) 44 * 45 * The repeat-start bug and workaround are described in a problem report at 46 * https://github.com/raspberrypi/linux/issues/254 with the crucial part being 47 * in a comment block from a fragment of a GPU i2c driver, containing this: 48 * 49 * ----------------------------------------------------------------------------- 50 * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count 51 * - in the IDLE state if start is set. 52 * - 53 * - We want to generate a ReSTART not a STOP at the end of the TX phase. In 54 * - order to do that we must ensure the state machine goes RACK1 -> RACK2 -> 55 * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1). 56 * - 57 * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have 58 * - already set, ready to be sampled: 59 * - READ ; rw_bit <= I2CC bit 0 -- must be "read" 60 * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP 61 * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount 62 * - 63 * - The plan to do this is: 64 * - 1. Start the sub-address write, but don't let it finish 65 * - (keep xfer_count > 0) 66 * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence 67 * - 3. Let TX finish (write the rest of the data) 68 * - 4. Read back data as it arrives 69 * ----------------------------------------------------------------------------- 70 * 71 * The transfer function below scans the list of messages passed to it, looking 72 * for a read following a write to the same slave. When it finds that, it 73 * starts the write without prefilling the tx fifo, which holds xfer_count>0, 74 * then presets the direction, length, and start command for the following read, 75 * as described above. Then the tx fifo is filled and the rest of the transfer 76 * proceeds as normal, with the controller automatically supplying a 77 * repeat-start on the bus when the write operation finishes. 78 * 79 * XXX I suspect the controller may be able to do a repeat-start on any 80 * write->read or write->write transition, even when the slave addresses differ. 81 * It's unclear whether the slave address can be prestaged along with the 82 * direction and length while the write xfer_count is being held at zero. In 83 * fact, if it can't do this, then it couldn't be used to read EDID data. 84 */ 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/kernel.h> 89 #include <sys/lock.h> 90 #include <sys/module.h> 91 #include <sys/mutex.h> 92 #include <sys/bus.h> 93 #include <machine/resource.h> 94 #include <machine/bus.h> 95 #include <sys/rman.h> 96 #include <sys/sysctl.h> 97 98 #include <dev/iicbus/iicbus.h> 99 #include <dev/iicbus/iiconf.h> 100 #include <dev/ofw/ofw_bus.h> 101 #include <dev/ofw/ofw_bus_subr.h> 102 103 #include <arm/broadcom/bcm2835/bcm2835_bscreg.h> 104 #include <arm/broadcom/bcm2835/bcm2835_bscvar.h> 105 106 #include "iicbus_if.h" 107 108 static struct ofw_compat_data compat_data[] = { 109 {"broadcom,bcm2835-bsc", 1}, 110 {"brcm,bcm2708-i2c", 1}, 111 {"brcm,bcm2835-i2c", 1}, 112 {NULL, 0} 113 }; 114 115 #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ 116 if ((lvl) <= (sc)->sc_debug) \ 117 device_printf((sc)->sc_dev, fmt, ##args) 118 119 #define DEBUGF(sc, lvl, fmt, args...) \ 120 if ((lvl) <= (sc)->sc_debug) \ 121 printf(fmt, ##args) 122 123 static void bcm_bsc_intr(void *); 124 static int bcm_bsc_detach(device_t); 125 126 static void 127 bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, 128 uint32_t value) 129 { 130 uint32_t reg; 131 132 mtx_assert(&sc->sc_mtx, MA_OWNED); 133 reg = BCM_BSC_READ(sc, off); 134 reg &= ~mask; 135 reg |= value; 136 BCM_BSC_WRITE(sc, off, reg); 137 } 138 139 static int 140 bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) 141 { 142 struct bcm_bsc_softc *sc; 143 uint32_t clk; 144 145 sc = (struct bcm_bsc_softc *)arg1; 146 BCM_BSC_LOCK(sc); 147 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 148 BCM_BSC_UNLOCK(sc); 149 clk &= 0xffff; 150 if (clk == 0) 151 clk = 32768; 152 clk = BCM_BSC_CORE_CLK / clk; 153 154 return (sysctl_handle_int(oidp, &clk, 0, req)); 155 } 156 157 static int 158 bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) 159 { 160 struct bcm_bsc_softc *sc; 161 uint32_t clkt; 162 int error; 163 164 sc = (struct bcm_bsc_softc *)arg1; 165 166 BCM_BSC_LOCK(sc); 167 clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); 168 BCM_BSC_UNLOCK(sc); 169 clkt &= 0xffff; 170 error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); 171 if (error != 0 || req->newptr == NULL) 172 return (error); 173 174 BCM_BSC_LOCK(sc); 175 BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); 176 BCM_BSC_UNLOCK(sc); 177 178 return (0); 179 } 180 181 static int 182 bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) 183 { 184 struct bcm_bsc_softc *sc; 185 uint32_t clk, reg; 186 int error; 187 188 sc = (struct bcm_bsc_softc *)arg1; 189 190 BCM_BSC_LOCK(sc); 191 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 192 BCM_BSC_UNLOCK(sc); 193 reg >>= 16; 194 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 195 if (error != 0 || req->newptr == NULL) 196 return (error); 197 198 BCM_BSC_LOCK(sc); 199 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 200 clk = BCM_BSC_CORE_CLK / clk; 201 if (reg > clk / 2) 202 reg = clk / 2 - 1; 203 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); 204 BCM_BSC_UNLOCK(sc); 205 206 return (0); 207 } 208 209 static int 210 bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) 211 { 212 struct bcm_bsc_softc *sc; 213 uint32_t clk, reg; 214 int error; 215 216 sc = (struct bcm_bsc_softc *)arg1; 217 218 BCM_BSC_LOCK(sc); 219 reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); 220 BCM_BSC_UNLOCK(sc); 221 reg &= 0xffff; 222 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 223 if (error != 0 || req->newptr == NULL) 224 return (error); 225 226 BCM_BSC_LOCK(sc); 227 clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); 228 clk = BCM_BSC_CORE_CLK / clk; 229 if (reg > clk / 2) 230 reg = clk / 2 - 1; 231 bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); 232 BCM_BSC_UNLOCK(sc); 233 234 return (0); 235 } 236 237 static void 238 bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) 239 { 240 struct sysctl_ctx_list *ctx; 241 struct sysctl_oid *tree_node; 242 struct sysctl_oid_list *tree; 243 244 /* 245 * Add system sysctl tree/handlers. 246 */ 247 ctx = device_get_sysctl_ctx(sc->sc_dev); 248 tree_node = device_get_sysctl_tree(sc->sc_dev); 249 tree = SYSCTL_CHILDREN(tree_node); 250 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", 251 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 252 sc, sizeof(*sc), 253 bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); 254 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", 255 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 256 sc, sizeof(*sc), 257 bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); 258 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", 259 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 260 sc, sizeof(*sc), 261 bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); 262 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", 263 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 264 sc, sizeof(*sc), 265 bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); 266 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug", 267 CTLFLAG_RWTUN, &sc->sc_debug, 0, 268 "Enable debug; 1=reads/writes, 2=add starts/stops"); 269 } 270 271 static void 272 bcm_bsc_reset(struct bcm_bsc_softc *sc) 273 { 274 275 /* Enable the BSC Controller, disable interrupts. */ 276 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); 277 /* Clear pending interrupts. */ 278 BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | 279 BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); 280 /* Clear the FIFO. */ 281 bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, 282 BCM_BSC_CTRL_CLEAR0); 283 } 284 285 static int 286 bcm_bsc_probe(device_t dev) 287 { 288 289 if (!ofw_bus_status_okay(dev)) 290 return (ENXIO); 291 292 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 293 return (ENXIO); 294 295 device_set_desc(dev, "BCM2708/2835 BSC controller"); 296 297 return (BUS_PROBE_DEFAULT); 298 } 299 300 static int 301 bcm_bsc_attach(device_t dev) 302 { 303 struct bcm_bsc_softc *sc; 304 int rid; 305 306 sc = device_get_softc(dev); 307 sc->sc_dev = dev; 308 309 rid = 0; 310 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 311 RF_ACTIVE); 312 if (!sc->sc_mem_res) { 313 device_printf(dev, "cannot allocate memory window\n"); 314 return (ENXIO); 315 } 316 317 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 318 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 319 320 rid = 0; 321 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 322 RF_ACTIVE | RF_SHAREABLE); 323 if (!sc->sc_irq_res) { 324 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 325 device_printf(dev, "cannot allocate interrupt\n"); 326 return (ENXIO); 327 } 328 329 /* Hook up our interrupt handler. */ 330 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 331 NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { 332 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 333 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 334 device_printf(dev, "cannot setup the interrupt handler\n"); 335 return (ENXIO); 336 } 337 338 mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); 339 340 bcm_bsc_sysctl_init(sc); 341 342 /* Enable the BSC controller. Flush the FIFO. */ 343 BCM_BSC_LOCK(sc); 344 bcm_bsc_reset(sc); 345 BCM_BSC_UNLOCK(sc); 346 347 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 348 if (sc->sc_iicbus == NULL) { 349 bcm_bsc_detach(dev); 350 return (ENXIO); 351 } 352 353 /* Probe and attach the iicbus when interrupts are available. */ 354 return (bus_delayed_attach_children(dev)); 355 } 356 357 static int 358 bcm_bsc_detach(device_t dev) 359 { 360 struct bcm_bsc_softc *sc; 361 362 bus_generic_detach(dev); 363 364 sc = device_get_softc(dev); 365 if (sc->sc_iicbus != NULL) 366 device_delete_child(dev, sc->sc_iicbus); 367 mtx_destroy(&sc->sc_mtx); 368 if (sc->sc_intrhand) 369 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 370 if (sc->sc_irq_res) 371 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 372 if (sc->sc_mem_res) 373 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 374 375 return (0); 376 } 377 378 static void 379 bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc) 380 { 381 uint32_t status; 382 383 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */ 384 do { 385 if (sc->sc_resid == 0) { 386 sc->sc_data = sc->sc_curmsg->buf; 387 sc->sc_dlen = sc->sc_curmsg->len; 388 sc->sc_resid = sc->sc_dlen; 389 ++sc->sc_curmsg; 390 } 391 do { 392 *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA); 393 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 394 ++sc->sc_data; 395 --sc->sc_resid; 396 --sc->sc_totlen; 397 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 398 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)); 399 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD)); 400 } 401 402 static void 403 bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc) 404 { 405 uint32_t status; 406 407 /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */ 408 do { 409 if (sc->sc_resid == 0) { 410 sc->sc_data = sc->sc_curmsg->buf; 411 sc->sc_dlen = sc->sc_curmsg->len; 412 sc->sc_resid = sc->sc_dlen; 413 ++sc->sc_curmsg; 414 } 415 do { 416 BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); 417 DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); 418 ++sc->sc_data; 419 --sc->sc_resid; 420 --sc->sc_totlen; 421 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 422 } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)); 423 /* 424 * If a repeat-start was pending and we just hit the end of a tx 425 * buffer, see if it's also the end of the writes that preceeded 426 * the repeat-start. If so, log the repeat-start and the start 427 * of the following read, and return because we're not writing 428 * anymore (and TXD will be true because there's room to write 429 * in the fifo). 430 */ 431 if (sc->sc_replen > 0 && sc->sc_resid == 0) { 432 sc->sc_replen -= sc->sc_dlen; 433 if (sc->sc_replen == 0) { 434 DEBUGF(sc, 1, " err=0\n"); 435 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", 436 sc->sc_curmsg->slave | 0x01); 437 DEVICE_DEBUGF(sc, 1, 438 "read 0x%02x len %d: ", 439 sc->sc_curmsg->slave | 0x01, 440 sc->sc_totlen); 441 sc->sc_flags |= BCM_I2C_READ; 442 return; 443 } 444 } 445 } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD)); 446 } 447 448 static void 449 bcm_bsc_intr(void *arg) 450 { 451 struct bcm_bsc_softc *sc; 452 uint32_t status; 453 454 sc = (struct bcm_bsc_softc *)arg; 455 456 BCM_BSC_LOCK(sc); 457 458 /* The I2C interrupt is shared among all the BSC controllers. */ 459 if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { 460 BCM_BSC_UNLOCK(sc); 461 return; 462 } 463 464 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 465 DEBUGF(sc, 4, " <intrstatus=0x%08x> ", status); 466 467 /* RXD and DONE can assert together, empty fifo before checking done. */ 468 if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD)) 469 bcm_bsc_empty_rx_fifo(sc); 470 471 /* Check for completion. */ 472 if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) { 473 sc->sc_flags |= BCM_I2C_DONE; 474 if (status & BCM_BSC_STATUS_ERRBITS) 475 sc->sc_flags |= BCM_I2C_ERROR; 476 /* Disable interrupts. */ 477 bcm_bsc_reset(sc); 478 wakeup(sc); 479 } else if (!(sc->sc_flags & BCM_I2C_READ)) { 480 /* 481 * Don't check for TXD until after determining whether the 482 * transfer is complete; TXD will be asserted along with ERR or 483 * DONE if there is room in the fifo. 484 */ 485 if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0) 486 bcm_bsc_fill_tx_fifo(sc); 487 } 488 489 BCM_BSC_UNLOCK(sc); 490 } 491 492 static int 493 bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 494 { 495 struct bcm_bsc_softc *sc; 496 struct iic_msg *endmsgs, *nxtmsg; 497 uint32_t readctl, status; 498 int err; 499 uint16_t curlen; 500 uint8_t curisread, curslave, nxtisread, nxtslave; 501 502 sc = device_get_softc(dev); 503 BCM_BSC_LOCK(sc); 504 505 /* If the controller is busy wait until it is available. */ 506 while (sc->sc_flags & BCM_I2C_BUSY) 507 mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); 508 509 /* Now we have control over the BSC controller. */ 510 sc->sc_flags = BCM_I2C_BUSY; 511 512 DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs); 513 514 /* Clear the FIFO and the pending interrupts. */ 515 bcm_bsc_reset(sc); 516 517 /* 518 * Perform all the transfers requested in the array of msgs. Note that 519 * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance 520 * sc->sc_curmsg through the array of messages, as the data from each 521 * message is fully consumed, but it is this loop that notices when we 522 * have no more messages to process. 523 */ 524 err = 0; 525 sc->sc_resid = 0; 526 sc->sc_curmsg = msgs; 527 endmsgs = &msgs[nmsgs]; 528 while (sc->sc_curmsg < endmsgs) { 529 readctl = 0; 530 curslave = sc->sc_curmsg->slave >> 1; 531 curisread = sc->sc_curmsg->flags & IIC_M_RD; 532 sc->sc_replen = 0; 533 sc->sc_totlen = sc->sc_curmsg->len; 534 /* 535 * Scan for scatter/gather IO (same slave and direction) or 536 * repeat-start (read following write for the same slave). 537 */ 538 for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) { 539 nxtslave = nxtmsg->slave >> 1; 540 if (curslave == nxtslave) { 541 nxtisread = nxtmsg->flags & IIC_M_RD; 542 if (curisread == nxtisread) { 543 /* 544 * Same slave and direction, this 545 * message will be part of the same 546 * transfer as the previous one. 547 */ 548 sc->sc_totlen += nxtmsg->len; 549 continue; 550 } else if (curisread == IIC_M_WR) { 551 /* 552 * Read after write to same slave means 553 * repeat-start, remember how many bytes 554 * come before the repeat-start, switch 555 * the direction to IIC_M_RD, and gather 556 * up following reads to the same slave. 557 */ 558 curisread = IIC_M_RD; 559 sc->sc_replen = sc->sc_totlen; 560 sc->sc_totlen += nxtmsg->len; 561 continue; 562 } 563 } 564 break; 565 } 566 567 /* 568 * curslave and curisread temporaries from above may refer to 569 * the after-repstart msg, reset them to reflect sc_curmsg. 570 */ 571 curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0; 572 curslave = sc->sc_curmsg->slave | curisread; 573 574 /* Write the slave address. */ 575 BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1); 576 577 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave); 578 579 /* 580 * Either set up read length and direction variables for a 581 * simple transfer or get the hardware started on the first 582 * piece of a transfer that involves a repeat-start and set up 583 * the read length and direction vars for the second piece. 584 */ 585 if (sc->sc_replen == 0) { 586 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 587 (curisread) ? "read" : "write", curslave, 588 sc->sc_totlen); 589 curlen = sc->sc_totlen; 590 if (curisread) { 591 readctl = BCM_BSC_CTRL_READ; 592 sc->sc_flags |= BCM_I2C_READ; 593 } else { 594 readctl = 0; 595 sc->sc_flags &= ~BCM_I2C_READ; 596 } 597 } else { 598 DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", 599 (curisread) ? "read" : "write", curslave, 600 sc->sc_replen); 601 602 /* 603 * Start the write transfer with an empty fifo and wait 604 * for the 'transfer active' status bit to light up; 605 * that indicates that the hardware has latched the 606 * direction and length for the write, and we can safely 607 * reload those registers and issue the start for the 608 * following read; interrupts are not enabled here. 609 */ 610 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen); 611 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | 612 BCM_BSC_CTRL_ST); 613 do { 614 status = BCM_BSC_READ(sc, BCM_BSC_STATUS); 615 if (status & BCM_BSC_STATUS_ERR) { 616 /* no ACK on slave addr */ 617 err = EIO; 618 goto xfer_done; 619 } 620 } while ((status & BCM_BSC_STATUS_TA) == 0); 621 /* 622 * Set curlen and readctl for the repeat-start read that 623 * we need to set up below, but set sc_flags to write, 624 * because that is the operation in progress right now. 625 */ 626 curlen = sc->sc_totlen - sc->sc_replen; 627 readctl = BCM_BSC_CTRL_READ; 628 sc->sc_flags &= ~BCM_I2C_READ; 629 } 630 631 /* 632 * Start the transfer with interrupts enabled, then if doing a 633 * write, fill the tx fifo. Not prefilling the fifo until after 634 * this start command is the key workaround for making 635 * repeat-start work, and it's harmless to do it in this order 636 * for a regular write too. 637 */ 638 BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen); 639 BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN | 640 BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL); 641 642 if (!(sc->sc_curmsg->flags & IIC_M_RD)) { 643 bcm_bsc_fill_tx_fifo(sc); 644 } 645 646 /* Wait for the transaction to complete. */ 647 while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) { 648 err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz); 649 } 650 /* Check for errors. */ 651 if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) 652 err = EIO; 653 xfer_done: 654 DEBUGF(sc, 1, " err=%d\n", err); 655 DEVICE_DEBUGF(sc, 2, "stop\n"); 656 if (err != 0) 657 break; 658 } 659 660 /* Disable interrupts, clean fifo, etc. */ 661 bcm_bsc_reset(sc); 662 663 /* Clean the controller flags. */ 664 sc->sc_flags = 0; 665 666 /* Wake up the threads waiting for bus. */ 667 wakeup(dev); 668 669 BCM_BSC_UNLOCK(sc); 670 671 return (err); 672 } 673 674 static int 675 bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 676 { 677 struct bcm_bsc_softc *sc; 678 uint32_t busfreq; 679 680 sc = device_get_softc(dev); 681 BCM_BSC_LOCK(sc); 682 bcm_bsc_reset(sc); 683 if (sc->sc_iicbus == NULL) 684 busfreq = 100000; 685 else 686 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 687 BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); 688 BCM_BSC_UNLOCK(sc); 689 690 return (IIC_ENOADDR); 691 } 692 693 static phandle_t 694 bcm_bsc_get_node(device_t bus, device_t dev) 695 { 696 697 /* We only have one child, the I2C bus, which needs our own node. */ 698 return (ofw_bus_get_node(bus)); 699 } 700 701 static device_method_t bcm_bsc_methods[] = { 702 /* Device interface */ 703 DEVMETHOD(device_probe, bcm_bsc_probe), 704 DEVMETHOD(device_attach, bcm_bsc_attach), 705 DEVMETHOD(device_detach, bcm_bsc_detach), 706 707 /* iicbus interface */ 708 DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), 709 DEVMETHOD(iicbus_callback, iicbus_null_callback), 710 DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), 711 712 /* ofw_bus interface */ 713 DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), 714 715 DEVMETHOD_END 716 }; 717 718 static driver_t bcm_bsc_driver = { 719 "iichb", 720 bcm_bsc_methods, 721 sizeof(struct bcm_bsc_softc), 722 }; 723 724 DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, 0, 0); 725 DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, 0, 0);
Cache object: d2b485f5b2e435e01772f6158f90ad9a
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