Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/broadcom/bcm2835/bcm2835_dma.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Daisuke Aoyama <aoyama@peach.ne.jp> 5 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@bluezbox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/resource.h> 43 #include <sys/rman.h> 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <vm/vm.h> 50 #include <vm/pmap.h> 51 #include <machine/bus.h> 52 53 #include "bcm2835_dma.h" 54 #include "bcm2835_vcbus.h" 55 56 #define MAX_REG 9 57 58 /* private flags */ 59 #define BCM_DMA_CH_USED 0x00000001 60 #define BCM_DMA_CH_FREE 0x40000000 61 #define BCM_DMA_CH_UNMAP 0x80000000 62 63 /* Register Map (4.2.1.2) */ 64 #define BCM_DMA_CS(n) (0x100*(n) + 0x00) 65 #define CS_ACTIVE (1 << 0) 66 #define CS_END (1 << 1) 67 #define CS_INT (1 << 2) 68 #define CS_DREQ (1 << 3) 69 #define CS_ISPAUSED (1 << 4) 70 #define CS_ISHELD (1 << 5) 71 #define CS_ISWAIT (1 << 6) 72 #define CS_ERR (1 << 8) 73 #define CS_WAITWRT (1 << 28) 74 #define CS_DISDBG (1 << 29) 75 #define CS_ABORT (1 << 30) 76 #define CS_RESET (1U << 31) 77 #define BCM_DMA_CBADDR(n) (0x100*(n) + 0x04) 78 #define BCM_DMA_INFO(n) (0x100*(n) + 0x08) 79 #define INFO_INT_EN (1 << 0) 80 #define INFO_TDMODE (1 << 1) 81 #define INFO_WAIT_RESP (1 << 3) 82 #define INFO_D_INC (1 << 4) 83 #define INFO_D_WIDTH (1 << 5) 84 #define INFO_D_DREQ (1 << 6) 85 #define INFO_S_INC (1 << 8) 86 #define INFO_S_WIDTH (1 << 9) 87 #define INFO_S_DREQ (1 << 10) 88 #define INFO_WAITS_SHIFT (21) 89 #define INFO_PERMAP_SHIFT (16) 90 #define INFO_PERMAP_MASK (0x1f << INFO_PERMAP_SHIFT) 91 92 #define BCM_DMA_SRC(n) (0x100*(n) + 0x0C) 93 #define BCM_DMA_DST(n) (0x100*(n) + 0x10) 94 #define BCM_DMA_LEN(n) (0x100*(n) + 0x14) 95 #define BCM_DMA_STRIDE(n) (0x100*(n) + 0x18) 96 #define BCM_DMA_CBNEXT(n) (0x100*(n) + 0x1C) 97 #define BCM_DMA_DEBUG(n) (0x100*(n) + 0x20) 98 #define DEBUG_ERROR_MASK (7) 99 100 #define BCM_DMA_INT_STATUS 0xfe0 101 #define BCM_DMA_ENABLE 0xff0 102 103 /* relative offset from BCM_VC_DMA0_BASE (p.39) */ 104 #define BCM_DMA_CH(n) (0x100*(n)) 105 106 /* channels used by GPU */ 107 #define BCM_DMA_CH_BULK 0 108 #define BCM_DMA_CH_FAST1 2 109 #define BCM_DMA_CH_FAST2 3 110 111 #define BCM_DMA_CH_GPU_MASK ((1 << BCM_DMA_CH_BULK) | \ 112 (1 << BCM_DMA_CH_FAST1) | \ 113 (1 << BCM_DMA_CH_FAST2)) 114 115 /* DMA Control Block - 256bit aligned (p.40) */ 116 struct bcm_dma_cb { 117 uint32_t info; /* Transfer Information */ 118 uint32_t src; /* Source Address */ 119 uint32_t dst; /* Destination Address */ 120 uint32_t len; /* Transfer Length */ 121 uint32_t stride; /* 2D Mode Stride */ 122 uint32_t next; /* Next Control Block Address */ 123 uint32_t rsvd1; /* Reserved */ 124 uint32_t rsvd2; /* Reserved */ 125 }; 126 127 #ifdef DEBUG 128 static void bcm_dma_cb_dump(struct bcm_dma_cb *cb); 129 static void bcm_dma_reg_dump(int ch); 130 #endif 131 132 /* DMA channel private info */ 133 struct bcm_dma_ch { 134 int ch; 135 uint32_t flags; 136 struct bcm_dma_cb * cb; 137 uint32_t vc_cb; 138 bus_dmamap_t dma_map; 139 void (*intr_func)(int, void *); 140 void * intr_arg; 141 }; 142 143 struct bcm_dma_softc { 144 device_t sc_dev; 145 struct mtx sc_mtx; 146 struct resource * sc_mem; 147 struct resource * sc_irq[BCM_DMA_CH_MAX]; 148 void * sc_intrhand[BCM_DMA_CH_MAX]; 149 struct bcm_dma_ch sc_dma_ch[BCM_DMA_CH_MAX]; 150 bus_dma_tag_t sc_dma_tag; 151 }; 152 153 static struct bcm_dma_softc *bcm_dma_sc = NULL; 154 static uint32_t bcm_dma_channel_mask; 155 156 static struct ofw_compat_data compat_data[] = { 157 {"broadcom,bcm2835-dma", 1}, 158 {"brcm,bcm2835-dma", 1}, 159 {NULL, 0} 160 }; 161 162 static void 163 bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 164 int nseg, int err) 165 { 166 bus_addr_t *addr; 167 168 if (err) 169 return; 170 171 addr = (bus_addr_t*)arg; 172 *addr = ARMC_TO_VCBUS(segs[0].ds_addr); 173 } 174 175 static void 176 bcm_dma_reset(device_t dev, int ch) 177 { 178 struct bcm_dma_softc *sc = device_get_softc(dev); 179 struct bcm_dma_cb *cb; 180 uint32_t cs; 181 int count; 182 183 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 184 return; 185 186 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 187 188 if (cs & CS_ACTIVE) { 189 /* pause current task */ 190 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 0); 191 192 count = 1000; 193 do { 194 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch)); 195 } while (!(cs & CS_ISPAUSED) && (count-- > 0)); 196 197 if (!(cs & CS_ISPAUSED)) { 198 device_printf(dev, 199 "Can't abort DMA transfer at channel %d\n", ch); 200 } 201 202 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 203 204 /* Complete everything, clear interrupt */ 205 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), 206 CS_ABORT | CS_INT | CS_END| CS_ACTIVE); 207 } 208 209 /* clear control blocks */ 210 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 0); 211 bus_write_4(sc->sc_mem, BCM_DMA_CBNEXT(ch), 0); 212 213 /* Reset control block */ 214 cb = sc->sc_dma_ch[ch].cb; 215 bzero(cb, sizeof(*cb)); 216 cb->info = INFO_WAIT_RESP; 217 } 218 219 static int 220 bcm_dma_init(device_t dev) 221 { 222 struct bcm_dma_softc *sc = device_get_softc(dev); 223 uint32_t reg; 224 struct bcm_dma_ch *ch; 225 void *cb_virt; 226 vm_paddr_t cb_phys; 227 int err; 228 int i; 229 230 /* 231 * Only channels set in bcm_dma_channel_mask can be controlled by us. 232 * The others are out of our control as well as the corresponding bits 233 * in both BCM_DMA_ENABLE and BCM_DMA_INT_STATUS global registers. As 234 * these registers are RW ones, there is no safe way how to write only 235 * the bits which can be controlled by us. 236 * 237 * Fortunately, after reset, all channels are enabled in BCM_DMA_ENABLE 238 * register and all statuses are cleared in BCM_DMA_INT_STATUS one. 239 * Not touching these registers is a trade off between correct 240 * initialization which does not count on anything and not messing up 241 * something we have no control over. 242 */ 243 reg = bus_read_4(sc->sc_mem, BCM_DMA_ENABLE); 244 if ((reg & bcm_dma_channel_mask) != bcm_dma_channel_mask) 245 device_printf(dev, "channels are not enabled\n"); 246 reg = bus_read_4(sc->sc_mem, BCM_DMA_INT_STATUS); 247 if ((reg & bcm_dma_channel_mask) != 0) 248 device_printf(dev, "statuses are not cleared\n"); 249 250 /* 251 * Allocate DMA chunks control blocks based on p.40 of the peripheral 252 * spec - control block should be 32-bit aligned. The DMA controller 253 * has a full 32-bit register dedicated to this address, so we do not 254 * need to bother with the per-SoC peripheral restrictions. 255 */ 256 err = bus_dma_tag_create(bus_get_dma_tag(dev), 257 1, 0, BUS_SPACE_MAXADDR_32BIT, 258 BUS_SPACE_MAXADDR, NULL, NULL, 259 sizeof(struct bcm_dma_cb), 1, 260 sizeof(struct bcm_dma_cb), 261 BUS_DMA_ALLOCNOW, NULL, NULL, 262 &sc->sc_dma_tag); 263 264 if (err) { 265 device_printf(dev, "failed allocate DMA tag\n"); 266 return (err); 267 } 268 269 /* setup initial settings */ 270 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 271 ch = &sc->sc_dma_ch[i]; 272 273 bzero(ch, sizeof(struct bcm_dma_ch)); 274 ch->ch = i; 275 ch->flags = BCM_DMA_CH_UNMAP; 276 277 if ((bcm_dma_channel_mask & (1 << i)) == 0) 278 continue; 279 280 err = bus_dmamem_alloc(sc->sc_dma_tag, &cb_virt, 281 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 282 &ch->dma_map); 283 if (err) { 284 device_printf(dev, "cannot allocate DMA memory\n"); 285 break; 286 } 287 288 /* 289 * Least alignment for busdma-allocated stuff is cache 290 * line size, so just make sure nothing stupid happened 291 * and we got properly aligned address 292 */ 293 if ((uintptr_t)cb_virt & 0x1f) { 294 device_printf(dev, 295 "DMA address is not 32-bytes aligned: %p\n", 296 (void*)cb_virt); 297 break; 298 } 299 300 err = bus_dmamap_load(sc->sc_dma_tag, ch->dma_map, cb_virt, 301 sizeof(struct bcm_dma_cb), bcm_dmamap_cb, &cb_phys, 302 BUS_DMA_WAITOK); 303 if (err) { 304 device_printf(dev, "cannot load DMA memory\n"); 305 break; 306 } 307 308 ch->cb = cb_virt; 309 ch->vc_cb = cb_phys; 310 ch->flags = BCM_DMA_CH_FREE; 311 ch->cb->info = INFO_WAIT_RESP; 312 313 /* reset DMA engine */ 314 bus_write_4(sc->sc_mem, BCM_DMA_CS(i), CS_RESET); 315 } 316 317 return (0); 318 } 319 320 /* 321 * Allocate DMA channel for further use, returns channel # or 322 * BCM_DMA_CH_INVALID 323 */ 324 int 325 bcm_dma_allocate(int req_ch) 326 { 327 struct bcm_dma_softc *sc = bcm_dma_sc; 328 int ch = BCM_DMA_CH_INVALID; 329 int i; 330 331 if (req_ch >= BCM_DMA_CH_MAX) 332 return (BCM_DMA_CH_INVALID); 333 334 /* Auto(req_ch < 0) or CH specified */ 335 mtx_lock(&sc->sc_mtx); 336 337 if (req_ch < 0) { 338 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 339 if (sc->sc_dma_ch[i].flags & BCM_DMA_CH_FREE) { 340 ch = i; 341 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 342 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 343 break; 344 } 345 } 346 } 347 else { 348 if (sc->sc_dma_ch[req_ch].flags & BCM_DMA_CH_FREE) { 349 ch = req_ch; 350 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_FREE; 351 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_USED; 352 } 353 } 354 355 mtx_unlock(&sc->sc_mtx); 356 return (ch); 357 } 358 359 /* 360 * Frees allocated channel. Returns 0 on success, -1 otherwise 361 */ 362 int 363 bcm_dma_free(int ch) 364 { 365 struct bcm_dma_softc *sc = bcm_dma_sc; 366 367 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 368 return (-1); 369 370 mtx_lock(&sc->sc_mtx); 371 if (sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED) { 372 sc->sc_dma_ch[ch].flags |= BCM_DMA_CH_FREE; 373 sc->sc_dma_ch[ch].flags &= ~BCM_DMA_CH_USED; 374 sc->sc_dma_ch[ch].intr_func = NULL; 375 sc->sc_dma_ch[ch].intr_arg = NULL; 376 377 /* reset DMA engine */ 378 bcm_dma_reset(sc->sc_dev, ch); 379 } 380 381 mtx_unlock(&sc->sc_mtx); 382 return (0); 383 } 384 385 /* 386 * Assign handler function for channel interrupt 387 * Returns 0 on success, -1 otherwise 388 */ 389 int 390 bcm_dma_setup_intr(int ch, void (*func)(int, void *), void *arg) 391 { 392 struct bcm_dma_softc *sc = bcm_dma_sc; 393 struct bcm_dma_cb *cb; 394 395 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 396 return (-1); 397 398 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 399 return (-1); 400 401 sc->sc_dma_ch[ch].intr_func = func; 402 sc->sc_dma_ch[ch].intr_arg = arg; 403 cb = sc->sc_dma_ch[ch].cb; 404 cb->info |= INFO_INT_EN; 405 406 return (0); 407 } 408 409 /* 410 * Setup DMA source parameters 411 * ch - channel number 412 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 413 * source is physical memory 414 * inc_addr - BCM_DMA_INC_ADDR if source address 415 * should be increased after each access or 416 * BCM_DMA_SAME_ADDR if address should remain 417 * the same 418 * width - size of read operation, BCM_DMA_32BIT 419 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 420 * 421 * Returns 0 on success, -1 otherwise 422 */ 423 int 424 bcm_dma_setup_src(int ch, int dreq, int inc_addr, int width) 425 { 426 struct bcm_dma_softc *sc = bcm_dma_sc; 427 uint32_t info; 428 429 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 430 return (-1); 431 432 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 433 return (-1); 434 435 info = sc->sc_dma_ch[ch].cb->info; 436 info &= ~INFO_PERMAP_MASK; 437 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 438 439 if (dreq) 440 info |= INFO_S_DREQ; 441 else 442 info &= ~INFO_S_DREQ; 443 444 if (width == BCM_DMA_128BIT) 445 info |= INFO_S_WIDTH; 446 else 447 info &= ~INFO_S_WIDTH; 448 449 if (inc_addr == BCM_DMA_INC_ADDR) 450 info |= INFO_S_INC; 451 else 452 info &= ~INFO_S_INC; 453 454 sc->sc_dma_ch[ch].cb->info = info; 455 456 return (0); 457 } 458 459 /* 460 * Setup DMA destination parameters 461 * ch - channel number 462 * dreq - hardware DREQ # or BCM_DMA_DREQ_NONE if 463 * destination is physical memory 464 * inc_addr - BCM_DMA_INC_ADDR if source address 465 * should be increased after each access or 466 * BCM_DMA_SAME_ADDR if address should remain 467 * the same 468 * width - size of write operation, BCM_DMA_32BIT 469 * for 32bit bursts, BCM_DMA_128BIT for 128 bits 470 * 471 * Returns 0 on success, -1 otherwise 472 */ 473 int 474 bcm_dma_setup_dst(int ch, int dreq, int inc_addr, int width) 475 { 476 struct bcm_dma_softc *sc = bcm_dma_sc; 477 uint32_t info; 478 479 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 480 return (-1); 481 482 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 483 return (-1); 484 485 info = sc->sc_dma_ch[ch].cb->info; 486 info &= ~INFO_PERMAP_MASK; 487 info |= (dreq << INFO_PERMAP_SHIFT) & INFO_PERMAP_MASK; 488 489 if (dreq) 490 info |= INFO_D_DREQ; 491 else 492 info &= ~INFO_D_DREQ; 493 494 if (width == BCM_DMA_128BIT) 495 info |= INFO_D_WIDTH; 496 else 497 info &= ~INFO_D_WIDTH; 498 499 if (inc_addr == BCM_DMA_INC_ADDR) 500 info |= INFO_D_INC; 501 else 502 info &= ~INFO_D_INC; 503 504 sc->sc_dma_ch[ch].cb->info = info; 505 506 return (0); 507 } 508 509 #ifdef DEBUG 510 void 511 bcm_dma_cb_dump(struct bcm_dma_cb *cb) 512 { 513 514 printf("DMA CB "); 515 printf("INFO: %8.8x ", cb->info); 516 printf("SRC: %8.8x ", cb->src); 517 printf("DST: %8.8x ", cb->dst); 518 printf("LEN: %8.8x ", cb->len); 519 printf("\n"); 520 printf("STRIDE: %8.8x ", cb->stride); 521 printf("NEXT: %8.8x ", cb->next); 522 printf("RSVD1: %8.8x ", cb->rsvd1); 523 printf("RSVD2: %8.8x ", cb->rsvd2); 524 printf("\n"); 525 } 526 527 void 528 bcm_dma_reg_dump(int ch) 529 { 530 struct bcm_dma_softc *sc = bcm_dma_sc; 531 int i; 532 uint32_t reg; 533 534 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 535 return; 536 537 printf("DMA%d: ", ch); 538 for (i = 0; i < MAX_REG; i++) { 539 reg = bus_read_4(sc->sc_mem, BCM_DMA_CH(ch) + i*4); 540 printf("%8.8x ", reg); 541 } 542 printf("\n"); 543 } 544 #endif 545 546 /* 547 * Start DMA transaction 548 * ch - channel number 549 * src, dst - source and destination address in 550 * ARM physical memory address space. 551 * len - amount of bytes to be transferred 552 * 553 * Returns 0 on success, -1 otherwise 554 */ 555 int 556 bcm_dma_start(int ch, vm_paddr_t src, vm_paddr_t dst, int len) 557 { 558 struct bcm_dma_softc *sc = bcm_dma_sc; 559 struct bcm_dma_cb *cb; 560 561 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 562 return (-1); 563 564 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 565 return (-1); 566 567 cb = sc->sc_dma_ch[ch].cb; 568 cb->src = ARMC_TO_VCBUS(src); 569 cb->dst = ARMC_TO_VCBUS(dst); 570 571 cb->len = len; 572 573 bus_dmamap_sync(sc->sc_dma_tag, 574 sc->sc_dma_ch[ch].dma_map, BUS_DMASYNC_PREWRITE); 575 576 bus_write_4(sc->sc_mem, BCM_DMA_CBADDR(ch), 577 sc->sc_dma_ch[ch].vc_cb); 578 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch), CS_ACTIVE); 579 580 #ifdef DEBUG 581 bcm_dma_cb_dump(sc->sc_dma_ch[ch].cb); 582 bcm_dma_reg_dump(ch); 583 #endif 584 585 return (0); 586 } 587 588 /* 589 * Get length requested for DMA transaction 590 * ch - channel number 591 * 592 * Returns size of transaction, 0 if channel is invalid 593 */ 594 uint32_t 595 bcm_dma_length(int ch) 596 { 597 struct bcm_dma_softc *sc = bcm_dma_sc; 598 struct bcm_dma_cb *cb; 599 600 if (ch < 0 || ch >= BCM_DMA_CH_MAX) 601 return (0); 602 603 if (!(sc->sc_dma_ch[ch].flags & BCM_DMA_CH_USED)) 604 return (0); 605 606 cb = sc->sc_dma_ch[ch].cb; 607 608 return (cb->len); 609 } 610 611 static void 612 bcm_dma_intr(void *arg) 613 { 614 struct bcm_dma_softc *sc = bcm_dma_sc; 615 struct bcm_dma_ch *ch = (struct bcm_dma_ch *)arg; 616 uint32_t cs, debug; 617 618 /* my interrupt? */ 619 cs = bus_read_4(sc->sc_mem, BCM_DMA_CS(ch->ch)); 620 621 /* 622 * Is it an active channel? Our diagnostics could be better here, but 623 * it's not necessarily an easy task to resolve a rid/resource to an 624 * actual irq number. We'd want to do this to set a flag indicating 625 * whether the irq is shared or not, so we know to complain. 626 */ 627 if (!(ch->flags & BCM_DMA_CH_USED)) 628 return; 629 630 /* Again, we can't complain here. The same logic applies. */ 631 if (!(cs & (CS_INT | CS_ERR))) 632 return; 633 634 if (cs & CS_ERR) { 635 debug = bus_read_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch)); 636 device_printf(sc->sc_dev, "DMA error %d on CH%d\n", 637 debug & DEBUG_ERROR_MASK, ch->ch); 638 bus_write_4(sc->sc_mem, BCM_DMA_DEBUG(ch->ch), 639 debug & DEBUG_ERROR_MASK); 640 bcm_dma_reset(sc->sc_dev, ch->ch); 641 } 642 643 if (cs & CS_INT) { 644 /* acknowledge interrupt */ 645 bus_write_4(sc->sc_mem, BCM_DMA_CS(ch->ch), 646 CS_INT | CS_END); 647 648 /* Prepare for possible access to len field */ 649 bus_dmamap_sync(sc->sc_dma_tag, ch->dma_map, 650 BUS_DMASYNC_POSTWRITE); 651 652 /* save callback function and argument */ 653 if (ch->intr_func) 654 ch->intr_func(ch->ch, ch->intr_arg); 655 } 656 } 657 658 static int 659 bcm_dma_probe(device_t dev) 660 { 661 662 if (!ofw_bus_status_okay(dev)) 663 return (ENXIO); 664 665 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 666 return (ENXIO); 667 668 device_set_desc(dev, "BCM2835 DMA Controller"); 669 return (BUS_PROBE_DEFAULT); 670 } 671 672 static int 673 bcm_dma_attach(device_t dev) 674 { 675 struct bcm_dma_softc *sc = device_get_softc(dev); 676 phandle_t node; 677 int rid, err = 0; 678 int i; 679 680 sc->sc_dev = dev; 681 682 if (bcm_dma_sc) 683 return (ENXIO); 684 685 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 686 sc->sc_irq[i] = NULL; 687 sc->sc_intrhand[i] = NULL; 688 } 689 690 /* Get DMA channel mask. */ 691 node = ofw_bus_get_node(sc->sc_dev); 692 if (OF_getencprop(node, "brcm,dma-channel-mask", &bcm_dma_channel_mask, 693 sizeof(bcm_dma_channel_mask)) == -1 && 694 OF_getencprop(node, "broadcom,channels", &bcm_dma_channel_mask, 695 sizeof(bcm_dma_channel_mask)) == -1) { 696 device_printf(dev, "could not get channel mask property\n"); 697 return (ENXIO); 698 } 699 700 /* Mask out channels used by GPU. */ 701 bcm_dma_channel_mask &= ~BCM_DMA_CH_GPU_MASK; 702 703 /* DMA0 - DMA14 */ 704 rid = 0; 705 sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 706 if (sc->sc_mem == NULL) { 707 device_printf(dev, "could not allocate memory resource\n"); 708 return (ENXIO); 709 } 710 711 /* IRQ DMA0 - DMA11 XXX NOT USE DMA12(spurious?) */ 712 for (rid = 0; rid < BCM_DMA_CH_MAX; rid++) { 713 if ((bcm_dma_channel_mask & (1 << rid)) == 0) 714 continue; 715 716 sc->sc_irq[rid] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 717 RF_ACTIVE | RF_SHAREABLE); 718 if (sc->sc_irq[rid] == NULL) { 719 device_printf(dev, "cannot allocate interrupt\n"); 720 err = ENXIO; 721 goto fail; 722 } 723 if (bus_setup_intr(dev, sc->sc_irq[rid], INTR_TYPE_MISC | INTR_MPSAFE, 724 NULL, bcm_dma_intr, &sc->sc_dma_ch[rid], 725 &sc->sc_intrhand[rid])) { 726 device_printf(dev, "cannot setup interrupt handler\n"); 727 err = ENXIO; 728 goto fail; 729 } 730 } 731 732 mtx_init(&sc->sc_mtx, "bcmdma", "bcmdma", MTX_DEF); 733 bcm_dma_sc = sc; 734 735 err = bcm_dma_init(dev); 736 if (err) 737 goto fail; 738 739 return (err); 740 741 fail: 742 if (sc->sc_mem) 743 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem); 744 745 for (i = 0; i < BCM_DMA_CH_MAX; i++) { 746 if (sc->sc_intrhand[i]) 747 bus_teardown_intr(dev, sc->sc_irq[i], sc->sc_intrhand[i]); 748 if (sc->sc_irq[i]) 749 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq[i]); 750 } 751 752 return (err); 753 } 754 755 static device_method_t bcm_dma_methods[] = { 756 DEVMETHOD(device_probe, bcm_dma_probe), 757 DEVMETHOD(device_attach, bcm_dma_attach), 758 { 0, 0 } 759 }; 760 761 static driver_t bcm_dma_driver = { 762 "bcm_dma", 763 bcm_dma_methods, 764 sizeof(struct bcm_dma_softc), 765 }; 766 767 DRIVER_MODULE(bcm_dma, simplebus, bcm_dma_driver, 0, 0); 768 MODULE_VERSION(bcm_dma, 1);
Cache object: 46feefc9ed27e37ed19c55d7a3488dc9
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