Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/freescale/imx/imx51_ipuv3_fbd.c
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1 /*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Oleksandr Rybalko 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/11.0/sys/arm/freescale/imx/imx51_ipuv3_fbd.c 281085 2015-04-04 21:34:26Z andrew $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bio.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/kernel.h> 41 #include <sys/kthread.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/queue.h> 47 #include <sys/resource.h> 48 #include <sys/rman.h> 49 #include <sys/time.h> 50 #include <sys/timetc.h> 51 #include <sys/fbio.h> 52 #include <sys/consio.h> 53 #include <sys/eventhandler.h> 54 55 #include <sys/kdb.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/cpufunc.h> 60 #include <machine/resource.h> 61 #include <machine/frame.h> 62 #include <machine/intr.h> 63 64 #include <dev/fdt/fdt_common.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <dev/vt/vt.h> 69 #include <dev/vt/colors/vt_termcolors.h> 70 71 #include <arm/freescale/imx/imx51_ccmvar.h> 72 73 #include <arm/freescale/imx/imx51_ipuv3reg.h> 74 75 #include "fb_if.h" 76 77 #define IMX51_IPU_HSP_CLOCK 665000000 78 79 struct ipu3sc_softc { 80 device_t dev; 81 device_t sc_fbd; /* fbd child */ 82 struct fb_info sc_info; 83 84 bus_space_tag_t iot; 85 bus_space_handle_t ioh; 86 bus_space_handle_t cm_ioh; 87 bus_space_handle_t dp_ioh; 88 bus_space_handle_t di0_ioh; 89 bus_space_handle_t di1_ioh; 90 bus_space_handle_t dctmpl_ioh; 91 bus_space_handle_t dc_ioh; 92 bus_space_handle_t dmfc_ioh; 93 bus_space_handle_t idmac_ioh; 94 bus_space_handle_t cpmem_ioh; 95 }; 96 97 static struct ipu3sc_softc *ipu3sc_softc; 98 99 #define IPUV3_READ(ipuv3, module, reg) \ 100 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) 101 #define IPUV3_WRITE(ipuv3, module, reg, val) \ 102 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) 103 104 #define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40) 105 #define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20) 106 #define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000) 107 #define IMX_IPU_DP0 0 108 #define IMX_IPU_DP1 1 109 #define CPMEM_CHANNEL(_dp, _ch, _w) \ 110 (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \ 111 CPMEM_WORD_OFFSET(_w)) 112 #define CPMEM_OFFSET(_dp, _ch, _w, _o) \ 113 (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o)) 114 115 static int ipu3_fb_probe(device_t); 116 static int ipu3_fb_attach(device_t); 117 118 static void 119 ipu3_fb_init(struct ipu3sc_softc *sc) 120 { 121 uint64_t w0sh96; 122 uint32_t w1sh96; 123 124 /* FW W0[137:125] - 96 = [41:29] */ 125 /* FH W0[149:138] - 96 = [53:42] */ 126 w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16)); 127 w0sh96 <<= 32; 128 w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12)); 129 130 sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1; 131 sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1; 132 133 /* SLY W1[115:102] - 96 = [19:6] */ 134 w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12)); 135 sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1; 136 137 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 138 sc->sc_info.fb_stride); 139 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 140 141 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 142 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 143 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 144 145 /* DP1 + config_ch_23 + word_2 */ 146 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0), 147 (((uint32_t)sc->sc_info.fb_pbase >> 3) | 148 (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff); 149 150 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4), 151 (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff); 152 153 /* XXX: fetch or set it from/to IPU. */ 154 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride / 155 sc->sc_info.fb_width * 8; 156 } 157 158 /* Use own color map, because of different RGB offset. */ 159 static int 160 ipu3_fb_init_cmap(uint32_t *cmap, int bytespp) 161 { 162 163 switch (bytespp) { 164 case 8: 165 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 166 0x7, 5, 0x7, 2, 0x3, 0)); 167 case 15: 168 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 169 0x1f, 10, 0x1f, 5, 0x1f, 0)); 170 case 16: 171 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 172 0x1f, 11, 0x3f, 5, 0x1f, 0)); 173 case 24: 174 case 32: /* Ignore alpha. */ 175 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB, 176 0xff, 0, 0xff, 8, 0xff, 16)); 177 default: 178 return (1); 179 } 180 } 181 182 static int 183 ipu3_fb_probe(device_t dev) 184 { 185 186 if (!ofw_bus_status_okay(dev)) 187 return (ENXIO); 188 189 if (!ofw_bus_is_compatible(dev, "fsl,ipu3")) 190 return (ENXIO); 191 192 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)"); 193 194 return (BUS_PROBE_DEFAULT); 195 } 196 197 static int 198 ipu3_fb_attach(device_t dev) 199 { 200 struct ipu3sc_softc *sc = device_get_softc(dev); 201 bus_space_tag_t iot; 202 bus_space_handle_t ioh; 203 phandle_t node; 204 pcell_t reg; 205 int err; 206 uintptr_t base; 207 208 ipu3sc_softc = sc; 209 210 if (bootverbose) 211 device_printf(dev, "clock gate status is %d\n", 212 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT)); 213 214 sc->dev = dev; 215 216 sc = device_get_softc(dev); 217 sc->iot = iot = fdtbus_bs_tag; 218 219 /* 220 * Retrieve the device address based on the start address in the 221 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register 222 * address, so we just subtract IPU_CM_BASE to get the offset at which 223 * the IPU device was memory mapped. 224 * On i.MX53, the offset is 0. 225 */ 226 node = ofw_bus_get_node(dev); 227 if ((OF_getprop(node, "reg", ®, sizeof(reg))) <= 0) 228 base = 0; 229 else 230 base = fdt32_to_cpu(reg) - IPU_CM_BASE(0); 231 /* map controller registers */ 232 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh); 233 if (err) 234 goto fail_retarn_cm; 235 sc->cm_ioh = ioh; 236 237 /* map Display Multi FIFO Controller registers */ 238 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh); 239 if (err) 240 goto fail_retarn_dmfc; 241 sc->dmfc_ioh = ioh; 242 243 /* map Display Interface 0 registers */ 244 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh); 245 if (err) 246 goto fail_retarn_di0; 247 sc->di0_ioh = ioh; 248 249 /* map Display Interface 1 registers */ 250 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh); 251 if (err) 252 goto fail_retarn_di1; 253 sc->di1_ioh = ioh; 254 255 /* map Display Processor registers */ 256 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh); 257 if (err) 258 goto fail_retarn_dp; 259 sc->dp_ioh = ioh; 260 261 /* map Display Controller registers */ 262 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh); 263 if (err) 264 goto fail_retarn_dc; 265 sc->dc_ioh = ioh; 266 267 /* map Image DMA Controller registers */ 268 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0, 269 &ioh); 270 if (err) 271 goto fail_retarn_idmac; 272 sc->idmac_ioh = ioh; 273 274 /* map CPMEM registers */ 275 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0, 276 &ioh); 277 if (err) 278 goto fail_retarn_cpmem; 279 sc->cpmem_ioh = ioh; 280 281 /* map DCTEMPL registers */ 282 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0, 283 &ioh); 284 if (err) 285 goto fail_retarn_dctmpl; 286 sc->dctmpl_ioh = ioh; 287 288 #ifdef notyet 289 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, 290 ipuv3intr, sc); 291 if (sc->ih == NULL) { 292 device_printf(sc->dev, 293 "unable to establish interrupt at irq %d\n", 294 IMX51_INT_IPUV3); 295 return (ENXIO); 296 } 297 #endif 298 299 /* 300 * We have to wait until interrupts are enabled. 301 * Mailbox relies on it to get data from VideoCore 302 */ 303 ipu3_fb_init(sc); 304 305 sc->sc_info.fb_name = device_get_nameunit(dev); 306 307 ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth); 308 sc->sc_info.fb_cmsize = 16; 309 310 /* Ask newbus to attach framebuffer device to me. */ 311 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 312 if (sc->sc_fbd == NULL) 313 device_printf(dev, "Can't attach fbd device\n"); 314 315 return (bus_generic_attach(dev)); 316 317 fail_retarn_dctmpl: 318 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); 319 fail_retarn_cpmem: 320 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); 321 fail_retarn_idmac: 322 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); 323 fail_retarn_dp: 324 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); 325 fail_retarn_dc: 326 bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE); 327 fail_retarn_di1: 328 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); 329 fail_retarn_di0: 330 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); 331 fail_retarn_dmfc: 332 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); 333 fail_retarn_cm: 334 device_printf(sc->dev, 335 "failed to map registers (errno=%d)\n", err); 336 return (err); 337 } 338 339 static struct fb_info * 340 ipu3_fb_getinfo(device_t dev) 341 { 342 struct ipu3sc_softc *sc = device_get_softc(dev); 343 344 return (&sc->sc_info); 345 } 346 347 static device_method_t ipu3_fb_methods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_probe, ipu3_fb_probe), 350 DEVMETHOD(device_attach, ipu3_fb_attach), 351 352 /* Framebuffer service methods */ 353 DEVMETHOD(fb_getinfo, ipu3_fb_getinfo), 354 { 0, 0 } 355 }; 356 357 static devclass_t ipu3_fb_devclass; 358 359 static driver_t ipu3_fb_driver = { 360 "fb", 361 ipu3_fb_methods, 362 sizeof(struct ipu3sc_softc), 363 }; 364 365 DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0);
Cache object: 013202bbae68ed63f11ae4593c86c630
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