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sys/arm/freescale/imx/imx51_ipuv3reg.h
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1 /* $NetBSD: imx51_ipuv3reg.h,v 1.1 2012/04/17 10:19:57 bsh Exp $ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause AND BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 6 * Written by Hashimoto Kenichi for Genetec Corporation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /*- 31 * Copyright (c) 2012, 2013 The FreeBSD Foundation 32 * All rights reserved. 33 * 34 * Portions of this software were developed by Oleksandr Rybalko 35 * under sponsorship from the FreeBSD Foundation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 56 * SUCH DAMAGE. 57 * 58 * $FreeBSD$ 59 */ 60 61 #ifndef _ARM_IMX_IMX51_IPUV3REG_H 62 #define _ARM_IMX_IMX51_IPUV3REG_H 63 64 /* register offset address */ 65 66 /* 67 * CM 68 * Control Module 69 */ 70 #define IPU_CM_CONF 0x00000000 71 #define CM_CONF_CSI_SEL 0x80000000 72 #define CM_CONF_IC_INPUT 0x40000000 73 #define CM_CONF_CSI1_DATA_SOURCE 0x20000000 74 #define CM_CONF_CSI0_DATA_SOURCE 0x10000000 75 #define CM_CONF_VDI_DMFC_SYNC 0x08000000 76 #define CM_CONF_IC_DMFC_SYNC 0x04000000 77 #define CM_CONF_IC_DMFC_SEL 0x02000000 78 #define CM_CONF_ISP_DOUBLE_FLOW 0x01000000 79 #define CM_CONF_IDMAC_DISABLE 0x00400000 80 #define CM_CONF_IPU_DIAGBUS_ON 0x00200000 81 #define CM_CONF_IPU_DIAGBUS_MODE 0x001f0000 82 #define CM_CONF_VDI_EN 0x00001000 83 #define CM_CONF_SISG_EN 0x00000800 84 #define CM_CONF_DMFC_EN 0x00000400 85 #define CM_CONF_DC_EN 0x00000200 86 #define CM_CONF_SMFC_EN 0x00000100 87 #define CM_CONF_DI1_EN 0x00000080 88 #define CM_CONF_DI0_EN 0x00000040 89 #define CM_CONF_DP_EN 0x00000020 90 #define CM_CONF_ISP_EN 0x00000010 91 #define CM_CONF_IRT_EN 0x00000008 92 #define CM_CONF_IC_EN 0x00000004 93 #define CM_CONF_CSI1_EN 0x00000002 94 #define CM_CONF_CSI0_EN 0x00000001 95 #define IPU_SISG_CTRL0 0x00000004 96 #define IPU_SISG_CTRL1 0x00000008 97 #define IPU_CM_INT_CTRL_1 0x0000003c 98 #define IPU_CM_INT_CTRL_2 0x00000040 99 #define IPU_CM_INT_CTRL_3 0x00000044 100 #define IPU_CM_INT_CTRL_4 0x00000048 101 #define IPU_CM_INT_CTRL_5 0x0000004c 102 #define IPU_CM_INT_CTRL_6 0x00000050 103 #define IPU_CM_INT_CTRL_7 0x00000054 104 #define IPU_CM_INT_CTRL_8 0x00000058 105 #define IPU_CM_INT_CTRL_9 0x0000005c 106 #define IPU_CM_INT_CTRL_10 0x00000060 107 #define IPU_CM_INT_CTRL_11 0x00000064 108 #define IPU_CM_INT_CTRL_12 0x00000068 109 #define IPU_CM_INT_CTRL_13 0x0000006c 110 #define IPU_CM_INT_CTRL_14 0x00000070 111 #define IPU_CM_INT_CTRL_15 0x00000074 112 #define IPU_CM_SDMA_EVENT_1 0x00000078 113 #define IPU_CM_SDMA_EVENT_2 0x0000007c 114 #define IPU_CM_SDMA_EVENT_3 0x00000080 115 #define IPU_CM_SDMA_EVENT_4 0x00000084 116 #define IPU_CM_SDMA_EVENT_7 0x00000088 117 #define IPU_CM_SDMA_EVENT_8 0x0000008c 118 #define IPU_CM_SDMA_EVENT_11 0x00000090 119 #define IPU_CM_SDMA_EVENT_12 0x00000094 120 #define IPU_CM_SDMA_EVENT_13 0x00000098 121 #define IPU_CM_SDMA_EVENT_14 0x0000009c 122 #define IPU_CM_SRM_PRI1 0x000000a0 123 #define IPU_CM_SRM_PRI2 0x000000a4 124 #define IPU_CM_FS_PROC_FLOW1 0x000000a8 125 #define IPU_CM_FS_PROC_FLOW2 0x000000ac 126 #define IPU_CM_FS_PROC_FLOW3 0x000000b0 127 #define IPU_CM_FS_DISP_FLOW1 0x000000b4 128 #define IPU_CM_FS_DISP_FLOW2 0x000000b8 129 #define IPU_CM_SKIP 0x000000bc 130 #define IPU_CM_DISP_ALT_CONF 0x000000c0 131 #define IPU_CM_DISP_GEN 0x000000c4 132 #define CM_DISP_GEN_DI0_COUNTER_RELEASE 0x01000000 133 #define CM_DISP_GEN_DI1_COUNTER_RELEASE 0x00800000 134 #define CM_DISP_GEN_MCU_MAX_BURST_STOP 0x00400000 135 #define CM_DISP_GEN_MCU_T_SHIFT 18 136 #define CM_DISP_GEN_MCU_T(n) ((n) << CM_DISP_GEN_MCU_T_SHIFT) 137 #define IPU_CM_DISP_ALT1 0x000000c8 138 #define IPU_CM_DISP_ALT2 0x000000cc 139 #define IPU_CM_DISP_ALT3 0x000000d0 140 #define IPU_CM_DISP_ALT4 0x000000d4 141 #define IPU_CM_SNOOP 0x000000d8 142 #define IPU_CM_MEM_RST 0x000000dc 143 #define CM_MEM_START 0x80000000 144 #define CM_MEM_EN 0x007fffff 145 #define IPU_CM_PM 0x000000e0 146 #define IPU_CM_GPR 0x000000e4 147 #define CM_GPR_IPU_CH_BUF1_RDY1_CLR 0x80000000 148 #define CM_GPR_IPU_CH_BUF1_RDY0_CLR 0x40000000 149 #define CM_GPR_IPU_CH_BUF0_RDY1_CLR 0x20000000 150 #define CM_GPR_IPU_CH_BUF0_RDY0_CLR 0x10000000 151 #define CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR 0x08000000 152 #define CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR 0x04000000 153 #define CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR 0x02000000 154 #define CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR 0x01000000 155 #define CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS 0x00800000 156 #define CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS 0x00400000 157 #define CM_GPR_IPU_CH_BUF2_RDY1_CLR 0x00200000 158 #define CM_GPR_IPU_CH_BUF2_RDY0_CLR 0x00100000 159 #define CM_GPR_IPU_GP(n) __BIT((n)) 160 #define IPU_CM_CH_DB_MODE_SEL_0 0x00000150 161 #define IPU_CM_CH_DB_MODE_SEL_1 0x00000154 162 #define IPU_CM_ALT_CH_DB_MODE_SEL_0 0x00000168 163 #define IPU_CM_ALT_CH_DB_MODE_SEL_1 0x0000016c 164 #define IPU_CM_CH_TRB_MODE_SEL_0 0x00000178 165 #define IPU_CM_CH_TRB_MODE_SEL_1 0x0000017c 166 #define IPU_CM_INT_STAT_1 0x00000200 167 #define IPU_CM_INT_STAT_2 0x00000204 168 #define IPU_CM_INT_STAT_3 0x00000208 169 #define IPU_CM_INT_STAT_4 0x0000020c 170 #define IPU_CM_INT_STAT_5 0x00000210 171 #define IPU_CM_INT_STAT_6 0x00000214 172 #define IPU_CM_INT_STAT_7 0x00000218 173 #define IPU_CM_INT_STAT_8 0x0000021c 174 #define IPU_CM_INT_STAT_9 0x00000220 175 #define IPU_CM_INT_STAT_10 0x00000224 176 #define IPU_CM_INT_STAT_11 0x00000228 177 #define IPU_CM_INT_STAT_12 0x0000022c 178 #define IPU_CM_INT_STAT_13 0x00000230 179 #define IPU_CM_INT_STAT_14 0x00000234 180 #define IPU_CM_INT_STAT_15 0x00000238 181 #define IPU_CM_CUR_BUF_0 0x0000023c 182 #define IPU_CM_CUR_BUF_1 0x00000240 183 #define IPU_CM_ALT_CUR_BUF_0 0x00000244 184 #define IPU_CM_ALT_CUR_BUF_1 0x00000248 185 #define IPU_CM_SRM_STAT 0x0000024c 186 #define IPU_CM_PROC_TASKS_STAT 0x00000250 187 #define IPU_CM_DISP_TASKS_STAT 0x00000254 188 #define IPU_CM_TRIPLE_CUR_BUF_0 0x00000258 189 #define IPU_CM_TRIPLE_CUR_BUF_1 0x0000025c 190 #define IPU_CM_TRIPLE_CUR_BUF_2 0x00000260 191 #define IPU_CM_TRIPLE_CUR_BUF_3 0x00000264 192 #define IPU_CM_CH_BUF0_RDY0 0x00000268 193 #define IPU_CM_CH_BUF0_RDY1 0x0000026c 194 #define IPU_CM_CH_BUF1_RDY0 0x00000270 195 #define IPU_CM_CH_BUF1_RDY1 0x00000274 196 #define IPU_CM_ALT_CH_BUF0_RDY0 0x00000278 197 #define IPU_CM_ALT_CH_BUF0_RDY1 0x0000027c 198 #define IPU_CM_ALT_CH_BUF1_RDY0 0x00000280 199 #define IPU_CM_ALT_CH_BUF1_RDY1 0x00000284 200 #define IPU_CM_CH_BUF2_RDY0 0x00000288 201 #define IPU_CM_CH_BUF2_RDY1 0x0000028c 202 203 /* 204 * IDMAC 205 * Image DMA Controller 206 */ 207 #define IPU_IDMAC_CONF 0x00000000 208 #define IPU_IDMAC_CH_EN_1 0x00000004 209 #define IPU_IDMAC_CH_EN_2 0x00000008 210 #define IPU_IDMAC_SEP_ALPHA 0x0000000c 211 #define IPU_IDMAC_ALT_SEP_ALPHA 0x00000010 212 #define IPU_IDMAC_CH_PRI_1 0x00000014 213 #define IPU_IDMAC_CH_PRI_2 0x00000018 214 #define IPU_IDMAC_WM_EN_1 0x0000001c 215 #define IPU_IDMAC_WM_EN_2 0x00000020 216 #define IPU_IDMAC_LOCK_EN_1 0x00000024 217 #define IPU_IDMAC_LOCK_EN_2 0x00000028 218 #define IPU_IDMAC_SUB_ADDR_0 0x0000002c 219 #define IPU_IDMAC_SUB_ADDR_1 0x00000030 220 #define IPU_IDMAC_SUB_ADDR_2 0x00000034 221 #define IPU_IDMAC_SUB_ADDR_3 0x00000038 222 #define IPU_IDMAC_SUB_ADDR_4 0x0000003c 223 #define IPU_IDMAC_BNDM_EN_1 0x00000040 224 #define IPU_IDMAC_BNDM_EN_2 0x00000044 225 #define IPU_IDMAC_SC_CORD 0x00000048 226 #define IPU_IDMAC_SC_CORD1 0x0000004c 227 #define IPU_IDMAC_CH_BUSY_1 0x00000100 228 #define IPU_IDMAC_CH_BUSY_2 0x00000104 229 230 #define CH_PANNEL_BG 23 231 #define CH_PANNEL_FG 27 232 233 /* 234 * DP 235 * Display Port 236 */ 237 #define IPU_DP_DEBUG_CNT 0x000000bc 238 #define IPU_DP_DEBUG_STAT 0x000000c0 239 240 /* 241 * IC 242 * Image Converter 243 */ 244 #define IPU_IC_CONF 0x00000000 245 #define IPU_IC_PRP_ENC_RSC 0x00000004 246 #define IPU_IC_PRP_VF_RSC 0x00000008 247 #define IPU_IC_PP_RSC 0x0000000c 248 #define IPU_IC_CMBP_1 0x00000010 249 #define IPU_IC_CMBP_2 0x00000014 250 #define IPU_IC_IDMAC_1 0x00000018 251 #define IPU_IC_IDMAC_2 0x0000001c 252 #define IPU_IC_IDMAC_3 0x00000020 253 #define IPU_IC_IDMAC_4 0x00000024 254 255 /* 256 * CSI 257 * Camera Sensor Interface 258 */ 259 #define IPU_CSI0_SENS_CONF 0x00000000 260 #define IPU_CSI0_SENS_FRM_SIZE 0x00000004 261 #define IPU_CSI0_ACT_FRM_SIZE 0x00000008 262 #define IPU_CSI0_OUT_FRM_CTRL 0x0000000c 263 #define IPU_CSI0_TST_CTRL 0x00000010 264 #define IPU_CSI0_CCIR_CODE_1 0x00000014 265 #define IPU_CSI0_CCIR_CODE_2 0x00000018 266 #define IPU_CSI0_CCIR_CODE_3 0x0000001c 267 #define IPU_CSI0_DI 0x00000020 268 #define IPU_CSI0_SKIP 0x00000024 269 #define IPU_CSI0_CPD_CTRL 0x00000028 270 #define IPU_CSI0_CPD_OFFSET1 0x000000ec 271 #define IPU_CSI0_CPD_OFFSET2 0x000000f0 272 273 #define IPU_CSI1_SENS_CONF 0x00000000 274 #define IPU_CSI1_SENS_FRM_SIZE 0x00000004 275 #define IPU_CSI1_ACT_FRM_SIZE 0x00000008 276 #define IPU_CSI1_OUT_FRM_CTRL 0x0000000c 277 #define IPU_CSI1_TST_CTRL 0x00000010 278 #define IPU_CSI1_CCIR_CODE_1 0x00000014 279 #define IPU_CSI1_CCIR_CODE_2 0x00000018 280 #define IPU_CSI1_CCIR_CODE_3 0x0000001c 281 #define IPU_CSI1_DI 0x00000020 282 #define IPU_CSI1_SKIP 0x00000024 283 #define IPU_CSI1_CPD_CTRL 0x00000028 284 #define IPU_CSI1_CPD_OFFSET1 0x000000ec 285 #define IPU_CSI1_CPD_OFFSET2 0x000000f0 286 287 /* 288 * DI 289 * Display Interface 290 */ 291 #define IPU_DI_GENERAL 0x00000000 292 #define DI_GENERAL_DISP_Y_SEL 0x70000000 293 #define DI_GENERAL_CLOCK_STOP_MODE 0x0f000000 294 #define DI_GENERAL_DISP_CLOCK_INIT 0x00800000 295 #define DI_GENERAL_MASK_SEL 0x00400000 296 #define DI_GENERAL_VSYNC_EXT 0x00200000 297 #define DI_GENERAL_CLK_EXT 0x00100000 298 #define DI_GENERAL_WATCHDOG_MODE 0x000c0000 299 #define DI_GENERAL_POLARITY_DISP_CLK 0x00020000 300 #define DI_GENERAL_SYNC_COUNT_SEL 0x0000f000 301 #define DI_GENERAL_ERR_TREATMENT 0x00000800 302 #define DI_GENERAL_ERM_VSYNC_SEL 0x00000400 303 #define DI_GENERAL_POLARITY_CS(n) (1 << ((n) + 8)) 304 #define DI_GENERAL_POLARITY(n) (1 << ((n) - 1)) 305 306 #define IPU_DI_BS_CLKGEN0 0x00000004 307 #define DI_BS_CLKGEN0_OFFSET_SHIFT 16 308 #define IPU_DI_BS_CLKGEN1 0x00000008 309 #define DI_BS_CLKGEN1_DOWN_SHIFT 16 310 #define DI_BS_CLKGEN1_UP_SHIFT 0 311 #define IPU_DI_SW_GEN0(n) (0x0000000c + ((n) - 1) * 4) 312 #define DI_SW_GEN0_RUN_VAL 0x7ff80000 313 #define DI_SW_GEN0_RUN_RESOL 0x00070000 314 #define DI_SW_GEN0_OFFSET_VAL 0x00007ff8 315 #define DI_SW_GEN0_OFFSET_RESOL 0x00000007 316 #define __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol) \ 317 (((run_val) << 19) | ((run_resol) << 16) | \ 318 ((offset_val) << 3) | (offset_resol)) 319 #define IPU_DI_SW_GEN1(n) (0x00000030 + ((n) - 1) * 4) 320 #define DI_SW_GEN1_CNT_POL_GEN_EN 0x60000000 321 #define DI_SW_GEN1_CNT_AUTO_RELOAD 0x10000000 322 #define DI_SW_GEN1_CNT_CLR_SEL 0x0e000000 323 #define DI_SW_GEN1_CNT_DOWN 0x01ff0000 324 #define DI_SW_GEN1_CNT_POL_TRIG_SEL 0x00007000 325 #define DI_SW_GEN1_CNT_POL_CLR_SEL 0x00000e00 326 #define DI_SW_GEN1_CNT_UP 0x000001ff 327 #define __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \ 328 (((pol_gen_en) << 29) | ((auto_reload) << 28) | \ 329 ((clr_sel) << 25) | \ 330 ((down) << 16) | ((pol_trig_sel) << 12) | \ 331 ((pol_clr_sel) << 9) | (up)) 332 #define IPU_DI_SYNC_AS_GEN 0x00000054 333 #define DI_SYNC_AS_GEN_SYNC_START_EN 0x10000000 334 #define DI_SYNC_AS_GEN_VSYNC_SEL 0x0000e000 335 #define DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT 13 336 #define DI_SYNC_AS_GEN_SYNC_STAR 0x00000fff 337 #define IPU_DI_DW_GEN(n) (0x00000058 + (n) * 4) 338 #define DI_DW_GEN_ACCESS_SIZE_SHIFT 24 339 #define DI_DW_GEN_COMPONNENT_SIZE_SHIFT 16 340 #define DI_DW_GEN_PIN_SHIFT(n) (((n) - 11) * 2) 341 #define DI_DW_GEN_PIN(n) __BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \ 342 DI_DW_GEN_PIN_SHIFT(n)) 343 #define IPU_DI_DW_SET(n, m) (0x00000088 + (n) * 4 + (m) * 0x30) 344 #define DI_DW_SET_DOWN_SHIFT 16 345 #define DI_DW_SET_UP_SHIFT 0 346 #define IPU_DI_STP_REP(n) (0x00000148 + ((n - 1) / 2) * 4) 347 #define DI_STP_REP_SHIFT(n) (((n - 1) % 2) * 16) 348 #define DI_STP_REP_MASK(n) (0x00000fff << DI_STP_REP_SHIFT((n))) 349 #define IPU_DI_SER_CONF 0x0000015c 350 #define IPU_DI_SSC 0x00000160 351 #define IPU_DI_POL 0x00000164 352 #define DI_POL_DRDY_POLARITY_17 0x00000040 353 #define DI_POL_DRDY_POLARITY_16 0x00000020 354 #define DI_POL_DRDY_POLARITY_15 0x00000010 355 #define DI_POL_DRDY_POLARITY_14 0x00000008 356 #define DI_POL_DRDY_POLARITY_13 0x00000004 357 #define DI_POL_DRDY_POLARITY_12 0x00000002 358 #define DI_POL_DRDY_POLARITY_11 0x00000001 359 #define IPU_DI_AW0 0x00000168 360 #define IPU_DI_AW1 0x0000016c 361 #define IPU_DI_SCR_CONF 0x00000170 362 #define IPU_DI_STAT 0x00000174 363 364 /* 365 * SMFC 366 * Sensor Multi FIFO Controller 367 */ 368 #define IPU_SMFC_MAP 0x00000000 369 #define IPU_SMFC_WMC 0x00000004 370 #define IPU_SMFC_BS 0x00000008 371 372 /* 373 * DC 374 * Display Controller 375 */ 376 #define IPU_DC_READ_CH_CONF 0x00000000 377 #define IPU_DC_READ_CH_ADDR 0x00000004 378 379 #define IPU_DC_RL0_CH_0 0x00000008 380 #define IPU_DC_RL1_CH_0 0x0000000c 381 #define IPU_DC_RL2_CH_0 0x00000010 382 #define IPU_DC_RL3_CH_0 0x00000014 383 #define IPU_DC_RL4_CH_0 0x00000018 384 #define IPU_DC_WR_CH_CONF_1 0x0000001c 385 #define IPU_DC_WR_CH_ADDR_1 0x00000020 386 #define IPU_DC_RL0_CH_1 0x00000024 387 #define IPU_DC_RL1_CH_1 0x00000028 388 #define IPU_DC_RL2_CH_1 0x0000002c 389 #define IPU_DC_RL3_CH_1 0x00000030 390 #define IPU_DC_RL4_CH_1 0x00000034 391 #define IPU_DC_WR_CH_CONF_2 0x00000038 392 #define IPU_DC_WR_CH_ADDR_2 0x0000003c 393 #define IPU_DC_RL0_CH_2 0x00000040 394 #define IPU_DC_RL1_CH_2 0x00000044 395 #define IPU_DC_RL2_CH_2 0x00000048 396 #define IPU_DC_RL3_CH_2 0x0000004c 397 #define IPU_DC_RL4_CH_2 0x00000050 398 #define IPU_DC_CMD_CH_CONF_3 0x00000054 399 #define IPU_DC_CMD_CH_CONF_4 0x00000058 400 #define IPU_DC_WR_CH_CONF_5 0x0000005c 401 #define IPU_DC_WR_CH_ADDR_5 0x00000060 402 #define IPU_DC_RL0_CH_5 0x00000064 403 #define IPU_DC_RL1_CH_5 0x00000068 404 #define IPU_DC_RL2_CH_5 0x0000006c 405 #define IPU_DC_RL3_CH_5 0x00000070 406 #define IPU_DC_RL4_CH_5 0x00000074 407 #define IPU_DC_WR_CH_CONF_6 0x00000078 408 #define IPU_DC_WR_CH_ADDR_6 0x0000007c 409 #define IPU_DC_RL0_CH_6 0x00000080 410 #define IPU_DC_RL1_CH_6 0x00000084 411 #define IPU_DC_RL2_CH_6 0x00000088 412 #define IPU_DC_RL3_CH_6 0x0000008c 413 #define IPU_DC_RL4_CH_6 0x00000090 414 #define IPU_DC_WR_CH_CONF1_8 0x00000094 415 #define IPU_DC_WR_CH_CONF2_8 0x00000098 416 #define IPU_DC_RL1_CH_8 0x0000009c 417 #define IPU_DC_RL2_CH_8 0x000000a0 418 #define IPU_DC_RL3_CH_8 0x000000a4 419 #define IPU_DC_RL4_CH_8 0x000000a8 420 #define IPU_DC_RL5_CH_8 0x000000ac 421 #define IPU_DC_RL6_CH_8 0x000000b0 422 #define IPU_DC_WR_CH_CONF1_9 0x000000b4 423 #define IPU_DC_WR_CH_CONF2_9 0x000000b8 424 #define IPU_DC_RL1_CH_9 0x000000bc 425 #define IPU_DC_RL2_CH_9 0x000000c0 426 #define IPU_DC_RL3_CH_9 0x000000c4 427 #define IPU_DC_RL4_CH_9 0x000000c8 428 #define IPU_DC_RL5_CH_9 0x000000cc 429 #define IPU_DC_RL6_CH_9 0x000000d0 430 431 #define IPU_DC_RL(chan_base, evt) ((chan_base) + (evt / 2) *0x4) 432 #define DC_RL_CH_0 IPU_DC_RL0_CH_0 433 #define DC_RL_CH_1 IPU_DC_RL0_CH_1 434 #define DC_RL_CH_2 IPU_DC_RL0_CH_2 435 #define DC_RL_CH_5 IPU_DC_RL0_CH_5 436 #define DC_RL_CH_6 IPU_DC_RL0_CH_6 437 #define DC_RL_CH_8 IPU_DC_RL0_CH_8 438 439 #define DC_RL_EVT_NF 0 440 #define DC_RL_EVT_NL 1 441 #define DC_RL_EVT_EOF 2 442 #define DC_RL_EVT_NFIELD 3 443 #define DC_RL_EVT_EOL 4 444 #define DC_RL_EVT_EOFIELD 5 445 #define DC_RL_EVT_NEW_ADDR 6 446 #define DC_RL_EVT_NEW_CHAN 7 447 #define DC_RL_EVT_NEW_DATA 8 448 449 #define IPU_DC_GEN 0x000000d4 450 #define IPU_DC_DISP_CONF1_0 0x000000d8 451 #define IPU_DC_DISP_CONF1_1 0x000000dc 452 #define IPU_DC_DISP_CONF1_2 0x000000e0 453 #define IPU_DC_DISP_CONF1_3 0x000000e4 454 #define IPU_DC_DISP_CONF2_0 0x000000e8 455 #define IPU_DC_DISP_CONF2_1 0x000000ec 456 #define IPU_DC_DISP_CONF2_2 0x000000f0 457 #define IPU_DC_DISP_CONF2_3 0x000000f4 458 #define IPU_DC_DI0_CONF_1 0x000000f8 459 #define IPU_DC_DI0_CONF_2 0x000000fc 460 #define IPU_DC_DI1_CONF_1 0x00000100 461 #define IPU_DC_DI1_CONF_2 0x00000104 462 463 #define IPU_DC_MAP_CONF_PNTR(n) (0x00000108 + (n) * 4) 464 #define IPU_DC_MAP_CONF_0 0x00000108 465 #define IPU_DC_MAP_CONF_1 0x0000010c 466 #define IPU_DC_MAP_CONF_2 0x00000110 467 #define IPU_DC_MAP_CONF_3 0x00000114 468 #define IPU_DC_MAP_CONF_4 0x00000118 469 #define IPU_DC_MAP_CONF_5 0x0000011c 470 #define IPU_DC_MAP_CONF_6 0x00000120 471 #define IPU_DC_MAP_CONF_7 0x00000124 472 #define IPU_DC_MAP_CONF_8 0x00000128 473 #define IPU_DC_MAP_CONF_9 0x0000012c 474 #define IPU_DC_MAP_CONF_10 0x00000130 475 #define IPU_DC_MAP_CONF_11 0x00000134 476 #define IPU_DC_MAP_CONF_12 0x00000138 477 #define IPU_DC_MAP_CONF_13 0x0000013c 478 #define IPU_DC_MAP_CONF_14 0x00000140 479 480 #define IPU_DC_MAP_CONF_MASK(n) (0x00000144 + (n) * 4) 481 #define IPU_DC_MAP_CONF_15 0x00000144 482 #define IPU_DC_MAP_CONF_16 0x00000148 483 #define IPU_DC_MAP_CONF_17 0x0000014c 484 #define IPU_DC_MAP_CONF_18 0x00000150 485 #define IPU_DC_MAP_CONF_19 0x00000154 486 #define IPU_DC_MAP_CONF_20 0x00000158 487 #define IPU_DC_MAP_CONF_21 0x0000015c 488 #define IPU_DC_MAP_CONF_22 0x00000160 489 #define IPU_DC_MAP_CONF_23 0x00000164 490 #define IPU_DC_MAP_CONF_24 0x00000168 491 #define IPU_DC_MAP_CONF_25 0x0000016c 492 #define IPU_DC_MAP_CONF_26 0x00000170 493 494 #define IPU_DC_UGDE(m, n) (0x00000174 + (m) * 0x10 + (n) +4) 495 #define IPU_DC_UGDE0_0 0x00000174 496 #define IPU_DC_UGDE0_1 0x00000178 497 #define IPU_DC_UGDE0_2 0x0000017c 498 #define IPU_DC_UGDE0_3 0x00000180 499 #define IPU_DC_UGDE1_0 0x00000184 500 #define IPU_DC_UGDE1_1 0x00000188 501 #define IPU_DC_UGDE1_2 0x0000018c 502 #define IPU_DC_UGDE1_3 0x00000190 503 #define IPU_DC_UGDE2_0 0x00000194 504 #define IPU_DC_UGDE2_1 0x00000198 505 #define IPU_DC_UGDE2_2 0x0000019c 506 #define IPU_DC_UGDE2_3 0x000001a0 507 #define IPU_DC_UGDE3_0 0x000001a4 508 #define IPU_DC_UGDE3_1 0x000001a8 509 #define IPU_DC_UGDE3_2 0x000001ac 510 #define IPU_DC_UGDE3_3 0x000001b0 511 #define IPU_DC_LLA0 0x000001b4 512 #define IPU_DC_LLA1 0x000001b8 513 #define IPU_DC_R_LLA0 0x000001bc 514 #define IPU_DC_R_LLA1 0x000001c0 515 #define IPU_DC_WR_CH_ADDR_5_ALT 0x000001c4 516 #define IPU_DC_STAT 0x000001c8 517 518 /* 519 * DMFC 520 * Display Multi FIFO Controller 521 */ 522 #define IPU_DMFC_RD_CHAN 0x00000000 523 #define DMFC_RD_CHAN_PPW_C 0x03000000 524 #define DMFC_RD_CHAN_WM_DR_0 0x00e00000 525 #define DMFC_RD_CHAN_WM_SET_0 0x001c0000 526 #define DMFC_RD_CHAN_WM_EN_0 0x00020000 527 #define DMFC_RD_CHAN_BURST_SIZE_0 0x000000c0 528 #define IPU_DMFC_WR_CHAN 0x00000004 529 #define DMFC_WR_CHAN_BUSRT_SIZE_2C 0xc0000000 530 #define DMFC_WR_CHAN_FIFO_SIZE_2C 0x38000000 531 #define DMFC_WR_CHAN_ST_ADDR_2C 0x07000000 532 #define DMFC_WR_CHAN_BURST_SIZE_1C 0x00c00000 533 #define DMFC_WR_CHAN_FIFO_SIZE_1C 0x00380000 534 #define DMFC_WR_CHAN_ST_ADDR_1C 0x00070000 535 #define DMFC_WR_CHAN_BURST_SIZE_2 0x0000c000 536 #define DMFC_WR_CHAN_FIFO_SIZE_2 0x00003800 537 #define DMFC_WR_CHAN_ST_ADDR_2 0x00000700 538 #define DMFC_WR_CHAN_BURST_SIZE_1 0x000000c0 539 #define DMFC_WR_CHAN_FIFO_SIZE_1 0x00000038 540 #define DMFC_WR_CHAN_ST_ADDR_1 0x00000007 541 #define IPU_DMFC_WR_CHAN_DEF 0x00000008 542 #define DMFC_WR_CHAN_DEF_WM_CLR_2C 0xe0000000 543 #define DMFC_WR_CHAN_DEF_WM_SET_2C 0x1c000000 544 #define DMFC_WR_CHAN_DEF_WM_EN_2C 0x02000000 545 #define DMFC_WR_CHAN_DEF_WM_CLR_1C 0x00e00000 546 #define DMFC_WR_CHAN_DEF_WM_SET_1C 0x001c0000 547 #define DMFC_WR_CHAN_DEF_WM_EN_1C 0x00020000 548 #define DMFC_WR_CHAN_DEF_WM_CLR_2 0x0000e000 549 #define DMFC_WR_CHAN_DEF_WM_SET_2 0x00001c00 550 #define DMFC_WR_CHAN_DEF_WM_EN_2 0x00000200 551 #define DMFC_WR_CHAN_DEF_WM_CLR_1 0x000000e0 552 #define DMFC_WR_CHAN_DEF_WM_SET_1 0x0000000c 553 #define DMFC_WR_CHAN_DEF_WM_EN_1 0x00000002 554 #define IPU_DMFC_DP_CHAN 0x0000000c 555 #define DMFC_DP_CHAN_BUSRT_SIZE_6F 0xc0000000 556 #define DMFC_DP_CHAN_FIFO_SIZE_6F 0x38000000 557 #define DMFC_DP_CHAN_ST_ADDR_6F 0x07000000 558 #define DMFC_DP_CHAN_BURST_SIZE_6B 0x00c00000 559 #define DMFC_DP_CHAN_FIFO_SIZE_6B 0x00380000 560 #define DMFC_DP_CHAN_ST_ADDR_6B 0x00070000 561 #define DMFC_DP_CHAN_BURST_SIZE_5F 0x0000c000 562 #define DMFC_DP_CHAN_FIFO_SIZE_5F 0x00003800 563 #define DMFC_DP_CHAN_ST_ADDR_5F 0x00000700 564 #define DMFC_DP_CHAN_BURST_SIZE_5B 0x000000c0 565 #define DMFC_DP_CHAN_FIFO_SIZE_5B 0x00000038 566 #define DMFC_DP_CHAN_ST_ADDR_5B 0x00000007 567 #define IPU_DMFC_DP_CHAN_DEF 0x00000010 568 #define DMFC_DP_CHAN_DEF_WM_CLR_6F 0xe0000000 569 #define DMFC_DP_CHAN_DEF_WM_SET_6F 0x1c000000 570 #define DMFC_DP_CHAN_DEF_WM_EN_6F 0x02000000 571 #define DMFC_DP_CHAN_DEF_WM_CLR_6B 0x00e00000 572 #define DMFC_DP_CHAN_DEF_WM_SET_6B 0x001c0000 573 #define DMFC_DP_CHAN_DEF_WM_EN_6B 0x00020000 574 #define DMFC_DP_CHAN_DEF_WM_CLR_5F 0x0000e000 575 #define DMFC_DP_CHAN_DEF_WM_SET_5F 0x00001c00 576 #define DMFC_DP_CHAN_DEF_WM_EN_5F 0x00000200 577 #define DMFC_DP_CHAN_DEF_WM_CLR_5B 0x000000e0 578 #define DMFC_DP_CHAN_DEF_WM_SET_5B 0x0000001c 579 #define DMFC_DP_CHAN_DEF_WM_EN_5B 0x00000002 580 #define IPU_DMFC_GENERAL1 0x00000014 581 #define DMFC_GENERAL1_WAIT4EOT_9 0x01000000 582 #define DMFC_GENERAL1_WAIT4EOT_6F 0x00800000 583 #define DMFC_GENERAL1_WAIT4EOT_6B 0x00400000 584 #define DMFC_GENERAL1_WAIT4EOT_5F 0x00200000 585 #define DMFC_GENERAL1_WAIT4EOT_5B 0x00100000 586 #define DMFC_GENERAL1_WAIT4EOT_4 0x00080000 587 #define DMFC_GENERAL1_WAIT4EOT_3 0x00040000 588 #define DMFC_GENERAL1_WAIT4EOT_2 0x00020000 589 #define DMFC_GENERAL1_WAIT4EOT_1 0x00010000 590 #define DMFC_GENERAL1_WM_CLR_9 0x0000e000 591 #define DMFC_GENERAL1_WM_SET_9 0x00001c00 592 #define DMFC_GENERAL1_BURST_SIZE_9 0x00000060 593 #define DMFC_GENERAL1_DCDP_SYNC_PR 0x00000003 594 #define DCDP_SYNC_PR_FORBIDDEN 0 595 #define DCDP_SYNC_PR_DC_DP 1 596 #define DCDP_SYNC_PR_DP_DC 2 597 #define DCDP_SYNC_PR_ROUNDROBIN 3 598 #define IPU_DMFC_GENERAL2 0x00000018 599 #define DMFC_GENERAL2_FRAME_HEIGHT_RD 0x1fff0000 600 #define DMFC_GENERAL2_FRAME_WIDTH_RD 0x00001fff 601 #define IPU_DMFC_IC_CTRL 0x0000001c 602 #define DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD 0xfff80000 603 #define DMFC_IC_CTRL_IC_FRAME_WIDTH_RD 0x0007ffc0 604 #define DMFC_IC_CTRL_IC_PPW_C 0x00000030 605 #define DMFC_IC_CTRL_IC_IN_PORT 0x00000007 606 #define IC_IN_PORT_CH28 0 607 #define IC_IN_PORT_CH41 1 608 #define IC_IN_PORT_DISABLE 2 609 #define IC_IN_PORT_CH23 4 610 #define IC_IN_PORT_CH27 5 611 #define IC_IN_PORT_CH24 6 612 #define IC_IN_PORT_CH29 7 613 #define IPU_DMFC_WR_CHAN_ALT 0x00000020 614 #define IPU_DMFC_WR_CHAN_DEF_ALT 0x00000024 615 #define IPU_DMFC_DP_CHAN_ALT 0x00000028 616 #define IPU_DMFC_DP_CHAN_DEF_ALT 0x0000002c 617 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT 0xe0000000 618 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT 0x1c000000 619 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT 0x02000000 620 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT 0x00e00000 621 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT 0x001c0000 622 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT 0x00020000 623 #define DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT 0x000000e0 624 #define DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT 0x0000001c 625 #define DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT 0x00000002 626 #define IPU_DMFC_GENERAL1_ALT 0x00000030 627 #define DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT 0x00800000 628 #define DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT 0x00400000 629 #define DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT 0x00100000 630 #define DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT 0x00020000 631 #define IPU_DMFC_STAT 0x00000034 632 #define DMFC_STAT_IC_BUFFER_EMPTY 0x02000000 633 #define DMFC_STAT_IC_BUFFER_FULL 0x01000000 634 #define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) 635 #define DMFC_STAT_FIFO_FULL(n) __BIT((n)) 636 637 /* 638 * VCI 639 * Video De Interkacing Module 640 */ 641 #define IPU_VDI_FSIZE 0x00000000 642 #define IPU_VDI_C 0x00000004 643 644 /* 645 * DP 646 * Display Processor 647 */ 648 #define IPU_DP_COM_CONF_SYNC 0x00000000 649 #define DP_FG_EN_SYNC 0x00000001 650 #define DP_DP_GWAM_SYNC 0x00000004 651 #define IPU_DP_GRAPH_WIND_CTRL_SYNC 0x00000004 652 #define IPU_DP_FG_POS_SYNC 0x00000008 653 #define IPU_DP_CUR_POS_SYNC 0x0000000c 654 #define IPU_DP_CUR_MAP_SYNC 0x00000010 655 #define IPU_DP_CSC_SYNC_0 0x00000054 656 #define IPU_DP_CSC_SYNC_1 0x00000058 657 #define IPU_DP_CUR_POS_ALT 0x0000005c 658 #define IPU_DP_COM_CONF_ASYNC0 0x00000060 659 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC0 0x00000064 660 #define IPU_DP_FG_POS_ASYNC0 0x00000068 661 #define IPU_DP_CUR_POS_ASYNC0 0x0000006c 662 #define IPU_DP_CUR_MAP_ASYNC0 0x00000070 663 #define IPU_DP_CSC_ASYNC0_0 0x000000b4 664 #define IPU_DP_CSC_ASYNC0_1 0x000000b8 665 #define IPU_DP_COM_CONF_ASYNC1 0x000000bc 666 #define IPU_DP_GRAPH_WIND_CTRL_ASYNC1 0x000000c0 667 #define IPU_DP_FG_POS_ASYNC1 0x000000c4 668 #define IPU_DP_CUR_POS_ASYNC1 0x000000c8 669 #define IPU_DP_CUR_MAP_ASYNC1 0x000000cc 670 #define IPU_DP_CSC_ASYNC1_0 0x00000110 671 #define IPU_DP_CSC_ASYNC1_1 0x00000114 672 673 /* IDMA parameter */ 674 /* 675 * non-Interleaved parameter 676 * 677 * param 0: XV W0[ 9: 0] 678 * YV W0[18:10] 679 * XB W0[31:19] 680 * param 1: YB W0[43:32] 681 * NSB W0[44] 682 * CF W0[45] 683 * UBO W0[61:46] 684 * param 2: UBO W0[67:62] 685 * VBO W0[89:68] 686 * IOX W0[93:90] 687 * RDRW W0[94] 688 * Reserved W0[95] 689 * param 3: Reserved W0[112:96] 690 * S0 W0[113] 691 * BNDM W0[116:114] 692 * BM W0[118:117] 693 * ROT W0[119] 694 * HF W0[120] 695 * VF W0[121] 696 * THF W0[122] 697 * CAP W0[123] 698 * CAE W0[124] 699 * FW W0[127:125] 700 * param 4: FW W0[137:128] 701 * FH W0[149:138] 702 * param 5: EBA0 W1[28:0] 703 * EBA1 W1[31:29] 704 * param 6: EBA1 W1[57:32] 705 * ILO W1[63:58] 706 * param 7: ILO W1[77:64] 707 * NPB W1[84:78] 708 * PFS W1[88:85] 709 * ALU W1[89] 710 * ALBM W1[92:90] 711 * ID W1[94:93] 712 * TH W1[95] 713 * param 8: TH W1[101:96] 714 * SLY W1[115:102] 715 * WID3 W1[127:125] 716 * param 9: SLUV W1[141:128] 717 * CRE W1[149] 718 * 719 * Interleaved parameter 720 * 721 * param 0: XV W0[ 9: 0] 722 * YV W0[18:10] 723 * XB W0[31:19] 724 * param 1: YB W0[43:32] 725 * NSB W0[44] 726 * CF W0[45] 727 * SX W0[57:46] 728 * SY W0[61:58] 729 * param 2: SY W0[68:62] 730 * NS W0[78:69] 731 * SDX W0[85:79] 732 * SM W0[95:86] 733 * param 3: SCC W0[96] 734 * SCE W0[97] 735 * SDY W0[104:98] 736 * SDRX W0[105] 737 * SDRY W0[106] 738 * BPP W0[109:107] 739 * DEC_SEL W0[111:110] 740 * DIM W0[112] 741 * SO W0[113] 742 * BNDM W0[116:114] 743 * BM W0[118:117] 744 * ROT W0[119] 745 * HF W0[120] 746 * VF W0[121] 747 * THF W0[122] 748 * CAP W0[123] 749 * CAE W0[124] 750 * FW W0[127:125] 751 * param 4: FW W0[137:128] 752 * FH W0[149:138] 753 * param 5: EBA0 W1[28:0] 754 * EBA1 W1[31:29] 755 * param 6: EBA1 W1[57:32] 756 * ILO W1[63:58] 757 * param 7: ILO W1[77:64] 758 * NPB W1[84:78] 759 * PFS W1[88:85] 760 * ALU W1[89] 761 * ALBM W1[92:90] 762 * ID W1[94:93] 763 * TH W1[95] 764 * param 8: TH W1[101:96] 765 * SL W1[115:102] 766 * WID0 W1[118:116] 767 * WID1 W1[121:119] 768 * WID2 W1[124:122] 769 * WID3 W1[127:125] 770 * param 9: OFS0 W1[132:128] 771 * OFS1 W1[137:133] 772 * OFS2 W1[142:138] 773 * OFS3 W1[147:143] 774 * SXYS W1[148] 775 * CRE W1[149] 776 * DEC_SEL2 W1[150] 777 */ 778 779 #define __IDMA_PARAM(word, shift, size) \ 780 ((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff)) 781 782 /* non-Interleaved parameter */ 783 /* W0 */ 784 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 785 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 786 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 787 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 788 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 789 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 790 #define IDMAC_Ch_PARAM_UBO __IDMA_PARAM(0, 46, 22) 791 #define IDMAC_Ch_PARAM_VBO __IDMA_PARAM(0, 68, 22) 792 #define IDMAC_Ch_PARAM_IOX __IDMA_PARAM(0, 90, 4) 793 #define IDMAC_Ch_PARAM_RDRW __IDMA_PARAM(0, 94, 1) 794 #define IDMAC_Ch_PARAM_S0 __IDMA_PARAM(0,113, 1) 795 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 796 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 797 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 798 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 799 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 800 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 801 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 802 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 803 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 804 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 805 /* W1 */ 806 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 807 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 808 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 809 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 810 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 811 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 812 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 813 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 814 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 815 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 816 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 817 #define IDMAC_Ch_PARAM_SLUV __IDMA_PARAM(1,128, 14) 818 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 819 820 /* Interleaved parameter */ 821 /* W0 */ 822 #define IDMAC_Ch_PARAM_XV __IDMA_PARAM(0, 0, 10) 823 #define IDMAC_Ch_PARAM_YV __IDMA_PARAM(0, 10, 9) 824 #define IDMAC_Ch_PARAM_XB __IDMA_PARAM(0, 19, 13) 825 #define IDMAC_Ch_PARAM_YB __IDMA_PARAM(0, 32, 12) 826 #define IDMAC_Ch_PARAM_NSB __IDMA_PARAM(0, 44, 1) 827 #define IDMAC_Ch_PARAM_CF __IDMA_PARAM(0, 45, 1) 828 #define IDMAC_Ch_PARAM_SX __IDMA_PARAM(0, 46, 12) 829 #define IDMAC_Ch_PARAM_SY __IDMA_PARAM(0, 58, 11) 830 #define IDMAC_Ch_PARAM_NS __IDMA_PARAM(0, 69, 10) 831 #define IDMAC_Ch_PARAM_SDX __IDMA_PARAM(0, 79, 7) 832 #define IDMAC_Ch_PARAM_SM __IDMA_PARAM(0, 86, 10) 833 #define IDMAC_Ch_PARAM_SCC __IDMA_PARAM(0, 96, 1) 834 #define IDMAC_Ch_PARAM_SCE __IDMA_PARAM(0, 97, 1) 835 #define IDMAC_Ch_PARAM_SDY __IDMA_PARAM(0, 98, 7) 836 #define IDMAC_Ch_PARAM_SDRX __IDMA_PARAM(0,105, 1) 837 #define IDMAC_Ch_PARAM_SDRY __IDMA_PARAM(0,106, 1) 838 #define IDMAC_Ch_PARAM_BPP __IDMA_PARAM(0,107, 3) 839 #define IDMAC_Ch_PARAM_DEC_SEL __IDMA_PARAM(0,110, 2) 840 #define IDMAC_Ch_PARAM_DIM __IDMA_PARAM(0,112, 1) 841 #define IDMAC_Ch_PARAM_SO __IDMA_PARAM(0,113, 1) 842 #define IDMAC_Ch_PARAM_BNDM __IDMA_PARAM(0,114, 3) 843 #define IDMAC_Ch_PARAM_BM __IDMA_PARAM(0,117, 2) 844 #define IDMAC_Ch_PARAM_ROT __IDMA_PARAM(0,119, 1) 845 #define IDMAC_Ch_PARAM_HF __IDMA_PARAM(0,120, 1) 846 #define IDMAC_Ch_PARAM_VF __IDMA_PARAM(0,121, 1) 847 #define IDMAC_Ch_PARAM_THF __IDMA_PARAM(0,122, 1) 848 #define IDMAC_Ch_PARAM_CAP __IDMA_PARAM(0,123, 1) 849 #define IDMAC_Ch_PARAM_CAE __IDMA_PARAM(0,124, 1) 850 #define IDMAC_Ch_PARAM_FW __IDMA_PARAM(0,125, 13) 851 #define IDMAC_Ch_PARAM_FH __IDMA_PARAM(0,138, 12) 852 /* W1 */ 853 #define IDMAC_Ch_PARAM_EBA0 __IDMA_PARAM(1, 0, 29) 854 #define IDMAC_Ch_PARAM_EBA1 __IDMA_PARAM(1, 29, 29) 855 #define IDMAC_Ch_PARAM_ILO __IDMA_PARAM(1, 58, 20) 856 #define IDMAC_Ch_PARAM_NPB __IDMA_PARAM(1, 78, 7) 857 #define IDMAC_Ch_PARAM_PFS __IDMA_PARAM(1, 85, 4) 858 #define IDMAC_Ch_PARAM_ALU __IDMA_PARAM(1, 89, 1) 859 #define IDMAC_Ch_PARAM_ALBM __IDMA_PARAM(1, 90, 3) 860 #define IDMAC_Ch_PARAM_ID __IDMA_PARAM(1, 93, 2) 861 #define IDMAC_Ch_PARAM_TH __IDMA_PARAM(1, 95, 7) 862 #define IDMAC_Ch_PARAM_SL __IDMA_PARAM(1,102, 14) 863 #define IDMAC_Ch_PARAM_WID0 __IDMA_PARAM(1,116, 3) 864 #define IDMAC_Ch_PARAM_WID1 __IDMA_PARAM(1,119, 3) 865 #define IDMAC_Ch_PARAM_WID2 __IDMA_PARAM(1,122, 3) 866 #define IDMAC_Ch_PARAM_WID3 __IDMA_PARAM(1,125, 3) 867 #define IDMAC_Ch_PARAM_OFS0 __IDMA_PARAM(1,128, 5) 868 #define IDMAC_Ch_PARAM_OFS1 __IDMA_PARAM(1,133, 5) 869 #define IDMAC_Ch_PARAM_OFS2 __IDMA_PARAM(1,138, 5) 870 #define IDMAC_Ch_PARAM_OFS3 __IDMA_PARAM(1,143, 5) 871 #define IDMAC_Ch_PARAM_SXYS __IDMA_PARAM(1,148, 1) 872 #define IDMAC_Ch_PARAM_CRE __IDMA_PARAM(1,149, 1) 873 #define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150, 1) 874 875 /* XXX Temp */ 876 #define GPUMEM_BASE 0x20000000 877 #define GPUMEM_SIZE 0x20000 878 879 #define GPU_BASE 0x30000000 880 #define GPU_SIZE 0x10000000 881 882 /* 883 * Image Processing Unit 884 * 885 * All addresses are relative to the base SoC address. 886 */ 887 #define IPU_CM_BASE(_base) ((_base) + 0x1e000000) 888 #define IPU_CM_SIZE 0x8000 889 #define IPU_IDMAC_BASE(_base) ((_base) + 0x1e008000) 890 #define IPU_IDMAC_SIZE 0x8000 891 #define IPU_DP_BASE(_base) ((_base) + 0x1e018000) 892 #define IPU_DP_SIZE 0x8000 893 #define IPU_IC_BASE(_base) ((_base) + 0x1e020000) 894 #define IPU_IC_SIZE 0x8000 895 #define IPU_IRT_BASE(_base) ((_base) + 0x1e028000) 896 #define IPU_IRT_SIZE 0x8000 897 #define IPU_CSI0_BASE(_base) ((_base) + 0x1e030000) 898 #define IPU_CSI0_SIZE 0x8000 899 #define IPU_CSI1_BASE(_base) ((_base) + 0x1e038000) 900 #define IPU_CSI1_SIZE 0x8000 901 #define IPU_DI0_BASE(_base) ((_base) + 0x1e040000) 902 #define IPU_DI0_SIZE 0x8000 903 #define IPU_DI1_BASE(_base) ((_base) + 0x1e048000) 904 #define IPU_DI1_SIZE 0x8000 905 #define IPU_SMFC_BASE(_base) ((_base) + 0x1e050000) 906 #define IPU_SMFC_SIZE 0x8000 907 #define IPU_DC_BASE(_base) ((_base) + 0x1e058000) 908 #define IPU_DC_SIZE 0x8000 909 #define IPU_DMFC_BASE(_base) ((_base) + 0x1e060000) 910 #define IPU_DMFC_SIZE 0x8000 911 #define IPU_VDI_BASE(_base) ((_base) + 0x1e068000) 912 #define IPU_VDI_SIZE 0x8000 913 #define IPU_CPMEM_BASE(_base) ((_base) + 0x1f000000) 914 #define IPU_CPMEM_SIZE 0x20000 915 #define IPU_LUT_BASE(_base) ((_base) + 0x1f020000) 916 #define IPU_LUT_SIZE 0x20000 917 #define IPU_SRM_BASE(_base) ((_base) + 0x1f040000) 918 #define IPU_SRM_SIZE 0x20000 919 #define IPU_TPM_BASE(_base) ((_base) + 0x1f060000) 920 #define IPU_TPM_SIZE 0x20000 921 #define IPU_DCTMPL_BASE(_base) ((_base) + 0x1f080000) 922 #define IPU_DCTMPL_SIZE 0x20000 923 924 #endif /* _ARM_IMX_IMX51_IPUV3REG_H */
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