1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 /*
34 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs.
35 * Also, temperature montoring and cpu frequency control. It was Freescale who
36 * kitchen-sinked this device, not us. :)
37 *
38 * We don't really do anything with analog PLLs, but the registers for
39 * controlling them belong to the same block as the power regulator registers.
40 * Since the newbus hierarchy makes it hard for anyone other than us to get at
41 * them, we just export a couple public functions to allow the imx6 CCM clock
42 * driver to read and write those registers.
43 *
44 * We also don't do anything about power regulation yet, but when the need
45 * arises, this would be the place for that code to live.
46 *
47 * I have no idea where the "anatop" name comes from. It's in the standard DTS
48 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
49 * from Freescale, but it's not in the SoC manual.
50 *
51 * Note that temperature values throughout this code are handled in two types of
52 * units. Items with '_cnt' in the name use the hardware temperature count
53 * units (higher counts are lower temperatures). Items with '_val' in the name
54 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl
55 * handlers (dK is the standard unit for temperature in sysctl).
56 */
57
58 #include <sys/param.h>
59 #include <sys/systm.h>
60 #include <sys/callout.h>
61 #include <sys/kernel.h>
62 #include <sys/limits.h>
63 #include <sys/sysctl.h>
64 #include <sys/module.h>
65 #include <sys/bus.h>
66 #include <sys/rman.h>
67
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
70
71 #include <machine/bus.h>
72
73 #include <arm/arm/mpcore_timervar.h>
74 #include <arm/freescale/fsl_ocotpreg.h>
75 #include <arm/freescale/fsl_ocotpvar.h>
76 #include <arm/freescale/imx/imx_ccmvar.h>
77 #include <arm/freescale/imx/imx_machdep.h>
78 #include <arm/freescale/imx/imx6_anatopreg.h>
79 #include <arm/freescale/imx/imx6_anatopvar.h>
80
81 static struct resource_spec imx6_anatop_spec[] = {
82 { SYS_RES_MEMORY, 0, RF_ACTIVE },
83 { -1, 0 }
84 };
85 #define MEMRES 0
86 #define IRQRES 1
87
88 struct imx6_anatop_softc {
89 device_t dev;
90 struct resource *res[2];
91 struct intr_config_hook
92 intr_setup_hook;
93 uint32_t cpu_curmhz;
94 uint32_t cpu_curmv;
95 uint32_t cpu_minmhz;
96 uint32_t cpu_minmv;
97 uint32_t cpu_maxmhz;
98 uint32_t cpu_maxmv;
99 uint32_t cpu_maxmhz_hw;
100 boolean_t cpu_overclock_enable;
101 boolean_t cpu_init_done;
102 uint32_t refosc_mhz;
103 void *temp_intrhand;
104 uint32_t temp_high_val;
105 uint32_t temp_high_cnt;
106 uint32_t temp_last_cnt;
107 uint32_t temp_room_cnt;
108 struct callout temp_throttle_callout;
109 sbintime_t temp_throttle_delay;
110 uint32_t temp_throttle_reset_cnt;
111 uint32_t temp_throttle_trigger_cnt;
112 uint32_t temp_throttle_val;
113 };
114
115 static struct imx6_anatop_softc *imx6_anatop_sc;
116
117 /*
118 * Table of "operating points".
119 * These are combinations of frequency and voltage blessed by Freescale.
120 * While the datasheet says the ARM voltage can be as low as 925mV at
121 * 396MHz, it also says that the ARM and SOC voltages can't differ by
122 * more than 200mV, and the minimum SOC voltage is 1150mV, so that
123 * dictates the 950mV entry in this table.
124 */
125 static struct oppt {
126 uint32_t mhz;
127 uint32_t mv;
128 } imx6_oppt_table[] = {
129 { 396, 950},
130 { 792, 1150},
131 { 852, 1225},
132 { 996, 1225},
133 {1200, 1275},
134 };
135
136 /*
137 * Table of CPU max frequencies. This is used to translate the max frequency
138 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
139 * up in the operating points table.
140 */
141 static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200};
142
143 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */
144
145 uint32_t
146 imx6_anatop_read_4(bus_size_t offset)
147 {
148
149 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL"));
150
151 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
152 }
153
154 void
155 imx6_anatop_write_4(bus_size_t offset, uint32_t value)
156 {
157
158 KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));
159
160 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
161 }
162
163 static void
164 vdd_set(struct imx6_anatop_softc *sc, int mv)
165 {
166 int newtarg, newtargSoc, oldtarg;
167 uint32_t delay, pmureg;
168 static boolean_t init_done = false;
169
170 /*
171 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
172 * can't be more than 50mV above or 200mV below them. We keep them the
173 * same except in the case of the lowest operating point, which is
174 * handled as a special case below.
175 */
176
177 pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
178 oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
179
180 /* Convert mV to target value. Clamp target to valid range. */
181 if (mv < 725)
182 newtarg = 0x00;
183 else if (mv > 1450)
184 newtarg = 0x1F;
185 else
186 newtarg = (mv - 700) / 25;
187
188 /*
189 * The SOC voltage can't go below 1150mV, and thus because of the 200mV
190 * rule, the ARM voltage can't go below 950mV. The 950 is encoded in
191 * our oppt table, here we handle the SOC 1150 rule as a special case.
192 * (1150-700/25=18).
193 */
194 newtargSoc = (newtarg < 18) ? 18 : newtarg;
195
196 /*
197 * The first time through the 3 voltages might not be equal so use a
198 * long conservative delay. After that we need to delay 3uS for every
199 * 25mV step upward; we actually delay 6uS because empirically, it works
200 * and the 3uS per step recommended by the docs doesn't (3uS fails when
201 * going from 400->1200, but works for smaller changes).
202 */
203 if (init_done) {
204 if (newtarg == oldtarg)
205 return;
206 else if (newtarg > oldtarg)
207 delay = (newtarg - oldtarg) * 6;
208 else
209 delay = 0;
210 } else {
211 delay = (700 / 25) * 6;
212 init_done = true;
213 }
214
215 /*
216 * Make the change and wait for it to take effect.
217 */
218 pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
219 IMX6_ANALOG_PMU_REG1_TARG_MASK |
220 IMX6_ANALOG_PMU_REG2_TARG_MASK);
221
222 pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
223 pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
224 pmureg |= newtargSoc << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
225
226 imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
227 DELAY(delay);
228 sc->cpu_curmv = newtarg * 25 + 700;
229 }
230
231 static inline uint32_t
232 cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t corediv,
233 uint32_t plldiv)
234 {
235
236 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1));
237 }
238
239 static inline void
240 cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz,
241 uint32_t *corediv, uint32_t *plldiv)
242 {
243
244 *corediv = (cpu_mhz < 650) ? 1 : 0;
245 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2);
246 }
247
248 static inline uint32_t
249 cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
250 {
251 uint32_t corediv, plldiv;
252
253 cpufreq_mhz_to_div(sc, cpu_mhz, &corediv, &plldiv);
254 return (cpufreq_mhz_from_div(sc, corediv, plldiv));
255 }
256
257 static struct oppt *
258 cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz)
259 {
260 int d, diff, i, nearest;
261
262 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
263 cpu_newmhz = sc->cpu_maxmhz_hw;
264
265 diff = INT_MAX;
266 nearest = 0;
267 for (i = 0; i < nitems(imx6_oppt_table); ++i) {
268 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
269 if (diff > d) {
270 diff = d;
271 nearest = i;
272 }
273 }
274 return (&imx6_oppt_table[nearest]);
275 }
276
277 static void
278 cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
279 {
280 uint32_t corediv, plldiv, timeout, wrk32;
281
282 /* If increasing the frequency, we must first increase the voltage. */
283 if (op->mhz > sc->cpu_curmhz) {
284 vdd_set(sc, op->mv);
285 }
286
287 /*
288 * I can't find a documented procedure for changing the ARM PLL divisor,
289 * but some trial and error came up with this:
290 * - Set the bypass clock source to REF_CLK_24M (source #0).
291 * - Set the PLL into bypass mode; cpu should now be running at 24mhz.
292 * - Change the divisor.
293 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
294 * - Turn off bypass mode; cpu should now be running at the new speed.
295 */
296 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
297 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
298 IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
299 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
300 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
301
302 wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
303 wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
304 wrk32 |= plldiv;
305 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
306
307 timeout = 10000;
308 while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
309 IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
310 if (--timeout == 0)
311 panic("imx6_set_cpu_clock(): PLL never locked");
312
313 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
314 IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
315 imx_ccm_set_cacrr(corediv);
316
317 /* If lowering the frequency, it is now safe to lower the voltage. */
318 if (op->mhz < sc->cpu_curmhz)
319 vdd_set(sc, op->mv);
320 sc->cpu_curmhz = op->mhz;
321
322 /* Tell the mpcore timer that its frequency has changed. */
323 arm_tmr_change_frequency(
324 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
325 }
326
327 static int
328 cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS)
329 {
330 struct imx6_anatop_softc *sc;
331 struct oppt * op;
332 uint32_t temp;
333 int err;
334
335 sc = arg1;
336
337 temp = sc->cpu_minmhz;
338 err = sysctl_handle_int(oidp, &temp, 0, req);
339 if (err != 0 || req->newptr == NULL)
340 return (err);
341
342 op = cpufreq_nearest_oppt(sc, temp);
343 if (op->mhz > sc->cpu_maxmhz)
344 return (ERANGE);
345 else if (op->mhz == sc->cpu_minmhz)
346 return (0);
347
348 /*
349 * Value changed, update softc. If the new min is higher than the
350 * current speed, raise the current speed to match.
351 */
352 sc->cpu_minmhz = op->mhz;
353 if (sc->cpu_minmhz > sc->cpu_curmhz) {
354 cpufreq_set_clock(sc, op);
355 }
356 return (err);
357 }
358
359 static int
360 cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS)
361 {
362 struct imx6_anatop_softc *sc;
363 struct oppt * op;
364 uint32_t temp;
365 int err;
366
367 sc = arg1;
368
369 temp = sc->cpu_maxmhz;
370 err = sysctl_handle_int(oidp, &temp, 0, req);
371 if (err != 0 || req->newptr == NULL)
372 return (err);
373
374 op = cpufreq_nearest_oppt(sc, temp);
375 if (op->mhz < sc->cpu_minmhz)
376 return (ERANGE);
377 else if (op->mhz == sc->cpu_maxmhz)
378 return (0);
379
380 /*
381 * Value changed, update softc and hardware. The hardware update is
382 * unconditional. We always try to run at max speed, so any change of
383 * the max means we need to change the current speed too, regardless of
384 * whether it is higher or lower than the old max.
385 */
386 sc->cpu_maxmhz = op->mhz;
387 cpufreq_set_clock(sc, op);
388
389 return (err);
390 }
391
392 static void
393 cpufreq_initialize(struct imx6_anatop_softc *sc)
394 {
395 uint32_t cfg3speed;
396 struct oppt * op;
397
398 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
399 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
400 "CPU frequency");
401
402 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
403 OID_AUTO, "cpu_minmhz",
404 CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_NEEDGIANT,
405 sc, 0, cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency");
406
407 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
408 OID_AUTO, "cpu_maxmhz",
409 CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_NOFETCH | CTLFLAG_NEEDGIANT,
410 sc, 0, cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency");
411
412 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
413 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
414 "Maximum CPU frequency allowed by hardware");
415
416 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
417 OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN,
418 &sc->cpu_overclock_enable, 0,
419 "Allow setting CPU frequency higher than cpu_maxmhz_hw");
420
421 /*
422 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
423 * (even though in the real world it will always be 24mhz). Oh wait a
424 * sec, I never wrote imx6_ccm.
425 */
426 sc->refosc_mhz = 24;
427
428 /*
429 * Get the maximum speed this cpu can be set to. The values in the
430 * OCOTP CFG3 register are not documented in the reference manual.
431 * The following info was in an archived email found via web search:
432 * - 2b'11: 1200000000Hz;
433 * - 2b'10: 996000000Hz;
434 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
435 * - 2b'00: 792000000Hz;
436 * The default hardware max speed can be overridden by a tunable.
437 */
438 cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) &
439 FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT;
440 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
441 sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
442
443 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
444 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
445 sc->cpu_minmhz = op->mhz;
446 sc->cpu_minmv = op->mv;
447
448 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
449 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
450 sc->cpu_maxmhz = op->mhz;
451 sc->cpu_maxmv = op->mv;
452
453 /*
454 * Set the CPU to maximum speed.
455 *
456 * We won't have thermal throttling until interrupts are enabled, but we
457 * want to run at full speed through all the device init stuff. This
458 * basically assumes that a single core can't overheat before interrupts
459 * are enabled; empirical testing shows that to be a safe assumption.
460 */
461 cpufreq_set_clock(sc, op);
462 }
463
464 static inline uint32_t
465 temp_from_count(struct imx6_anatop_softc *sc, uint32_t count)
466 {
467
468 return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
469 (sc->temp_high_val - 250) /
470 (sc->temp_room_cnt - sc->temp_high_cnt))));
471 }
472
473 static inline uint32_t
474 temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp)
475 {
476
477 return ((sc->temp_room_cnt - sc->temp_high_cnt) *
478 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
479 sc->temp_high_cnt);
480 }
481
482 static void
483 temp_update_count(struct imx6_anatop_softc *sc)
484 {
485 uint32_t val;
486
487 val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0);
488 if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID))
489 return;
490 sc->temp_last_cnt =
491 (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >>
492 IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
493 }
494
495 static int
496 temp_sysctl_handler(SYSCTL_HANDLER_ARGS)
497 {
498 struct imx6_anatop_softc *sc = arg1;
499 uint32_t t;
500
501 temp_update_count(sc);
502
503 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
504
505 return (sysctl_handle_int(oidp, &t, 0, req));
506 }
507
508 static int
509 temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
510 {
511 struct imx6_anatop_softc *sc = arg1;
512 int err;
513 uint32_t temp;
514
515 temp = sc->temp_throttle_val + TZ_ZEROC;
516 err = sysctl_handle_int(oidp, &temp, 0, req);
517 if (temp < TZ_ZEROC)
518 return (ERANGE);
519 temp -= TZ_ZEROC;
520 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
521 return (err);
522
523 /* Value changed, update counts in softc and hardware. */
524 sc->temp_throttle_val = temp;
525 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
526 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
527 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
528 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
529 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
530 (sc->temp_throttle_trigger_cnt <<
531 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
532 return (err);
533 }
534
535 static void
536 tempmon_gofast(struct imx6_anatop_softc *sc)
537 {
538
539 if (sc->cpu_curmhz < sc->cpu_maxmhz) {
540 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
541 }
542 }
543
544 static void
545 tempmon_goslow(struct imx6_anatop_softc *sc)
546 {
547
548 if (sc->cpu_curmhz > sc->cpu_minmhz) {
549 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
550 }
551 }
552
553 static int
554 tempmon_intr(void *arg)
555 {
556 struct imx6_anatop_softc *sc = arg;
557
558 /*
559 * XXX Note that this code doesn't currently run (for some mysterious
560 * reason we just never get an interrupt), so the real monitoring is
561 * done by tempmon_throttle_check().
562 */
563 tempmon_goslow(sc);
564 /* XXX Schedule callout to speed back up eventually. */
565 return (FILTER_HANDLED);
566 }
567
568 static void
569 tempmon_throttle_check(void *arg)
570 {
571 struct imx6_anatop_softc *sc = arg;
572
573 /* Lower counts are higher temperatures. */
574 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
575 tempmon_goslow(sc);
576 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
577 tempmon_gofast(sc);
578
579 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
580 0, tempmon_throttle_check, sc, 0);
581
582 }
583
584 static void
585 initialize_tempmon(struct imx6_anatop_softc *sc)
586 {
587 uint32_t cal;
588
589 /*
590 * Fetch calibration data: a sensor count at room temperature (25C),
591 * a sensor count at a high temperature, and that temperature
592 */
593 cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
594 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
595 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
596 sc->temp_high_val = (cal & 0x000000FF) * 10;
597
598 /*
599 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and
600 * reset back to max cpu freq at 5C below the trigger.
601 */
602 sc->temp_throttle_val = sc->temp_high_val - 100;
603 sc->temp_throttle_trigger_cnt =
604 temp_to_count(sc, sc->temp_throttle_val);
605 sc->temp_throttle_reset_cnt =
606 temp_to_count(sc, sc->temp_throttle_val - 50);
607
608 /*
609 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
610 * the throttle count, and begin making measurements.
611 */
612 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
613 imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
614 (sc->temp_throttle_trigger_cnt <<
615 IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
616 IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
617
618 /*
619 * XXX Note that the alarm-interrupt feature isn't working yet, so
620 * we'll use a callout handler to check at 10Hz. Make sure we have an
621 * initial temperature reading before starting up the callouts so we
622 * don't get a bogus reading of zero.
623 */
624 while (sc->temp_last_cnt == 0)
625 temp_update_count(sc);
626 sc->temp_throttle_delay = 100 * SBT_1MS;
627 callout_init(&sc->temp_throttle_callout, 0);
628 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
629 0, tempmon_throttle_check, sc, 0);
630
631 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
632 OID_AUTO, "temperature",
633 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
634 temp_sysctl_handler, "IK", "Current die temperature");
635 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx),
636 OID_AUTO, "throttle_temperature",
637 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc,
638 0, temp_throttle_sysctl_handler, "IK",
639 "Throttle CPU when exceeding this temperature");
640 }
641
642 static void
643 intr_setup(void *arg)
644 {
645 int rid;
646 struct imx6_anatop_softc *sc;
647
648 sc = arg;
649 rid = 0;
650 sc->res[IRQRES] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
651 RF_ACTIVE);
652 if (sc->res[IRQRES] != NULL) {
653 bus_setup_intr(sc->dev, sc->res[IRQRES],
654 INTR_TYPE_MISC | INTR_MPSAFE, tempmon_intr, NULL, sc,
655 &sc->temp_intrhand);
656 } else {
657 device_printf(sc->dev, "Cannot allocate IRQ resource\n");
658 }
659 config_intrhook_disestablish(&sc->intr_setup_hook);
660 }
661
662 static void
663 imx6_anatop_new_pass(device_t dev)
664 {
665 struct imx6_anatop_softc *sc;
666 const int cpu_init_pass = BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE;
667
668 /*
669 * We attach during BUS_PASS_BUS (because some day we will be a
670 * simplebus that has regulator devices as children), but some of our
671 * init work cannot be done until BUS_PASS_CPU (we rely on other devices
672 * that attach on the CPU pass).
673 */
674 sc = device_get_softc(dev);
675 if (!sc->cpu_init_done && bus_current_pass >= cpu_init_pass) {
676 sc->cpu_init_done = true;
677 cpufreq_initialize(sc);
678 initialize_tempmon(sc);
679 if (bootverbose) {
680 device_printf(sc->dev, "CPU %uMHz @ %umV\n",
681 sc->cpu_curmhz, sc->cpu_curmv);
682 }
683 }
684 bus_generic_new_pass(dev);
685 }
686
687 static int
688 imx6_anatop_detach(device_t dev)
689 {
690
691 /* This device can never detach. */
692 return (EBUSY);
693 }
694
695 static int
696 imx6_anatop_attach(device_t dev)
697 {
698 struct imx6_anatop_softc *sc;
699 int err;
700
701 sc = device_get_softc(dev);
702 sc->dev = dev;
703
704 /* Allocate bus_space resources. */
705 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
706 device_printf(dev, "Cannot allocate resources\n");
707 err = ENXIO;
708 goto out;
709 }
710
711 sc->intr_setup_hook.ich_func = intr_setup;
712 sc->intr_setup_hook.ich_arg = sc;
713 config_intrhook_establish(&sc->intr_setup_hook);
714
715 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
716 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
717 OID_AUTO, "cpu_voltage", CTLFLAG_RD,
718 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
719
720 imx6_anatop_sc = sc;
721
722 /*
723 * Other code seen on the net sets this SELFBIASOFF flag around the same
724 * time the temperature sensor is set up, although it's unclear how the
725 * two are related (if at all).
726 */
727 imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
728 IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
729
730 /*
731 * Some day, when we're ready to deal with the actual anatop regulators
732 * that are described in fdt data as children of this "bus", this would
733 * be the place to invoke a simplebus helper routine to instantiate the
734 * children from the fdt data.
735 */
736
737 err = 0;
738
739 out:
740
741 if (err != 0) {
742 bus_release_resources(dev, imx6_anatop_spec, sc->res);
743 }
744
745 return (err);
746 }
747
748 uint32_t
749 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
750 {
751 int reg;
752
753 /*
754 * Audio PLL (PLL4).
755 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
756 */
757
758 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
759 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
760 IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
761 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
762 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
763 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_NUM, mfn);
764 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO_DENOM, mfd);
765
766 return (0);
767 }
768
769 static int
770 imx6_anatop_probe(device_t dev)
771 {
772
773 if (!ofw_bus_status_okay(dev))
774 return (ENXIO);
775
776 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)
777 return (ENXIO);
778
779 device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power");
780
781 return (BUS_PROBE_DEFAULT);
782 }
783
784 uint32_t
785 imx6_get_cpu_clock(void)
786 {
787 uint32_t corediv, plldiv;
788
789 corediv = imx_ccm_get_cacrr();
790 plldiv = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
791 IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
792 return (cpufreq_mhz_from_div(imx6_anatop_sc, corediv, plldiv));
793 }
794
795 static device_method_t imx6_anatop_methods[] = {
796 /* Device interface */
797 DEVMETHOD(device_probe, imx6_anatop_probe),
798 DEVMETHOD(device_attach, imx6_anatop_attach),
799 DEVMETHOD(device_detach, imx6_anatop_detach),
800
801 /* Bus interface */
802 DEVMETHOD(bus_new_pass, imx6_anatop_new_pass),
803
804 DEVMETHOD_END
805 };
806
807 static driver_t imx6_anatop_driver = {
808 "imx6_anatop",
809 imx6_anatop_methods,
810 sizeof(struct imx6_anatop_softc)
811 };
812
813 EARLY_DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, 0, 0,
814 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
815 EARLY_DRIVER_MODULE(imx6_anatop, ofwbus, imx6_anatop_driver, 0, 0,
816 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
Cache object: 35867024df6663596374dfb767be507f
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