Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/freescale/imx/imx6_ipu.c
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1 /*- 2 * Copyright 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/clock.h> 35 #include <sys/eventhandler.h> 36 #include <sys/time.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 #include <sys/fbio.h> 44 #include <sys/consio.h> 45 46 #include <machine/bus.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/fb/fbreg.h> 53 #include <dev/vt/vt.h> 54 55 #include <dev/videomode/videomode.h> 56 #include <dev/videomode/edidvar.h> 57 58 #include <arm/freescale/imx/imx6_src.h> 59 #include <arm/freescale/imx/imx_ccmvar.h> 60 61 #include "fb_if.h" 62 #include "hdmi_if.h" 63 64 static int have_ipu = 0; 65 66 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 67 #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 68 #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 69 #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 70 #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 71 #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 72 73 #define MODE_BPP 16 74 #define MODE_PIXEL_CLOCK_INVERT 1 75 76 #define DMA_CHANNEL 23 77 #define DC_CHAN5 5 78 #define DI_PORT 0 79 80 #define IPU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 81 #define IPU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 82 #define IPU_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 83 device_get_nameunit(_sc->sc_dev), "ipu", MTX_DEF) 84 #define IPU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 85 86 #define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg)) 87 #define IPU_WRITE4(_sc, reg, value) \ 88 bus_write_4((_sc)->sc_mem_res, (reg), (value)) 89 90 #define CPMEM_BASE 0x300000 91 #define DC_TEMPL_BASE 0x380000 92 93 /* Microcode */ 94 /* Word 1 */ 95 #define TEMPLATE_SYNC(v) ((v) << 0) 96 #define TEMPLATE_GLUELOGIC(v) ((v) << 4) 97 #define TEMPLATE_MAPPING(v) ((v) << 15) 98 #define TEMPLATE_WAVEFORM(v) ((v) << 11) 99 #define GLUELOGIC_KEEP_ASSERTED (1 << 3) 100 #define GLUELOGIC_KEEP_NEGATED (1 << 2) 101 /* Word 2 */ 102 #define TEMPLATE_OPCODE(v) ((v) << 4) 103 #define OPCODE_WROD 0x18 104 #define TEMPLATE_STOP (1 << 9) 105 106 #define IPU_CONF 0x200000 107 #define IPU_CONF_DMFC_EN (1 << 10) 108 #define IPU_CONF_DC_EN (1 << 9) 109 #define IPU_CONF_DI1_EN (1 << 7) 110 #define IPU_CONF_DI0_EN (1 << 6) 111 #define IPU_CONF_DP_EN (1 << 5) 112 #define IPU_DISP_GEN 0x2000C4 113 #define DISP_GEN_DI1_CNTR_RELEASE (1 << 25) 114 #define DISP_GEN_DI0_CNTR_RELEASE (1 << 24) 115 #define DISP_GEN_MCU_MAX_BURST_STOP (1 << 22) 116 #define DISP_GEN_MCU_T_SHIFT 18 117 #define IPU_MEM_RST 0x2000DC 118 #define IPU_MEM_RST_START (1 << 31) 119 #define IPU_MEM_RST_ALL 0x807FFFFF 120 #define IPU_CH_DB_MODE_SEL_0 0x200150 121 #define IPU_CH_DB_MODE_SEL_1 0x200154 122 #define IPU_CUR_BUF_0 0x20023C 123 #define IPU_CUR_BUF_1 0x200240 124 125 #define IPU_IDMAC_CH_EN_1 0x208004 126 #define IPU_IDMAC_CH_EN_2 0x208008 127 #define IPU_IDMAC_CH_PRI_1 0x208014 128 #define IPU_IDMAC_CH_PRI_2 0x208018 129 130 #define IPU_DI0_GENERAL 0x240000 131 #define DI_CLOCK_EXTERNAL (1 << 20) 132 #define DI_GENERAL_POL_CLK (1 << 17) 133 #define DI_GENERAL_POLARITY_3 (1 << 2) 134 #define DI_GENERAL_POLARITY_2 (1 << 1) 135 #define IPU_DI0_BS_CLKGEN0 0x240004 136 #define DI_BS_CLKGEN0(_int, _frac) (((_int) << 4) | (_frac)) 137 #define IPU_DI0_BS_CLKGEN1 0x240008 138 #define DI_BS_CLKGEN1_DOWN(_int, _frac) ((((_int) << 1) | (_frac)) << 16) 139 #define IPU_DI0_SW_GEN0_1 0x24000C 140 #define DI_RUN_VALUE_M1(v) ((v) << 19) 141 #define DI_RUN_RESOLUTION(v) ((v) << 16) 142 #define DI_OFFSET_VALUE(v) ((v) << 3) 143 #define IPU_DI0_SW_GEN1_1 0x240030 144 #define DI_CNT_POLARITY_GEN_EN(v) ((v) << 29) 145 #define DI_CNT_AUTO_RELOAD (1 << 28) 146 #define DI_CNT_CLR_SEL(v) ((v) << 25) 147 #define DI_CNT_DOWN(v) ((v) << 16) 148 #define DI_CNT_POLARITY_TRIGGER_SEL(v) ((v) << 12) 149 #define DI_CNT_POLARITY_CLR_SEL(v) ((v) << 9) 150 #define IPU_DI0_SYNC_AS_GEN 0x240054 151 #define SYNC_AS_GEN_VSYNC_SEL(v) ((v) << 13) 152 #define SYNC_AS_GEN_SYNC_START(v) ((v) << 0) 153 #define IPU_DI0_DW_GEN_0 0x240058 154 #define DW_GEN_DI_ACCESS_SIZE(v) ((v) << 24) 155 #define DW_GEN_DI_COMPONENT_SIZE(v) ((v) << 16) 156 #define DW_GEN_DI_SET_MASK 3 157 #define DW_GEN_DI_PIN_15_SET(v) ((v) << 8) 158 #define IPU_DI0_DW_SET3_0 0x240118 159 #define DW_SET_DATA_CNT_DOWN(v) ((v) << 16) 160 #define DW_SET_DATA_CNT_UP(v) ((v) << 0) 161 #define IPU_DI0_STP_REP 0x240148 162 #define IPU_DI0_POL 0x240164 163 #define DI_POL_DRDY_POLARITY_15 (1 << 4) 164 #define IPU_DI0_SCR_CONF 0x240170 165 166 #define IPU_DI1_GENERAL 0x248000 167 #define IPU_DI1_BS_CLKGEN0 0x248004 168 #define IPU_DI1_BS_CLKGEN1 0x248008 169 #define IPU_DI1_SW_GEN0_1 0x24800C 170 #define IPU_DI1_SW_GEN1_1 0x248030 171 #define IPU_DI1_SYNC_AS_GEN 0x248054 172 #define IPU_DI1_DW_GEN_0 0x248058 173 #define IPU_DI1_POL 0x248164 174 #define IPU_DI1_DW_SET3_0 0x248118 175 #define IPU_DI1_STP_REP 0x248148 176 #define IPU_DI1_SCR_CONF 0x248170 177 #define DMFC_RD_CHAN 0x260000 178 #define DMFC_WR_CHAN 0x260004 179 #define DMFC_WR_CHAN_BURST_SIZE_32 (0 << 6) 180 #define DMFC_WR_CHAN_BURST_SIZE_16 (1 << 6) 181 #define DMFC_WR_CHAN_BURST_SIZE_8 (2 << 6) 182 #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) 183 #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) 184 #define DMFC_WR_CHAN_FIFO_SIZE_128 (2 << 3) 185 #define DMFC_WR_CHAN_DEF 0x260008 186 #define DMFC_WR_CHAN_DEF_WM_CLR_2C(v) ((v) << 29) 187 #define DMFC_WR_CHAN_DEF_WM_CLR_1C(v) ((v) << 21) 188 #define DMFC_WR_CHAN_DEF_WM_CLR_2(v) ((v) << 13) 189 #define DMFC_WR_CHAN_DEF_WM_CLR_1(v) ((v) << 5) 190 #define DMFC_WR_CHAN_DEF_WM_SET_1(v) ((v) << 2) 191 #define DMFC_WR_CHAN_DEF_WM_EN_1 (1 << 1) 192 #define DMFC_DP_CHAN 0x26000C 193 #define DMFC_DP_CHAN_BURST_SIZE_8 2 194 #define DMFC_DP_CHAN_FIFO_SIZE_256 1 195 #define DMFC_DP_CHAN_FIFO_SIZE_128 2 196 #define DMFC_DP_CHAN_BURST_SIZE_5F(v) ((v) << 14) 197 #define DMFC_DP_CHAN_FIFO_SIZE_5F(v) ((v) << 11) 198 #define DMFC_DP_CHAN_ST_ADDR_SIZE_5F(v) ((v) << 8) 199 #define DMFC_DP_CHAN_BURST_SIZE_5B(v) ((v) << 6) 200 #define DMFC_DP_CHAN_FIFO_SIZE_5B(v) ((v) << 3) 201 #define DMFC_DP_CHAN_ST_ADDR_SIZE_5B(v) ((v) << 0) 202 #define DMFC_DP_CHAN_DEF 0x260010 203 #define DMFC_DP_CHAN_DEF_WM_CLR_6F(v) ((v) << 29) 204 #define DMFC_DP_CHAN_DEF_WM_CLR_6B(v) ((v) << 21) 205 #define DMFC_DP_CHAN_DEF_WM_CLR_5F(v) ((v) << 13) 206 #define DMFC_DP_CHAN_DEF_WM_SET_5F(v) ((v) << 10) 207 #define DMFC_DP_CHAN_DEF_WM_EN_5F (1 << 9) 208 #define DMFC_DP_CHAN_DEF_WM_CLR_5B(v) ((v) << 5) 209 #define DMFC_DP_CHAN_DEF_WM_SET_5B(v) ((v) << 2) 210 #define DMFC_DP_CHAN_DEF_WM_EN_5B (1 << 1) 211 #define DMFC_GENERAL_1 0x260014 212 #define DMFC_GENERAL_1_WAIT4EOT_5B (1 << 20) 213 #define DMFC_IC_CTRL 0x26001C 214 #define DMFC_IC_CTRL_DISABLED 0x2 215 216 #define DC_WRITE_CH_CONF_1 0x0025801C 217 #define WRITE_CH_CONF_PROG_CHAN_TYP_MASK (7 << 5) 218 #define WRITE_CH_CONF_PROG_CHAN_NORMAL (4 << 5) 219 #define DC_WRITE_CH_ADDR_1 0x00258020 220 #define DC_WRITE_CH_CONF_5 0x0025805C 221 #define WRITE_CH_CONF_PROG_DISP_ID(v) ((v) << 3) 222 #define WRITE_CH_CONF_PROG_DI_ID(v) ((v) << 2) 223 #define WRITE_CH_CONF_PROG_W_SIZE(v) (v) 224 #define DC_WRITE_CH_ADDR_5 0x00258060 225 #define DC_RL0_CH_5 0x00258064 226 #define DC_GEN 0x002580D4 227 #define DC_GEN_SYNC_PRIORITY (1 << 7) 228 #define DC_GEN_ASYNC (0 << 1) 229 #define DC_GEN_SYNC (2 << 1) 230 #define DC_DISP_CONF2(di) (0x002580E8 + (di) * 4) 231 #define DC_MAP_CONF_0 0x00258108 232 #define DC_MAP_CONF_15 0x00258144 233 #define DC_MAP_CONF_VAL(map) (DC_MAP_CONF_15 + ((map) / 2) * sizeof(uint32_t)) 234 #define MAP_CONF_VAL_MASK 0xffff 235 #define DC_MAP_CONF_PTR(ptr) (DC_MAP_CONF_0 + ((ptr) / 2) * sizeof(uint32_t)) 236 #define MAP_CONF_PTR_MASK 0x1f 237 238 #define DI_COUNTER_INT_HSYNC 1 239 #define DI_COUNTER_HSYNC 2 240 #define DI_COUNTER_VSYNC 3 241 #define DI_COUNTER_AD_0 4 242 #define DI_COUNTER_AD_1 5 243 244 #define DI_SYNC_NONE 0 245 #define DI_SYNC_CLK 1 246 #define DI_SYNC_COUNTER(c) ((c) + 1) 247 248 struct ipu_cpmem_word { 249 uint32_t data[5]; 250 uint32_t padding[3]; 251 }; 252 253 struct ipu_cpmem_ch_param { 254 struct ipu_cpmem_word word[2]; 255 }; 256 257 #define CH_PARAM_RESET(param) memset(param, 0, sizeof(*param)) 258 #define IPU_READ_CH_PARAM(_sc, ch, param) bus_read_region_4( \ 259 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ 260 (uint32_t*)param, sizeof(*param) / 4) 261 #define IPU_WRITE_CH_PARAM(_sc, ch, param) bus_write_region_4( \ 262 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ 263 (uint32_t*)param, sizeof(*param) / 4) 264 265 #define CH_PARAM_SET_FW(param, v) ipu_ch_param_set_value((param), \ 266 0, 125, 13, (v)) 267 #define CH_PARAM_SET_FH(param, v) ipu_ch_param_set_value((param), \ 268 0, 138, 12, (v)) 269 #define CH_PARAM_SET_SLY(param, v) ipu_ch_param_set_value((param), \ 270 1, 102, 14, (v)) 271 #define CH_PARAM_SET_EBA0(param, v) ipu_ch_param_set_value((param), \ 272 1, 0, 29, (v)) 273 #define CH_PARAM_SET_EBA1(param, v) ipu_ch_param_set_value((param), \ 274 1, 29, 29, (v)) 275 #define CH_PARAM_SET_BPP(param, v) ipu_ch_param_set_value((param), \ 276 0, 107, 3, (v)) 277 #define CH_PARAM_SET_PFS(param, v) ipu_ch_param_set_value((param), \ 278 1, 85, 4, (v)) 279 #define CH_PARAM_SET_NPB(param, v) ipu_ch_param_set_value((param), \ 280 1, 78, 7, (v)) 281 #define CH_PARAM_SET_UBO(param, v) ipu_ch_param_set_value((param), \ 282 0, 46, 22, (v)) 283 #define CH_PARAM_SET_VBO(param, v) ipu_ch_param_set_value((param), \ 284 0, 68, 22, (v)) 285 286 #define CH_PARAM_SET_RED_WIDTH(param, v) ipu_ch_param_set_value((param), \ 287 1, 116, 3, (v)) 288 #define CH_PARAM_SET_RED_OFFSET(param, v) ipu_ch_param_set_value((param), \ 289 1, 128, 5, (v)) 290 291 #define CH_PARAM_SET_GREEN_WIDTH(param, v) ipu_ch_param_set_value((param), \ 292 1, 119, 3, (v)) 293 #define CH_PARAM_SET_GREEN_OFFSET(param, v) ipu_ch_param_set_value((param), \ 294 1, 133, 5, (v)) 295 296 #define CH_PARAM_SET_BLUE_WIDTH(param, v) ipu_ch_param_set_value((param), \ 297 1, 122, 3, (v)) 298 #define CH_PARAM_SET_BLUE_OFFSET(param, v) ipu_ch_param_set_value((param), \ 299 1, 138, 5, (v)) 300 301 #define CH_PARAM_SET_ALPHA_WIDTH(param, v) ipu_ch_param_set_value((param), \ 302 1, 125, 3, (v)) 303 #define CH_PARAM_SET_ALPHA_OFFSET(param, v) ipu_ch_param_set_value((param), \ 304 1, 143, 5, (v)) 305 306 #define CH_PARAM_GET_FW(param) ipu_ch_param_get_value((param), \ 307 0, 125, 13) 308 #define CH_PARAM_GET_FH(param) ipu_ch_param_get_value((param), \ 309 0, 138, 12) 310 #define CH_PARAM_GET_SLY(param) ipu_ch_param_get_value((param), \ 311 1, 102, 14) 312 #define CH_PARAM_GET_EBA0(param) ipu_ch_param_get_value((param), \ 313 1, 0, 29) 314 #define CH_PARAM_GET_EBA1(param) ipu_ch_param_get_value((param), \ 315 1, 29, 29) 316 #define CH_PARAM_GET_BPP(param) ipu_ch_param_get_value((param), \ 317 0, 107, 3) 318 #define CH_PARAM_GET_PFS(param) ipu_ch_param_get_value((param), \ 319 1, 85, 4) 320 #define CH_PARAM_GET_NPB(param) ipu_ch_param_get_value((param), \ 321 1, 78, 7) 322 #define CH_PARAM_GET_UBO(param) ipu_ch_param_get_value((param), \ 323 0, 46, 22) 324 #define CH_PARAM_GET_VBO(param) ipu_ch_param_get_value((param), \ 325 0, 68, 22) 326 327 #define CH_PARAM_GET_RED_WIDTH(param) ipu_ch_param_get_value((param), \ 328 1, 116, 3) 329 #define CH_PARAM_GET_RED_OFFSET(param) ipu_ch_param_get_value((param), \ 330 1, 128, 5) 331 332 #define CH_PARAM_GET_GREEN_WIDTH(param) ipu_ch_param_get_value((param), \ 333 1, 119, 3) 334 #define CH_PARAM_GET_GREEN_OFFSET(param) ipu_ch_param_get_value((param), \ 335 1, 133, 5) 336 337 #define CH_PARAM_GET_BLUE_WIDTH(param) ipu_ch_param_get_value((param), \ 338 1, 122, 3) 339 #define CH_PARAM_GET_BLUE_OFFSET(param) ipu_ch_param_get_value((param), \ 340 1, 138, 5) 341 342 #define CH_PARAM_GET_ALPHA_WIDTH(param) ipu_ch_param_get_value((param), \ 343 1, 125, 3) 344 #define CH_PARAM_GET_ALPHA_OFFSET(param) ipu_ch_param_get_value((param), \ 345 1, 143, 5) 346 347 #define IPU_PIX_FORMAT_BPP_32 0 348 #define IPU_PIX_FORMAT_BPP_24 1 349 #define IPU_PIX_FORMAT_BPP_18 2 350 #define IPU_PIX_FORMAT_BPP_16 3 351 #define IPU_PIX_FORMAT_BPP_12 4 352 #define IPU_PIX_FORMAT_BPP_8 5 353 #define IPU_PIX_FORMAT_BPP_ 354 355 #define IPU_PIX_FORMAT_RGB 7 356 357 enum dc_event_t { 358 DC_EVENT_NF = 0, 359 DC_EVENT_NL, 360 DC_EVENT_EOF, 361 DC_EVENT_NFIELD, 362 DC_EVENT_EOL, 363 DC_EVENT_EOFIELD, 364 DC_EVENT_NEW_ADDR, 365 DC_EVENT_NEW_CHAN, 366 DC_EVENT_NEW_DATA 367 }; 368 369 struct ipu_softc { 370 device_t sc_dev; 371 struct resource *sc_mem_res; 372 int sc_mem_rid; 373 struct resource *sc_irq_res; 374 int sc_irq_rid; 375 void *sc_intr_hl; 376 struct mtx sc_mtx; 377 struct fb_info sc_fb_info; 378 const struct videomode *sc_mode; 379 380 /* Framebuffer */ 381 bus_dma_tag_t sc_dma_tag; 382 bus_dmamap_t sc_dma_map; 383 size_t sc_fb_size; 384 bus_addr_t sc_fb_phys; 385 uint8_t *sc_fb_base; 386 387 /* HDMI */ 388 eventhandler_tag sc_hdmi_evh; 389 }; 390 391 static void 392 ipu_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 393 { 394 bus_addr_t *addr; 395 396 if (err) 397 return; 398 399 addr = (bus_addr_t*)arg; 400 *addr = segs[0].ds_addr; 401 } 402 403 static void 404 ipu_ch_param_set_value(struct ipu_cpmem_ch_param *param, 405 int word, unsigned int offset, int len, uint32_t value) 406 { 407 uint32_t datapos, bitpos, mask; 408 uint32_t data, data2; 409 410 KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); 411 412 datapos = offset / 32; 413 bitpos = offset % 32; 414 415 mask = (1 << len) - 1; 416 data = param->word[word].data[datapos]; 417 data &= ~(mask << bitpos); 418 data |= (value << bitpos); 419 param->word[word].data[datapos] = data; 420 421 if ((bitpos + len) > 32) { 422 len = bitpos + len - 32; 423 mask = (1UL << len) - 1; 424 data2 = param->word[word].data[datapos + 1]; 425 data2 &= mask; 426 data2 |= (value >> (32 - bitpos)); 427 param->word[word].data[datapos + 1] = data2; 428 } 429 } 430 431 #ifdef DEBUG 432 static uint32_t 433 ipu_ch_param_get_value(struct ipu_cpmem_ch_param *param, 434 int word, unsigned int offset, int len) 435 { 436 uint32_t datapos, bitpos, mask; 437 uint32_t data, data2; 438 439 KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); 440 441 datapos = offset / 32; 442 bitpos = offset % 32; 443 mask = (1UL << len) - 1; 444 data = param->word[word].data[datapos]; 445 data = data >> bitpos; 446 data &= mask; 447 if ((bitpos + len) > 32) { 448 len = bitpos + len - 32; 449 mask = (1UL << len) - 1; 450 data2 = param->word[word].data[datapos + 1]; 451 data2 &= mask; 452 data |= (data2 << (32 - bitpos)); 453 } 454 455 return (data); 456 } 457 458 static void 459 ipu_print_channel(struct ipu_cpmem_ch_param *param) 460 { 461 int offset0[] = {0, 10, 19, 32, 44, 45, 46, 68, 90, 94, 95, 113, 114, 117, 119, 120, 121, 122, 123, 124, 125, 138, 150, 151, -1}; 462 int offset1[] = {0, 29, 58, 78, 85, 89, 90, 93, 95, 102, 116, 119, 122, 125, 128, 133, 138, 143, 148, 149, 150, -1}; 463 printf("WORD0: %08x %08x %08x %08x %08x\n", 464 param->word[0].data[0], param->word[0].data[1], 465 param->word[0].data[2], param->word[0].data[3], 466 param->word[0].data[4]); 467 printf("WORD1: %08x %08x %08x %08x %08x\n", 468 param->word[1].data[0], param->word[1].data[1], 469 param->word[1].data[2], param->word[1].data[3], 470 param->word[1].data[4]); 471 472 for (int i = 0; offset0[i + 1] != -1; i++) { 473 int len = offset0[i + 1] - offset0[i]; 474 printf("W0[%d:%d] = %d\n", offset0[i], 475 offset0[i] + len - 1, 476 ipu_ch_param_get_value(param, 0, offset0[i], len) 477 ); 478 } 479 480 for (int i = 0; offset1[i + 1] != -1; i++) { 481 int len = offset1[i + 1] - offset1[i]; 482 printf("W1[%d:%d] = %d\n", offset1[i], 483 offset1[i] + len - 1, 484 ipu_ch_param_get_value(param, 1, offset1[i], len) 485 ); 486 } 487 488 printf("FW: %d\n", CH_PARAM_GET_FW(param)); 489 printf("FH: %d\n", CH_PARAM_GET_FH(param)); 490 printf("SLY: %d\n", CH_PARAM_GET_SLY(param)); 491 printf("EBA0: 0x%08x\n", CH_PARAM_GET_EBA0(param)); 492 printf("EBA1: 0x%08x\n", CH_PARAM_GET_EBA1(param)); 493 printf("BPP: %d\n", CH_PARAM_GET_BPP(param)); 494 printf("PFS: %d\n", CH_PARAM_GET_PFS(param)); 495 printf("NPB: %d\n", CH_PARAM_GET_NPB(param)); 496 printf("UBO: %d\n", CH_PARAM_GET_UBO(param)); 497 printf("VBO: %d\n", CH_PARAM_GET_VBO(param)); 498 printf("RED: %d bits @%d\n", CH_PARAM_GET_RED_WIDTH(param) + 1, 499 CH_PARAM_GET_RED_OFFSET(param)); 500 printf("GREEN: %d bits @%d\n", CH_PARAM_GET_GREEN_WIDTH(param) + 1, 501 CH_PARAM_GET_GREEN_OFFSET(param)); 502 printf("BLUE: %d bits @%d\n", CH_PARAM_GET_BLUE_WIDTH(param) + 1, 503 CH_PARAM_GET_BLUE_OFFSET(param)); 504 printf("ALPHA: %d bits @%d\n", CH_PARAM_GET_ALPHA_WIDTH(param) + 1, 505 CH_PARAM_GET_ALPHA_OFFSET(param)); 506 } 507 #endif 508 509 static void 510 ipu_di_enable(struct ipu_softc *sc, int di) 511 { 512 uint32_t flag, reg; 513 514 flag = di ? DISP_GEN_DI1_CNTR_RELEASE : DISP_GEN_DI0_CNTR_RELEASE; 515 reg = IPU_READ4(sc, IPU_DISP_GEN); 516 reg |= flag; 517 IPU_WRITE4(sc, IPU_DISP_GEN, reg); 518 } 519 520 static void 521 ipu_config_wave_gen_0(struct ipu_softc *sc, int di, 522 int wave_gen, int run_value, int run_res, 523 int offset_value, int offset_res) 524 { 525 uint32_t addr, reg; 526 527 addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) 528 + (wave_gen - 1) * sizeof(uint32_t); 529 reg = DI_RUN_VALUE_M1(run_value) | 530 DI_RUN_RESOLUTION(run_res) | 531 DI_OFFSET_VALUE(offset_value) | offset_res; 532 IPU_WRITE4(sc, addr, reg); 533 } 534 535 static void 536 ipu_config_wave_gen_1(struct ipu_softc *sc, int di, int wave_gen, 537 int repeat_count, int cnt_clr_src, 538 int cnt_polarity_gen_en, 539 int cnt_polarity_clr_src, 540 int cnt_polarity_trigger_src, 541 int cnt_up, int cnt_down) 542 { 543 uint32_t addr, reg; 544 545 addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) 546 + (wave_gen - 1) * sizeof(uint32_t); 547 reg = DI_CNT_POLARITY_GEN_EN(cnt_polarity_gen_en) | 548 DI_CNT_CLR_SEL(cnt_clr_src) | 549 DI_CNT_POLARITY_TRIGGER_SEL(cnt_polarity_trigger_src) | 550 DI_CNT_POLARITY_CLR_SEL(cnt_polarity_clr_src); 551 reg |= DI_CNT_DOWN(cnt_down) | cnt_up; 552 if (repeat_count == 0) 553 reg |= DI_CNT_AUTO_RELOAD; 554 IPU_WRITE4(sc, addr, reg); 555 556 addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) 557 + (wave_gen - 1) / 2 * sizeof(uint32_t); 558 reg = IPU_READ4(sc, addr); 559 if (wave_gen % 2) { 560 reg &= ~(0xffff); 561 reg |= repeat_count; 562 } 563 else { 564 reg &= ~(0xffff << 16); 565 reg |= (repeat_count << 16); 566 } 567 IPU_WRITE4(sc, addr, reg); 568 } 569 570 static void 571 ipu_reset_wave_gen(struct ipu_softc *sc, int di, 572 int wave_gen) 573 { 574 uint32_t addr, reg; 575 576 addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) 577 + (wave_gen - 1) * sizeof(uint32_t); 578 IPU_WRITE4(sc, addr, 0); 579 580 addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) 581 + (wave_gen - 1) * sizeof(uint32_t); 582 IPU_WRITE4(sc, addr, 0); 583 584 addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) 585 + (wave_gen - 1) / 2 * sizeof(uint32_t); 586 reg = IPU_READ4(sc, addr); 587 if (wave_gen % 2) 588 reg &= ~(0xffff); 589 else 590 reg &= ~(0xffff << 16); 591 IPU_WRITE4(sc, addr, reg); 592 } 593 594 static void 595 ipu_init_microcode_template(struct ipu_softc *sc, int di, int map) 596 { 597 uint32_t addr; 598 uint32_t w1, w2; 599 int i, word; 600 int glue; 601 602 word = di ? 2 : 5; 603 604 for (i = 0; i < 3; i++) { 605 if (i == 0) 606 glue = GLUELOGIC_KEEP_ASSERTED; 607 else if (i == 1) 608 glue = GLUELOGIC_KEEP_NEGATED; 609 else if (i == 2) 610 glue = 0; 611 612 w1 = TEMPLATE_SYNC(5) | 613 TEMPLATE_GLUELOGIC(glue) | 614 TEMPLATE_WAVEFORM(1) | /* wave unit 0 */ 615 TEMPLATE_MAPPING(map + 1); 616 /* operand is zero */ 617 618 /* Write data to DI and Hold data in register */ 619 w2 = TEMPLATE_OPCODE(OPCODE_WROD) | 620 TEMPLATE_STOP; 621 622 addr = DC_TEMPL_BASE + (word + i) * 2 * sizeof(uint32_t); 623 IPU_WRITE4(sc, addr, w1); 624 IPU_WRITE4(sc, addr + sizeof(uint32_t), w2); 625 } 626 } 627 628 static uint32_t 629 ipu_calc_divisor(uint32_t reference, uint32_t freq) 630 { 631 uint32_t div, i; 632 uint32_t delta, min_delta; 633 634 min_delta = freq; 635 div = 255; 636 637 for (i = 1; i < 255; i++) { 638 delta = abs(reference/i - freq); 639 if (delta < min_delta) { 640 div = i; 641 min_delta = delta; 642 } 643 } 644 645 return (div); 646 } 647 648 static void 649 ipu_config_timing(struct ipu_softc *sc, int di) 650 { 651 uint32_t div; 652 uint32_t di_scr_conf; 653 uint32_t gen_offset, gen; 654 uint32_t as_gen_offset, as_gen; 655 uint32_t dw_gen_offset, dw_gen; 656 uint32_t dw_set_offset, dw_set; 657 uint32_t bs_clkgen_offset; 658 int map; 659 uint32_t freq; 660 661 freq = sc->sc_mode->dot_clock * 1000; 662 663 div = ipu_calc_divisor(imx_ccm_ipu_hz(), freq); 664 map = 0; 665 666 bs_clkgen_offset = di ? IPU_DI1_BS_CLKGEN0 : IPU_DI0_BS_CLKGEN0; 667 IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0)); 668 /* half of the divider */ 669 IPU_WRITE4(sc, bs_clkgen_offset + 4, DI_BS_CLKGEN1_DOWN(div / 2, div % 2)); 670 671 /* Setup wave generator */ 672 dw_gen_offset = di ? IPU_DI1_DW_GEN_0 : IPU_DI0_DW_GEN_0; 673 dw_gen = DW_GEN_DI_ACCESS_SIZE(div - 1) | DW_GEN_DI_COMPONENT_SIZE(div - 1); 674 dw_gen &= ~DW_GEN_DI_PIN_15_SET(DW_GEN_DI_SET_MASK); 675 dw_gen |= DW_GEN_DI_PIN_15_SET(3); /* set 3*/ 676 IPU_WRITE4(sc, dw_gen_offset, dw_gen); 677 678 dw_set_offset = di ? IPU_DI1_DW_SET3_0 : IPU_DI0_DW_SET3_0; 679 dw_set = DW_SET_DATA_CNT_DOWN(div * 2) | DW_SET_DATA_CNT_UP(0); 680 IPU_WRITE4(sc, dw_set_offset, dw_set); 681 682 /* DI_COUNTER_INT_HSYNC */ 683 ipu_config_wave_gen_0(sc, di, DI_COUNTER_INT_HSYNC, 684 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE); 685 ipu_config_wave_gen_1(sc, di, DI_COUNTER_INT_HSYNC, 686 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 687 688 /* DI_COUNTER_HSYNC */ 689 ipu_config_wave_gen_0(sc, di, DI_COUNTER_HSYNC, 690 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK); 691 ipu_config_wave_gen_1(sc, di, DI_COUNTER_HSYNC, 692 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, DI_SYNC_CLK, 693 0, MODE_HSW(sc->sc_mode) * 2); 694 695 /* DI_COUNTER_VSYNC */ 696 ipu_config_wave_gen_0(sc, di, DI_COUNTER_VSYNC, 697 sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 698 0, DI_SYNC_NONE); 699 ipu_config_wave_gen_1(sc, di, DI_COUNTER_VSYNC, 700 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, 701 DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 702 0, MODE_VSW(sc->sc_mode) * 2); 703 704 di_scr_conf = di ? IPU_DI1_SCR_CONF : IPU_DI0_SCR_CONF; 705 IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1); 706 707 /* TODO: update DI_SCR_CONF */ 708 709 /* Active Data 0 */ 710 ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_0, 711 0, DI_SYNC_COUNTER(DI_COUNTER_HSYNC), 712 MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC)); 713 ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_0, 714 sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC), 715 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 716 717 ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_1, 718 0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK); 719 ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_1, 720 sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0), 721 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 722 723 ipu_reset_wave_gen(sc, di, 6); 724 ipu_reset_wave_gen(sc, di, 7); 725 ipu_reset_wave_gen(sc, di, 8); 726 ipu_reset_wave_gen(sc, di, 9); 727 728 ipu_init_microcode_template(sc, di, map); 729 730 gen_offset = di ? IPU_DI1_GENERAL : IPU_DI0_GENERAL; 731 gen = IPU_READ4(sc, gen_offset); 732 733 if (sc->sc_mode->flags & VID_NHSYNC) 734 gen &= ~DI_GENERAL_POLARITY_2; 735 else /* active high */ 736 gen |= DI_GENERAL_POLARITY_2; 737 738 if (sc->sc_mode->flags & VID_NVSYNC) 739 gen &= ~DI_GENERAL_POLARITY_3; 740 else /* active high */ 741 gen |= DI_GENERAL_POLARITY_3; 742 743 if (MODE_PIXEL_CLOCK_INVERT) 744 gen &= ~DI_GENERAL_POL_CLK; 745 else 746 gen |= DI_GENERAL_POL_CLK; 747 748 /* Use LDB clock to drive pixel clock */ 749 gen |= DI_CLOCK_EXTERNAL; 750 751 IPU_WRITE4(sc, gen_offset, gen); 752 753 as_gen_offset = di ? IPU_DI1_SYNC_AS_GEN : IPU_DI0_SYNC_AS_GEN; 754 as_gen = SYNC_AS_GEN_VSYNC_SEL(DI_COUNTER_VSYNC - 1) | 755 SYNC_AS_GEN_SYNC_START(2); 756 IPU_WRITE4(sc, as_gen_offset, as_gen); 757 758 IPU_WRITE4(sc, (di ? IPU_DI1_POL : IPU_DI0_POL), DI_POL_DRDY_POLARITY_15); 759 760 IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay); 761 } 762 763 static void 764 ipu_dc_enable(struct ipu_softc *sc) 765 { 766 uint32_t conf; 767 768 /* channel 1 uses DI1 */ 769 IPU_WRITE4(sc, DC_WRITE_CH_CONF_1, WRITE_CH_CONF_PROG_DI_ID(1)); 770 771 conf = IPU_READ4(sc, DC_WRITE_CH_CONF_5); 772 conf &= ~WRITE_CH_CONF_PROG_CHAN_TYP_MASK; 773 conf |= WRITE_CH_CONF_PROG_CHAN_NORMAL; 774 IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); 775 } 776 777 static void 778 ipu_dc_link_event(struct ipu_softc *sc, int event, int addr, int priority) 779 { 780 uint32_t reg; 781 int offset; 782 int shift; 783 784 if (event % 2) 785 shift = 16; 786 else 787 shift = 0; 788 789 offset = DC_RL0_CH_5 + (event / 2) * sizeof(uint32_t); 790 791 reg = IPU_READ4(sc, offset); 792 reg &= ~(0xFFFF << shift); 793 reg |= ((addr << 8) | priority) << shift; 794 IPU_WRITE4(sc, offset, reg); 795 } 796 797 static void 798 ipu_dc_setup_map(struct ipu_softc *sc, int map, 799 int byte, int offset, int mask) 800 { 801 uint32_t reg, shift, ptr; 802 803 ptr = map * 3 + byte; 804 805 reg = IPU_READ4(sc, DC_MAP_CONF_VAL(ptr)); 806 if (ptr & 1) 807 shift = 16; 808 else 809 shift = 0; 810 reg &= ~(0xffff << shift); 811 reg |= ((offset << 8) | mask) << shift; 812 IPU_WRITE4(sc, DC_MAP_CONF_VAL(ptr), reg); 813 814 reg = IPU_READ4(sc, DC_MAP_CONF_PTR(map)); 815 if (map & 1) 816 shift = 16 + 5 * byte; 817 else 818 shift = 5 * byte; 819 reg &= ~(MAP_CONF_PTR_MASK << shift); 820 reg |= (ptr) << shift; 821 IPU_WRITE4(sc, DC_MAP_CONF_PTR(map), reg); 822 } 823 824 static void 825 ipu_dc_reset_map(struct ipu_softc *sc, int map) 826 { 827 uint32_t reg, shift; 828 829 reg = IPU_READ4(sc, DC_MAP_CONF_VAL(map)); 830 if (map & 1) 831 shift = 16; 832 else 833 shift = 0; 834 reg &= ~(MAP_CONF_VAL_MASK << shift); 835 IPU_WRITE4(sc, DC_MAP_CONF_VAL(map), reg); 836 } 837 838 static void 839 ipu_dc_init(struct ipu_softc *sc, int di_port) 840 { 841 int addr; 842 uint32_t conf; 843 844 if (di_port) 845 addr = 2; 846 else 847 addr = 5; 848 849 ipu_dc_link_event(sc, DC_EVENT_NL, addr, 3); 850 ipu_dc_link_event(sc, DC_EVENT_EOL, addr + 1, 2); 851 ipu_dc_link_event(sc, DC_EVENT_NEW_DATA, addr + 2, 1); 852 ipu_dc_link_event(sc, DC_EVENT_NF, 0, 0); 853 ipu_dc_link_event(sc, DC_EVENT_NFIELD, 0, 0); 854 ipu_dc_link_event(sc, DC_EVENT_EOF, 0, 0); 855 ipu_dc_link_event(sc, DC_EVENT_EOFIELD, 0, 0); 856 ipu_dc_link_event(sc, DC_EVENT_NEW_CHAN, 0, 0); 857 ipu_dc_link_event(sc, DC_EVENT_NEW_ADDR, 0, 0); 858 859 conf = WRITE_CH_CONF_PROG_W_SIZE(0x02) | 860 WRITE_CH_CONF_PROG_DISP_ID(DI_PORT) | 861 WRITE_CH_CONF_PROG_DI_ID(DI_PORT); 862 863 IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); 864 IPU_WRITE4(sc, DC_WRITE_CH_ADDR_5, 0x00000000); 865 IPU_WRITE4(sc, DC_GEN, DC_GEN_SYNC_PRIORITY | DC_GEN_SYNC); /* High priority, sync */ 866 } 867 868 static void 869 ipu_init_buffer(struct ipu_softc *sc) 870 { 871 struct ipu_cpmem_ch_param param; 872 uint32_t stride; 873 uint32_t reg, db_mode_sel, cur_buf; 874 875 stride = sc->sc_mode->hdisplay * MODE_BPP / 8; 876 877 /* init channel parameters */ 878 CH_PARAM_RESET(¶m); 879 /* XXX: interlaced modes are not supported yet */ 880 CH_PARAM_SET_FW(¶m, sc->sc_mode->hdisplay - 1); 881 CH_PARAM_SET_FH(¶m, sc->sc_mode->vdisplay - 1); 882 CH_PARAM_SET_SLY(¶m, stride - 1); 883 884 CH_PARAM_SET_EBA0(¶m, (sc->sc_fb_phys >> 3)); 885 CH_PARAM_SET_EBA1(¶m, (sc->sc_fb_phys >> 3)); 886 887 CH_PARAM_SET_BPP(¶m, IPU_PIX_FORMAT_BPP_16); 888 CH_PARAM_SET_PFS(¶m, IPU_PIX_FORMAT_RGB); 889 /* 16 pixels per burst access */ 890 CH_PARAM_SET_NPB(¶m, 16 - 1); 891 892 CH_PARAM_SET_RED_OFFSET(¶m, 0); 893 CH_PARAM_SET_RED_WIDTH(¶m, 5 - 1); 894 CH_PARAM_SET_GREEN_OFFSET(¶m, 5); 895 CH_PARAM_SET_GREEN_WIDTH(¶m, 6 - 1); 896 CH_PARAM_SET_BLUE_OFFSET(¶m, 11); 897 CH_PARAM_SET_BLUE_WIDTH(¶m, 5 - 1); 898 CH_PARAM_SET_ALPHA_OFFSET(¶m, 16); 899 CH_PARAM_SET_ALPHA_WIDTH(¶m, 8 - 1); 900 901 CH_PARAM_SET_UBO(¶m, 0); 902 CH_PARAM_SET_VBO(¶m, 0); 903 904 IPU_WRITE_CH_PARAM(sc, DMA_CHANNEL, ¶m); 905 #ifdef DEBUG 906 ipu_print_channel(¶m); 907 #endif 908 909 /* init DMFC */ 910 IPU_WRITE4(sc, DMFC_IC_CTRL, DMFC_IC_CTRL_DISABLED); 911 /* High resolution DP */ 912 IPU_WRITE4(sc, DMFC_WR_CHAN, DMFC_WR_CHAN_BURST_SIZE_8 | 913 DMFC_WR_CHAN_FIFO_SIZE_128); 914 IPU_WRITE4(sc, DMFC_WR_CHAN_DEF, DMFC_WR_CHAN_DEF_WM_CLR_2C(1) | 915 DMFC_WR_CHAN_DEF_WM_CLR_1C(1) | 916 DMFC_WR_CHAN_DEF_WM_CLR_2(1) | 917 DMFC_WR_CHAN_DEF_WM_CLR_1(7) | 918 DMFC_WR_CHAN_DEF_WM_SET_1(5) | 919 DMFC_WR_CHAN_DEF_WM_EN_1); 920 921 IPU_WRITE4(sc, DMFC_DP_CHAN, 922 DMFC_DP_CHAN_BURST_SIZE_5F(DMFC_DP_CHAN_BURST_SIZE_8) | 923 DMFC_DP_CHAN_FIFO_SIZE_5F(DMFC_DP_CHAN_FIFO_SIZE_128) | 924 DMFC_DP_CHAN_ST_ADDR_SIZE_5F(6) /* segment 6 */ | 925 DMFC_DP_CHAN_BURST_SIZE_5B(DMFC_DP_CHAN_BURST_SIZE_8) | 926 DMFC_DP_CHAN_FIFO_SIZE_5B(DMFC_DP_CHAN_FIFO_SIZE_256) | 927 DMFC_DP_CHAN_ST_ADDR_SIZE_5B(2) /* segment 2 */); 928 929 IPU_WRITE4(sc, DMFC_DP_CHAN_DEF, DMFC_DP_CHAN_DEF_WM_CLR_6F(1) | 930 DMFC_DP_CHAN_DEF_WM_CLR_6B(1) | 931 DMFC_DP_CHAN_DEF_WM_CLR_5F(7) | 932 DMFC_DP_CHAN_DEF_WM_SET_5F(5) | 933 DMFC_DP_CHAN_DEF_WM_EN_5F | 934 DMFC_DP_CHAN_DEF_WM_CLR_5B(7) | 935 DMFC_DP_CHAN_DEF_WM_SET_5B(5) | 936 DMFC_DP_CHAN_DEF_WM_EN_5B); 937 938 reg = IPU_READ4(sc, DMFC_GENERAL_1); 939 reg &= ~(DMFC_GENERAL_1_WAIT4EOT_5B); 940 IPU_WRITE4(sc, DMFC_GENERAL_1, reg); 941 942 /* XXX: set priority? */ 943 944 /* Set single buffer mode */ 945 if (DMA_CHANNEL < 32) { 946 db_mode_sel = IPU_CH_DB_MODE_SEL_0; 947 cur_buf = IPU_CUR_BUF_0; 948 } else { 949 db_mode_sel = IPU_CH_DB_MODE_SEL_1; 950 cur_buf = IPU_CUR_BUF_1; 951 } 952 953 reg = IPU_READ4(sc, db_mode_sel); 954 reg |= (1UL << (DMA_CHANNEL & 0x1f)); 955 IPU_WRITE4(sc, db_mode_sel, reg); 956 957 IPU_WRITE4(sc, cur_buf, (1UL << (DMA_CHANNEL & 0x1f))); 958 } 959 960 static int 961 ipu_init(struct ipu_softc *sc) 962 { 963 uint32_t reg, off; 964 int i, err; 965 size_t dma_size; 966 967 IPU_WRITE4(sc, IPU_CONF, DI_PORT ? IPU_CONF_DI1_EN : IPU_CONF_DI0_EN); 968 969 IPU_WRITE4(sc, IPU_MEM_RST, IPU_MEM_RST_ALL); 970 i = 1000; 971 while (i-- > 0) { 972 if (!(IPU_READ4(sc, IPU_MEM_RST) & IPU_MEM_RST_START)) 973 break; 974 DELAY(1); 975 } 976 977 if (i <= 0) { 978 err = ETIMEDOUT; 979 device_printf(sc->sc_dev, "timeout while resetting memory\n"); 980 goto fail; 981 } 982 983 ipu_dc_reset_map(sc, 0); 984 ipu_dc_setup_map(sc, 0, 0, 7, 0xff); 985 ipu_dc_setup_map(sc, 0, 1, 15, 0xff); 986 ipu_dc_setup_map(sc, 0, 2, 23, 0xff); 987 988 dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8)); 989 990 /* 991 * Now allocate framebuffer memory 992 */ 993 err = bus_dma_tag_create( 994 bus_get_dma_tag(sc->sc_dev), 995 4, 0, /* alignment, boundary */ 996 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 997 BUS_SPACE_MAXADDR, /* highaddr */ 998 NULL, NULL, /* filter, filterarg */ 999 dma_size, 1, /* maxsize, nsegments */ 1000 dma_size, 0, /* maxsegsize, flags */ 1001 NULL, NULL, /* lockfunc, lockarg */ 1002 &sc->sc_dma_tag); 1003 if (err) 1004 goto fail; 1005 1006 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 1007 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_dma_map); 1008 1009 if (err) { 1010 device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 1011 goto fail; 1012 } 1013 1014 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 1015 dma_size, ipu_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 1016 1017 if (err) { 1018 device_printf(sc->sc_dev, "cannot load DMA map\n"); 1019 goto fail; 1020 } 1021 1022 /* Calculate actual FB Size */ 1023 sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8; 1024 1025 ipu_dc_init(sc, DI_PORT); 1026 reg = IPU_READ4(sc, IPU_CONF); 1027 reg |= IPU_CONF_DMFC_EN | IPU_CONF_DC_EN | IPU_CONF_DP_EN; 1028 IPU_WRITE4(sc, IPU_CONF, reg); 1029 1030 ipu_config_timing(sc, DI_PORT); 1031 ipu_init_buffer(sc); 1032 ipu_di_enable(sc, DI_PORT); 1033 1034 /* Enable DMA channel */ 1035 off = (DMA_CHANNEL > 31) ? IPU_IDMAC_CH_EN_2 : IPU_IDMAC_CH_EN_1; 1036 reg = IPU_READ4(sc, off); 1037 reg |= (1 << (DMA_CHANNEL & 0x1f)); 1038 IPU_WRITE4(sc, off, reg); 1039 1040 ipu_dc_enable(sc); 1041 1042 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 1043 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 1044 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 1045 sc->sc_fb_info.fb_size = sc->sc_fb_size; 1046 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = MODE_BPP; 1047 sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8; 1048 sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay; 1049 sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay; 1050 1051 device_t fbd = device_add_child(sc->sc_dev, "fbd", 1052 device_get_unit(sc->sc_dev)); 1053 if (fbd == NULL) { 1054 device_printf(sc->sc_dev, "Failed to add fbd child\n"); 1055 goto fail; 1056 } 1057 if (device_probe_and_attach(fbd) != 0) { 1058 device_printf(sc->sc_dev, "Failed to attach fbd device\n"); 1059 goto fail; 1060 } 1061 1062 return (0); 1063 fail: 1064 1065 return (err); 1066 } 1067 1068 static int 1069 ipu_mode_is_valid(const struct videomode *mode) 1070 { 1071 if ((mode->dot_clock < 13500) || (mode->dot_clock > 216000)) 1072 return (0); 1073 1074 return (1); 1075 } 1076 1077 static const struct videomode * 1078 ipu_pick_mode(struct edid_info *ei) 1079 { 1080 const struct videomode *videomode; 1081 const struct videomode *m; 1082 int n; 1083 1084 videomode = NULL; 1085 1086 /* 1087 * Pick a mode. 1088 */ 1089 if (ei->edid_preferred_mode != NULL) { 1090 if (ipu_mode_is_valid(ei->edid_preferred_mode)) 1091 videomode = ei->edid_preferred_mode; 1092 } 1093 1094 if (videomode == NULL) { 1095 m = ei->edid_modes; 1096 1097 sort_modes(ei->edid_modes, 1098 &ei->edid_preferred_mode, 1099 ei->edid_nmodes); 1100 for (n = 0; n < ei->edid_nmodes; n++) 1101 if (ipu_mode_is_valid(&m[n])) { 1102 videomode = &m[n]; 1103 break; 1104 } 1105 } 1106 1107 return videomode; 1108 } 1109 1110 static void 1111 ipu_hdmi_event(void *arg, device_t hdmi_dev) 1112 { 1113 struct ipu_softc *sc; 1114 uint8_t *edid; 1115 uint32_t edid_len; 1116 struct edid_info ei; 1117 const struct videomode *videomode; 1118 1119 sc = arg; 1120 1121 edid = NULL; 1122 edid_len = 0; 1123 if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 1124 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 1125 } 1126 1127 videomode = NULL; 1128 1129 if ( edid && (edid_parse(edid, &ei) == 0)) { 1130 if (bootverbose) 1131 edid_print(&ei); 1132 videomode = ipu_pick_mode(&ei); 1133 } else 1134 device_printf(sc->sc_dev, "failed to parse EDID\n"); 1135 1136 /* Use standard VGA as fallback */ 1137 if (videomode == NULL) 1138 videomode = pick_mode_by_ref(640, 480, 60); 1139 1140 if (videomode == NULL) { 1141 device_printf(sc->sc_dev, "failed to find usable videomode\n"); 1142 return; 1143 } 1144 1145 sc->sc_mode = videomode; 1146 1147 if (bootverbose) 1148 device_printf(sc->sc_dev, "detected videomode: %dx%d\n", 1149 videomode->hdisplay, videomode->vdisplay); 1150 1151 ipu_init(sc); 1152 1153 HDMI_SET_VIDEOMODE(hdmi_dev, sc->sc_mode); 1154 } 1155 1156 static int 1157 ipu_probe(device_t dev) 1158 { 1159 1160 if (have_ipu) 1161 return (ENXIO); 1162 1163 if (!ofw_bus_status_okay(dev)) 1164 return (ENXIO); 1165 1166 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ipu")) 1167 return (ENXIO); 1168 1169 device_set_desc(dev, "Freescale IPU"); 1170 1171 return (BUS_PROBE_DEFAULT); 1172 } 1173 1174 static int 1175 ipu_attach(device_t dev) 1176 { 1177 struct ipu_softc *sc; 1178 1179 if (have_ipu) 1180 return (ENXIO); 1181 1182 sc = device_get_softc(dev); 1183 sc->sc_dev = dev; 1184 1185 sc->sc_mem_rid = 0; 1186 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1187 &sc->sc_mem_rid, RF_ACTIVE); 1188 if (!sc->sc_mem_res) { 1189 device_printf(dev, "cannot allocate memory window\n"); 1190 return (ENXIO); 1191 } 1192 1193 sc->sc_irq_rid = 0; 1194 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1195 &sc->sc_irq_rid, RF_ACTIVE); 1196 if (!sc->sc_irq_res) { 1197 bus_release_resource(dev, SYS_RES_MEMORY, 1198 sc->sc_mem_rid, sc->sc_mem_res); 1199 device_printf(dev, "cannot allocate interrupt\n"); 1200 return (ENXIO); 1201 } 1202 1203 /* Enable IPU1 */ 1204 if (imx_ccm_pll_video_enable() != 0) { 1205 bus_release_resource(dev, SYS_RES_MEMORY, 1206 sc->sc_mem_rid, sc->sc_mem_res); 1207 bus_release_resource(dev, SYS_RES_IRQ, 1208 sc->sc_irq_rid, sc->sc_irq_res); 1209 device_printf(dev, "failed to set up video PLL\n"); 1210 return (ENXIO); 1211 } 1212 1213 imx_ccm_ipu_enable(1); 1214 1215 if (src_reset_ipu() != 0) { 1216 bus_release_resource(dev, SYS_RES_MEMORY, 1217 sc->sc_mem_rid, sc->sc_mem_res); 1218 bus_release_resource(dev, SYS_RES_IRQ, 1219 sc->sc_irq_rid, sc->sc_irq_res); 1220 device_printf(dev, "failed to reset IPU\n"); 1221 return (ENXIO); 1222 } 1223 1224 IPU_LOCK_INIT(sc); 1225 1226 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1227 ipu_hdmi_event, sc, 0); 1228 1229 have_ipu = 1; 1230 1231 return (0); 1232 } 1233 1234 static int 1235 ipu_detach(device_t dev) 1236 { 1237 /* Do not let unload driver */ 1238 return (EBUSY); 1239 } 1240 1241 static struct fb_info * 1242 ipu_fb_getinfo(device_t dev) 1243 { 1244 struct ipu_softc *sc; 1245 1246 sc = device_get_softc(dev); 1247 1248 return (&sc->sc_fb_info); 1249 } 1250 1251 static device_method_t ipu_methods[] = { 1252 DEVMETHOD(device_probe, ipu_probe), 1253 DEVMETHOD(device_attach, ipu_attach), 1254 DEVMETHOD(device_detach, ipu_detach), 1255 1256 /* Framebuffer service methods */ 1257 DEVMETHOD(fb_getinfo, ipu_fb_getinfo), 1258 1259 DEVMETHOD_END 1260 }; 1261 1262 static driver_t ipu_driver = { 1263 "fb", 1264 ipu_methods, 1265 sizeof(struct ipu_softc), 1266 }; 1267 1268 DRIVER_MODULE(ipu, simplebus, ipu_driver, 0, 0); 1269 MODULE_VERSION(ipu, 1); 1270 MODULE_DEPEND(ipu, simplebus, 1, 1, 1);
Cache object: 0a1bef7b239856556bca879118744ee5
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