Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/freescale/imx/imx6_ipu.c
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1 /*- 2 * Copyright 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/clock.h> 35 #include <sys/time.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/fbio.h> 43 #include <sys/consio.h> 44 45 #include <machine/bus.h> 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/fb/fbreg.h> 52 #include <dev/vt/vt.h> 53 54 #include <dev/videomode/videomode.h> 55 #include <dev/videomode/edidvar.h> 56 57 #include <arm/freescale/imx/imx6_src.h> 58 #include <arm/freescale/imx/imx_ccmvar.h> 59 60 #include "fb_if.h" 61 #include "hdmi_if.h" 62 63 static int have_ipu = 0; 64 65 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 66 #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 67 #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 68 #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 69 #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 70 #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 71 72 #define MODE_BPP 16 73 #define MODE_PIXEL_CLOCK_INVERT 1 74 75 #define DMA_CHANNEL 23 76 #define DC_CHAN5 5 77 #define DI_PORT 0 78 79 #define IPU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 80 #define IPU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 81 #define IPU_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 82 device_get_nameunit(_sc->sc_dev), "ipu", MTX_DEF) 83 #define IPU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 84 85 #define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg)) 86 #define IPU_WRITE4(_sc, reg, value) \ 87 bus_write_4((_sc)->sc_mem_res, (reg), (value)) 88 89 #define CPMEM_BASE 0x300000 90 #define DC_TEMPL_BASE 0x380000 91 92 /* Microcode */ 93 /* Word 1 */ 94 #define TEMPLATE_SYNC(v) ((v) << 0) 95 #define TEMPLATE_GLUELOGIC(v) ((v) << 4) 96 #define TEMPLATE_MAPPING(v) ((v) << 15) 97 #define TEMPLATE_WAVEFORM(v) ((v) << 11) 98 #define GLUELOGIC_KEEP_ASSERTED (1 << 3) 99 #define GLUELOGIC_KEEP_NEGATED (1 << 2) 100 /* Word 2 */ 101 #define TEMPLATE_OPCODE(v) ((v) << 4) 102 #define OPCODE_WROD 0x18 103 #define TEMPLATE_STOP (1 << 9) 104 105 #define IPU_CONF 0x200000 106 #define IPU_CONF_DMFC_EN (1 << 10) 107 #define IPU_CONF_DC_EN (1 << 9) 108 #define IPU_CONF_DI1_EN (1 << 7) 109 #define IPU_CONF_DI0_EN (1 << 6) 110 #define IPU_CONF_DP_EN (1 << 5) 111 #define IPU_DISP_GEN 0x2000C4 112 #define DISP_GEN_DI1_CNTR_RELEASE (1 << 25) 113 #define DISP_GEN_DI0_CNTR_RELEASE (1 << 24) 114 #define DISP_GEN_MCU_MAX_BURST_STOP (1 << 22) 115 #define DISP_GEN_MCU_T_SHIFT 18 116 #define IPU_MEM_RST 0x2000DC 117 #define IPU_MEM_RST_START (1 << 31) 118 #define IPU_MEM_RST_ALL 0x807FFFFF 119 #define IPU_CH_DB_MODE_SEL_0 0x200150 120 #define IPU_CH_DB_MODE_SEL_1 0x200154 121 #define IPU_CUR_BUF_0 0x20023C 122 #define IPU_CUR_BUF_1 0x200240 123 124 #define IPU_IDMAC_CH_EN_1 0x208004 125 #define IPU_IDMAC_CH_EN_2 0x208008 126 #define IPU_IDMAC_CH_PRI_1 0x208014 127 #define IPU_IDMAC_CH_PRI_2 0x208018 128 129 #define IPU_DI0_GENERAL 0x240000 130 #define DI_CLOCK_EXTERNAL (1 << 20) 131 #define DI_GENERAL_POL_CLK (1 << 17) 132 #define DI_GENERAL_POLARITY_3 (1 << 2) 133 #define DI_GENERAL_POLARITY_2 (1 << 1) 134 #define IPU_DI0_BS_CLKGEN0 0x240004 135 #define DI_BS_CLKGEN0(_int, _frac) (((_int) << 4) | (_frac)) 136 #define IPU_DI0_BS_CLKGEN1 0x240008 137 #define DI_BS_CLKGEN1_DOWN(_int, _frac) ((((_int) << 1) | (_frac)) << 16) 138 #define IPU_DI0_SW_GEN0_1 0x24000C 139 #define DI_RUN_VALUE_M1(v) ((v) << 19) 140 #define DI_RUN_RESOLUTION(v) ((v) << 16) 141 #define DI_OFFSET_VALUE(v) ((v) << 3) 142 #define IPU_DI0_SW_GEN1_1 0x240030 143 #define DI_CNT_POLARITY_GEN_EN(v) ((v) << 29) 144 #define DI_CNT_AUTO_RELOAD (1 << 28) 145 #define DI_CNT_CLR_SEL(v) ((v) << 25) 146 #define DI_CNT_DOWN(v) ((v) << 16) 147 #define DI_CNT_POLARITY_TRIGGER_SEL(v) ((v) << 12) 148 #define DI_CNT_POLARITY_CLR_SEL(v) ((v) << 9) 149 #define IPU_DI0_SYNC_AS_GEN 0x240054 150 #define SYNC_AS_GEN_VSYNC_SEL(v) ((v) << 13) 151 #define SYNC_AS_GEN_SYNC_START(v) ((v) << 0) 152 #define IPU_DI0_DW_GEN_0 0x240058 153 #define DW_GEN_DI_ACCESS_SIZE(v) ((v) << 24) 154 #define DW_GEN_DI_COMPONENT_SIZE(v) ((v) << 16) 155 #define DW_GEN_DI_SET_MASK 3 156 #define DW_GEN_DI_PIN_15_SET(v) ((v) << 8) 157 #define IPU_DI0_DW_SET3_0 0x240118 158 #define DW_SET_DATA_CNT_DOWN(v) ((v) << 16) 159 #define DW_SET_DATA_CNT_UP(v) ((v) << 0) 160 #define IPU_DI0_STP_REP 0x240148 161 #define IPU_DI0_POL 0x240164 162 #define DI_POL_DRDY_POLARITY_15 (1 << 4) 163 #define IPU_DI0_SCR_CONF 0x240170 164 165 #define IPU_DI1_GENERAL 0x248000 166 #define IPU_DI1_BS_CLKGEN0 0x248004 167 #define IPU_DI1_BS_CLKGEN1 0x248008 168 #define IPU_DI1_SW_GEN0_1 0x24800C 169 #define IPU_DI1_SW_GEN1_1 0x248030 170 #define IPU_DI1_SYNC_AS_GEN 0x248054 171 #define IPU_DI1_DW_GEN_0 0x248058 172 #define IPU_DI1_POL 0x248164 173 #define IPU_DI1_DW_SET3_0 0x248118 174 #define IPU_DI1_STP_REP 0x248148 175 #define IPU_DI1_SCR_CONF 0x248170 176 #define DMFC_RD_CHAN 0x260000 177 #define DMFC_WR_CHAN 0x260004 178 #define DMFC_WR_CHAN_BURST_SIZE_32 (0 << 6) 179 #define DMFC_WR_CHAN_BURST_SIZE_16 (1 << 6) 180 #define DMFC_WR_CHAN_BURST_SIZE_8 (2 << 6) 181 #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) 182 #define DMFC_WR_CHAN_BURST_SIZE_4 (3 << 6) 183 #define DMFC_WR_CHAN_FIFO_SIZE_128 (2 << 3) 184 #define DMFC_WR_CHAN_DEF 0x260008 185 #define DMFC_WR_CHAN_DEF_WM_CLR_2C(v) ((v) << 29) 186 #define DMFC_WR_CHAN_DEF_WM_CLR_1C(v) ((v) << 21) 187 #define DMFC_WR_CHAN_DEF_WM_CLR_2(v) ((v) << 13) 188 #define DMFC_WR_CHAN_DEF_WM_CLR_1(v) ((v) << 5) 189 #define DMFC_WR_CHAN_DEF_WM_SET_1(v) ((v) << 2) 190 #define DMFC_WR_CHAN_DEF_WM_EN_1 (1 << 1) 191 #define DMFC_DP_CHAN 0x26000C 192 #define DMFC_DP_CHAN_BURST_SIZE_8 2 193 #define DMFC_DP_CHAN_FIFO_SIZE_256 1 194 #define DMFC_DP_CHAN_FIFO_SIZE_128 2 195 #define DMFC_DP_CHAN_BURST_SIZE_5F(v) ((v) << 14) 196 #define DMFC_DP_CHAN_FIFO_SIZE_5F(v) ((v) << 11) 197 #define DMFC_DP_CHAN_ST_ADDR_SIZE_5F(v) ((v) << 8) 198 #define DMFC_DP_CHAN_BURST_SIZE_5B(v) ((v) << 6) 199 #define DMFC_DP_CHAN_FIFO_SIZE_5B(v) ((v) << 3) 200 #define DMFC_DP_CHAN_ST_ADDR_SIZE_5B(v) ((v) << 0) 201 #define DMFC_DP_CHAN_DEF 0x260010 202 #define DMFC_DP_CHAN_DEF_WM_CLR_6F(v) ((v) << 29) 203 #define DMFC_DP_CHAN_DEF_WM_CLR_6B(v) ((v) << 21) 204 #define DMFC_DP_CHAN_DEF_WM_CLR_5F(v) ((v) << 13) 205 #define DMFC_DP_CHAN_DEF_WM_SET_5F(v) ((v) << 10) 206 #define DMFC_DP_CHAN_DEF_WM_EN_5F (1 << 9) 207 #define DMFC_DP_CHAN_DEF_WM_CLR_5B(v) ((v) << 5) 208 #define DMFC_DP_CHAN_DEF_WM_SET_5B(v) ((v) << 2) 209 #define DMFC_DP_CHAN_DEF_WM_EN_5B (1 << 1) 210 #define DMFC_GENERAL_1 0x260014 211 #define DMFC_GENERAL_1_WAIT4EOT_5B (1 << 20) 212 #define DMFC_IC_CTRL 0x26001C 213 #define DMFC_IC_CTRL_DISABLED 0x2 214 215 #define DC_WRITE_CH_CONF_1 0x0025801C 216 #define WRITE_CH_CONF_PROG_CHAN_TYP_MASK (7 << 5) 217 #define WRITE_CH_CONF_PROG_CHAN_NORMAL (4 << 5) 218 #define DC_WRITE_CH_ADDR_1 0x00258020 219 #define DC_WRITE_CH_CONF_5 0x0025805C 220 #define WRITE_CH_CONF_PROG_DISP_ID(v) ((v) << 3) 221 #define WRITE_CH_CONF_PROG_DI_ID(v) ((v) << 2) 222 #define WRITE_CH_CONF_PROG_W_SIZE(v) (v) 223 #define DC_WRITE_CH_ADDR_5 0x00258060 224 #define DC_RL0_CH_5 0x00258064 225 #define DC_GEN 0x002580D4 226 #define DC_GEN_SYNC_PRIORITY (1 << 7) 227 #define DC_GEN_ASYNC (0 << 1) 228 #define DC_GEN_SYNC (2 << 1) 229 #define DC_DISP_CONF2(di) (0x002580E8 + (di) * 4) 230 #define DC_MAP_CONF_0 0x00258108 231 #define DC_MAP_CONF_15 0x00258144 232 #define DC_MAP_CONF_VAL(map) (DC_MAP_CONF_15 + ((map) / 2) * sizeof(uint32_t)) 233 #define MAP_CONF_VAL_MASK 0xffff 234 #define DC_MAP_CONF_PTR(ptr) (DC_MAP_CONF_0 + ((ptr) / 2) * sizeof(uint32_t)) 235 #define MAP_CONF_PTR_MASK 0x1f 236 237 #define DI_COUNTER_INT_HSYNC 1 238 #define DI_COUNTER_HSYNC 2 239 #define DI_COUNTER_VSYNC 3 240 #define DI_COUNTER_AD_0 4 241 #define DI_COUNTER_AD_1 5 242 243 #define DI_SYNC_NONE 0 244 #define DI_SYNC_CLK 1 245 #define DI_SYNC_COUNTER(c) ((c) + 1) 246 247 struct ipu_cpmem_word { 248 uint32_t data[5]; 249 uint32_t padding[3]; 250 }; 251 252 struct ipu_cpmem_ch_param { 253 struct ipu_cpmem_word word[2]; 254 }; 255 256 #define CH_PARAM_RESET(param) memset(param, 0, sizeof(*param)) 257 #define IPU_READ_CH_PARAM(_sc, ch, param) bus_read_region_4( \ 258 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ 259 (uint32_t*)param, sizeof(*param) / 4) 260 #define IPU_WRITE_CH_PARAM(_sc, ch, param) bus_write_region_4( \ 261 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\ 262 (uint32_t*)param, sizeof(*param) / 4) 263 264 #define CH_PARAM_SET_FW(param, v) ipu_ch_param_set_value((param), \ 265 0, 125, 13, (v)) 266 #define CH_PARAM_SET_FH(param, v) ipu_ch_param_set_value((param), \ 267 0, 138, 12, (v)) 268 #define CH_PARAM_SET_SLY(param, v) ipu_ch_param_set_value((param), \ 269 1, 102, 14, (v)) 270 #define CH_PARAM_SET_EBA0(param, v) ipu_ch_param_set_value((param), \ 271 1, 0, 29, (v)) 272 #define CH_PARAM_SET_EBA1(param, v) ipu_ch_param_set_value((param), \ 273 1, 29, 29, (v)) 274 #define CH_PARAM_SET_BPP(param, v) ipu_ch_param_set_value((param), \ 275 0, 107, 3, (v)) 276 #define CH_PARAM_SET_PFS(param, v) ipu_ch_param_set_value((param), \ 277 1, 85, 4, (v)) 278 #define CH_PARAM_SET_NPB(param, v) ipu_ch_param_set_value((param), \ 279 1, 78, 7, (v)) 280 #define CH_PARAM_SET_UBO(param, v) ipu_ch_param_set_value((param), \ 281 0, 46, 22, (v)) 282 #define CH_PARAM_SET_VBO(param, v) ipu_ch_param_set_value((param), \ 283 0, 68, 22, (v)) 284 285 #define CH_PARAM_SET_RED_WIDTH(param, v) ipu_ch_param_set_value((param), \ 286 1, 116, 3, (v)) 287 #define CH_PARAM_SET_RED_OFFSET(param, v) ipu_ch_param_set_value((param), \ 288 1, 128, 5, (v)) 289 290 #define CH_PARAM_SET_GREEN_WIDTH(param, v) ipu_ch_param_set_value((param), \ 291 1, 119, 3, (v)) 292 #define CH_PARAM_SET_GREEN_OFFSET(param, v) ipu_ch_param_set_value((param), \ 293 1, 133, 5, (v)) 294 295 #define CH_PARAM_SET_BLUE_WIDTH(param, v) ipu_ch_param_set_value((param), \ 296 1, 122, 3, (v)) 297 #define CH_PARAM_SET_BLUE_OFFSET(param, v) ipu_ch_param_set_value((param), \ 298 1, 138, 5, (v)) 299 300 #define CH_PARAM_SET_ALPHA_WIDTH(param, v) ipu_ch_param_set_value((param), \ 301 1, 125, 3, (v)) 302 #define CH_PARAM_SET_ALPHA_OFFSET(param, v) ipu_ch_param_set_value((param), \ 303 1, 143, 5, (v)) 304 305 #define CH_PARAM_GET_FW(param) ipu_ch_param_get_value((param), \ 306 0, 125, 13) 307 #define CH_PARAM_GET_FH(param) ipu_ch_param_get_value((param), \ 308 0, 138, 12) 309 #define CH_PARAM_GET_SLY(param) ipu_ch_param_get_value((param), \ 310 1, 102, 14) 311 #define CH_PARAM_GET_EBA0(param) ipu_ch_param_get_value((param), \ 312 1, 0, 29) 313 #define CH_PARAM_GET_EBA1(param) ipu_ch_param_get_value((param), \ 314 1, 29, 29) 315 #define CH_PARAM_GET_BPP(param) ipu_ch_param_get_value((param), \ 316 0, 107, 3) 317 #define CH_PARAM_GET_PFS(param) ipu_ch_param_get_value((param), \ 318 1, 85, 4) 319 #define CH_PARAM_GET_NPB(param) ipu_ch_param_get_value((param), \ 320 1, 78, 7) 321 #define CH_PARAM_GET_UBO(param) ipu_ch_param_get_value((param), \ 322 0, 46, 22) 323 #define CH_PARAM_GET_VBO(param) ipu_ch_param_get_value((param), \ 324 0, 68, 22) 325 326 #define CH_PARAM_GET_RED_WIDTH(param) ipu_ch_param_get_value((param), \ 327 1, 116, 3) 328 #define CH_PARAM_GET_RED_OFFSET(param) ipu_ch_param_get_value((param), \ 329 1, 128, 5) 330 331 #define CH_PARAM_GET_GREEN_WIDTH(param) ipu_ch_param_get_value((param), \ 332 1, 119, 3) 333 #define CH_PARAM_GET_GREEN_OFFSET(param) ipu_ch_param_get_value((param), \ 334 1, 133, 5) 335 336 #define CH_PARAM_GET_BLUE_WIDTH(param) ipu_ch_param_get_value((param), \ 337 1, 122, 3) 338 #define CH_PARAM_GET_BLUE_OFFSET(param) ipu_ch_param_get_value((param), \ 339 1, 138, 5) 340 341 #define CH_PARAM_GET_ALPHA_WIDTH(param) ipu_ch_param_get_value((param), \ 342 1, 125, 3) 343 #define CH_PARAM_GET_ALPHA_OFFSET(param) ipu_ch_param_get_value((param), \ 344 1, 143, 5) 345 346 #define IPU_PIX_FORMAT_BPP_32 0 347 #define IPU_PIX_FORMAT_BPP_24 1 348 #define IPU_PIX_FORMAT_BPP_18 2 349 #define IPU_PIX_FORMAT_BPP_16 3 350 #define IPU_PIX_FORMAT_BPP_12 4 351 #define IPU_PIX_FORMAT_BPP_8 5 352 #define IPU_PIX_FORMAT_BPP_ 353 354 #define IPU_PIX_FORMAT_RGB 7 355 356 enum dc_event_t { 357 DC_EVENT_NF = 0, 358 DC_EVENT_NL, 359 DC_EVENT_EOF, 360 DC_EVENT_NFIELD, 361 DC_EVENT_EOL, 362 DC_EVENT_EOFIELD, 363 DC_EVENT_NEW_ADDR, 364 DC_EVENT_NEW_CHAN, 365 DC_EVENT_NEW_DATA 366 }; 367 368 struct ipu_softc { 369 device_t sc_dev; 370 struct resource *sc_mem_res; 371 int sc_mem_rid; 372 struct resource *sc_irq_res; 373 int sc_irq_rid; 374 void *sc_intr_hl; 375 struct mtx sc_mtx; 376 struct fb_info sc_fb_info; 377 const struct videomode *sc_mode; 378 379 /* Framebuffer */ 380 bus_dma_tag_t sc_dma_tag; 381 bus_dmamap_t sc_dma_map; 382 size_t sc_fb_size; 383 bus_addr_t sc_fb_phys; 384 uint8_t *sc_fb_base; 385 386 /* HDMI */ 387 eventhandler_tag sc_hdmi_evh; 388 }; 389 390 static void 391 ipu_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 392 { 393 bus_addr_t *addr; 394 395 if (err) 396 return; 397 398 addr = (bus_addr_t*)arg; 399 *addr = segs[0].ds_addr; 400 } 401 402 static void 403 ipu_ch_param_set_value(struct ipu_cpmem_ch_param *param, 404 int word, unsigned int offset, int len, uint32_t value) 405 { 406 uint32_t datapos, bitpos, mask; 407 uint32_t data, data2; 408 409 KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); 410 411 datapos = offset / 32; 412 bitpos = offset % 32; 413 414 mask = (1 << len) - 1; 415 data = param->word[word].data[datapos]; 416 data &= ~(mask << bitpos); 417 data |= (value << bitpos); 418 param->word[word].data[datapos] = data; 419 420 if ((bitpos + len) > 32) { 421 len = bitpos + len - 32; 422 mask = (1UL << len) - 1; 423 data2 = param->word[word].data[datapos + 1]; 424 data2 &= mask; 425 data2 |= (value >> (32 - bitpos)); 426 param->word[word].data[datapos + 1] = data2; 427 } 428 } 429 430 #ifdef DEBUG 431 static uint32_t 432 ipu_ch_param_get_value(struct ipu_cpmem_ch_param *param, 433 int word, unsigned int offset, int len) 434 { 435 uint32_t datapos, bitpos, mask; 436 uint32_t data, data2; 437 438 KASSERT((len <= 32), ("%s: field len is more than 32", __func__)); 439 440 datapos = offset / 32; 441 bitpos = offset % 32; 442 mask = (1UL << len) - 1; 443 data = param->word[word].data[datapos]; 444 data = data >> bitpos; 445 data &= mask; 446 if ((bitpos + len) > 32) { 447 len = bitpos + len - 32; 448 mask = (1UL << len) - 1; 449 data2 = param->word[word].data[datapos + 1]; 450 data2 &= mask; 451 data |= (data2 << (32 - bitpos)); 452 } 453 454 return (data); 455 } 456 457 static void 458 ipu_print_channel(struct ipu_cpmem_ch_param *param) 459 { 460 int offset0[] = {0, 10, 19, 32, 44, 45, 46, 68, 90, 94, 95, 113, 114, 117, 119, 120, 121, 122, 123, 124, 125, 138, 150, 151, -1}; 461 int offset1[] = {0, 29, 58, 78, 85, 89, 90, 93, 95, 102, 116, 119, 122, 125, 128, 133, 138, 143, 148, 149, 150, -1}; 462 printf("WORD0: %08x %08x %08x %08x %08x\n", 463 param->word[0].data[0], param->word[0].data[1], 464 param->word[0].data[2], param->word[0].data[3], 465 param->word[0].data[4]); 466 printf("WORD1: %08x %08x %08x %08x %08x\n", 467 param->word[1].data[0], param->word[1].data[1], 468 param->word[1].data[2], param->word[1].data[3], 469 param->word[1].data[4]); 470 471 for (int i = 0; offset0[i + 1] != -1; i++) { 472 int len = offset0[i + 1] - offset0[i]; 473 printf("W0[%d:%d] = %d\n", offset0[i], 474 offset0[i] + len - 1, 475 ipu_ch_param_get_value(param, 0, offset0[i], len) 476 ); 477 } 478 479 for (int i = 0; offset1[i + 1] != -1; i++) { 480 int len = offset1[i + 1] - offset1[i]; 481 printf("W1[%d:%d] = %d\n", offset1[i], 482 offset1[i] + len - 1, 483 ipu_ch_param_get_value(param, 1, offset1[i], len) 484 ); 485 } 486 487 printf("FW: %d\n", CH_PARAM_GET_FW(param)); 488 printf("FH: %d\n", CH_PARAM_GET_FH(param)); 489 printf("SLY: %d\n", CH_PARAM_GET_SLY(param)); 490 printf("EBA0: 0x%08x\n", CH_PARAM_GET_EBA0(param)); 491 printf("EBA1: 0x%08x\n", CH_PARAM_GET_EBA1(param)); 492 printf("BPP: %d\n", CH_PARAM_GET_BPP(param)); 493 printf("PFS: %d\n", CH_PARAM_GET_PFS(param)); 494 printf("NPB: %d\n", CH_PARAM_GET_NPB(param)); 495 printf("UBO: %d\n", CH_PARAM_GET_UBO(param)); 496 printf("VBO: %d\n", CH_PARAM_GET_VBO(param)); 497 printf("RED: %d bits @%d\n", CH_PARAM_GET_RED_WIDTH(param) + 1, 498 CH_PARAM_GET_RED_OFFSET(param)); 499 printf("GREEN: %d bits @%d\n", CH_PARAM_GET_GREEN_WIDTH(param) + 1, 500 CH_PARAM_GET_GREEN_OFFSET(param)); 501 printf("BLUE: %d bits @%d\n", CH_PARAM_GET_BLUE_WIDTH(param) + 1, 502 CH_PARAM_GET_BLUE_OFFSET(param)); 503 printf("ALPHA: %d bits @%d\n", CH_PARAM_GET_ALPHA_WIDTH(param) + 1, 504 CH_PARAM_GET_ALPHA_OFFSET(param)); 505 } 506 #endif 507 508 static void 509 ipu_di_enable(struct ipu_softc *sc, int di) 510 { 511 uint32_t flag, reg; 512 513 flag = di ? DISP_GEN_DI1_CNTR_RELEASE : DISP_GEN_DI0_CNTR_RELEASE; 514 reg = IPU_READ4(sc, IPU_DISP_GEN); 515 reg |= flag; 516 IPU_WRITE4(sc, IPU_DISP_GEN, reg); 517 } 518 519 static void 520 ipu_config_wave_gen_0(struct ipu_softc *sc, int di, 521 int wave_gen, int run_value, int run_res, 522 int offset_value, int offset_res) 523 { 524 uint32_t addr, reg; 525 526 addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) 527 + (wave_gen - 1) * sizeof(uint32_t); 528 reg = DI_RUN_VALUE_M1(run_value) | 529 DI_RUN_RESOLUTION(run_res) | 530 DI_OFFSET_VALUE(offset_value) | offset_res; 531 IPU_WRITE4(sc, addr, reg); 532 } 533 534 static void 535 ipu_config_wave_gen_1(struct ipu_softc *sc, int di, int wave_gen, 536 int repeat_count, int cnt_clr_src, 537 int cnt_polarity_gen_en, 538 int cnt_polarity_clr_src, 539 int cnt_polarity_trigger_src, 540 int cnt_up, int cnt_down) 541 { 542 uint32_t addr, reg; 543 544 addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) 545 + (wave_gen - 1) * sizeof(uint32_t); 546 reg = DI_CNT_POLARITY_GEN_EN(cnt_polarity_gen_en) | 547 DI_CNT_CLR_SEL(cnt_clr_src) | 548 DI_CNT_POLARITY_TRIGGER_SEL(cnt_polarity_trigger_src) | 549 DI_CNT_POLARITY_CLR_SEL(cnt_polarity_clr_src); 550 reg |= DI_CNT_DOWN(cnt_down) | cnt_up; 551 if (repeat_count == 0) 552 reg |= DI_CNT_AUTO_RELOAD; 553 IPU_WRITE4(sc, addr, reg); 554 555 addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) 556 + (wave_gen - 1) / 2 * sizeof(uint32_t); 557 reg = IPU_READ4(sc, addr); 558 if (wave_gen % 2) { 559 reg &= ~(0xffff); 560 reg |= repeat_count; 561 } 562 else { 563 reg &= ~(0xffff << 16); 564 reg |= (repeat_count << 16); 565 } 566 IPU_WRITE4(sc, addr, reg); 567 } 568 569 static void 570 ipu_reset_wave_gen(struct ipu_softc *sc, int di, 571 int wave_gen) 572 { 573 uint32_t addr, reg; 574 575 addr = (di ? IPU_DI1_SW_GEN0_1 : IPU_DI0_SW_GEN0_1) 576 + (wave_gen - 1) * sizeof(uint32_t); 577 IPU_WRITE4(sc, addr, 0); 578 579 addr = (di ? IPU_DI1_SW_GEN1_1 : IPU_DI0_SW_GEN1_1) 580 + (wave_gen - 1) * sizeof(uint32_t); 581 IPU_WRITE4(sc, addr, 0); 582 583 addr = (di ? IPU_DI1_STP_REP : IPU_DI0_STP_REP) 584 + (wave_gen - 1) / 2 * sizeof(uint32_t); 585 reg = IPU_READ4(sc, addr); 586 if (wave_gen % 2) 587 reg &= ~(0xffff); 588 else 589 reg &= ~(0xffff << 16); 590 IPU_WRITE4(sc, addr, reg); 591 } 592 593 static void 594 ipu_init_microcode_template(struct ipu_softc *sc, int di, int map) 595 { 596 uint32_t addr; 597 uint32_t w1, w2; 598 int i, word; 599 int glue; 600 601 word = di ? 2 : 5; 602 603 for (i = 0; i < 3; i++) { 604 if (i == 0) 605 glue = GLUELOGIC_KEEP_ASSERTED; 606 else if (i == 1) 607 glue = GLUELOGIC_KEEP_NEGATED; 608 else if (i == 2) 609 glue = 0; 610 611 w1 = TEMPLATE_SYNC(5) | 612 TEMPLATE_GLUELOGIC(glue) | 613 TEMPLATE_WAVEFORM(1) | /* wave unit 0 */ 614 TEMPLATE_MAPPING(map + 1); 615 /* operand is zero */ 616 617 /* Write data to DI and Hold data in register */ 618 w2 = TEMPLATE_OPCODE(OPCODE_WROD) | 619 TEMPLATE_STOP; 620 621 addr = DC_TEMPL_BASE + (word + i) * 2 * sizeof(uint32_t); 622 IPU_WRITE4(sc, addr, w1); 623 IPU_WRITE4(sc, addr + sizeof(uint32_t), w2); 624 } 625 } 626 627 static uint32_t 628 ipu_calc_divisor(uint32_t reference, uint32_t freq) 629 { 630 uint32_t div, i; 631 uint32_t delta, min_delta; 632 633 min_delta = freq; 634 div = 255; 635 636 for (i = 1; i < 255; i++) { 637 delta = abs(reference/i - freq); 638 if (delta < min_delta) { 639 div = i; 640 min_delta = delta; 641 } 642 } 643 644 return (div); 645 } 646 647 static void 648 ipu_config_timing(struct ipu_softc *sc, int di) 649 { 650 uint32_t div; 651 uint32_t di_scr_conf; 652 uint32_t gen_offset, gen; 653 uint32_t as_gen_offset, as_gen; 654 uint32_t dw_gen_offset, dw_gen; 655 uint32_t dw_set_offset, dw_set; 656 uint32_t bs_clkgen_offset; 657 int map; 658 uint32_t freq; 659 660 freq = sc->sc_mode->dot_clock * 1000; 661 662 div = ipu_calc_divisor(imx_ccm_ipu_hz(), freq); 663 map = 0; 664 665 bs_clkgen_offset = di ? IPU_DI1_BS_CLKGEN0 : IPU_DI0_BS_CLKGEN0; 666 IPU_WRITE4(sc, bs_clkgen_offset, DI_BS_CLKGEN0(div, 0)); 667 /* half of the divider */ 668 IPU_WRITE4(sc, bs_clkgen_offset + 4, DI_BS_CLKGEN1_DOWN(div / 2, div % 2)); 669 670 /* Setup wave generator */ 671 dw_gen_offset = di ? IPU_DI1_DW_GEN_0 : IPU_DI0_DW_GEN_0; 672 dw_gen = DW_GEN_DI_ACCESS_SIZE(div - 1) | DW_GEN_DI_COMPONENT_SIZE(div - 1); 673 dw_gen &= ~DW_GEN_DI_PIN_15_SET(DW_GEN_DI_SET_MASK); 674 dw_gen |= DW_GEN_DI_PIN_15_SET(3); /* set 3*/ 675 IPU_WRITE4(sc, dw_gen_offset, dw_gen); 676 677 dw_set_offset = di ? IPU_DI1_DW_SET3_0 : IPU_DI0_DW_SET3_0; 678 dw_set = DW_SET_DATA_CNT_DOWN(div * 2) | DW_SET_DATA_CNT_UP(0); 679 IPU_WRITE4(sc, dw_set_offset, dw_set); 680 681 /* DI_COUNTER_INT_HSYNC */ 682 ipu_config_wave_gen_0(sc, di, DI_COUNTER_INT_HSYNC, 683 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE); 684 ipu_config_wave_gen_1(sc, di, DI_COUNTER_INT_HSYNC, 685 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 686 687 /* DI_COUNTER_HSYNC */ 688 ipu_config_wave_gen_0(sc, di, DI_COUNTER_HSYNC, 689 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK); 690 ipu_config_wave_gen_1(sc, di, DI_COUNTER_HSYNC, 691 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, DI_SYNC_CLK, 692 0, MODE_HSW(sc->sc_mode) * 2); 693 694 /* DI_COUNTER_VSYNC */ 695 ipu_config_wave_gen_0(sc, di, DI_COUNTER_VSYNC, 696 sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 697 0, DI_SYNC_NONE); 698 ipu_config_wave_gen_1(sc, di, DI_COUNTER_VSYNC, 699 0, DI_SYNC_NONE, 1, DI_SYNC_NONE, 700 DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), 701 0, MODE_VSW(sc->sc_mode) * 2); 702 703 di_scr_conf = di ? IPU_DI1_SCR_CONF : IPU_DI0_SCR_CONF; 704 IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1); 705 706 /* TODO: update DI_SCR_CONF */ 707 708 /* Active Data 0 */ 709 ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_0, 710 0, DI_SYNC_COUNTER(DI_COUNTER_HSYNC), 711 MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC)); 712 ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_0, 713 sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC), 714 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 715 716 ipu_config_wave_gen_0(sc, di, DI_COUNTER_AD_1, 717 0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK); 718 ipu_config_wave_gen_1(sc, di, DI_COUNTER_AD_1, 719 sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0), 720 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0); 721 722 ipu_reset_wave_gen(sc, di, 6); 723 ipu_reset_wave_gen(sc, di, 7); 724 ipu_reset_wave_gen(sc, di, 8); 725 ipu_reset_wave_gen(sc, di, 9); 726 727 ipu_init_microcode_template(sc, di, map); 728 729 gen_offset = di ? IPU_DI1_GENERAL : IPU_DI0_GENERAL; 730 gen = IPU_READ4(sc, gen_offset); 731 732 if (sc->sc_mode->flags & VID_NHSYNC) 733 gen &= ~DI_GENERAL_POLARITY_2; 734 else /* active high */ 735 gen |= DI_GENERAL_POLARITY_2; 736 737 if (sc->sc_mode->flags & VID_NVSYNC) 738 gen &= ~DI_GENERAL_POLARITY_3; 739 else /* active high */ 740 gen |= DI_GENERAL_POLARITY_3; 741 742 if (MODE_PIXEL_CLOCK_INVERT) 743 gen &= ~DI_GENERAL_POL_CLK; 744 else 745 gen |= DI_GENERAL_POL_CLK; 746 747 /* Use LDB clock to drive pixel clock */ 748 gen |= DI_CLOCK_EXTERNAL; 749 750 IPU_WRITE4(sc, gen_offset, gen); 751 752 as_gen_offset = di ? IPU_DI1_SYNC_AS_GEN : IPU_DI0_SYNC_AS_GEN; 753 as_gen = SYNC_AS_GEN_VSYNC_SEL(DI_COUNTER_VSYNC - 1) | 754 SYNC_AS_GEN_SYNC_START(2); 755 IPU_WRITE4(sc, as_gen_offset, as_gen); 756 757 IPU_WRITE4(sc, (di ? IPU_DI1_POL : IPU_DI0_POL), DI_POL_DRDY_POLARITY_15); 758 759 IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay); 760 } 761 762 static void 763 ipu_dc_enable(struct ipu_softc *sc) 764 { 765 uint32_t conf; 766 767 /* channel 1 uses DI1 */ 768 IPU_WRITE4(sc, DC_WRITE_CH_CONF_1, WRITE_CH_CONF_PROG_DI_ID(1)); 769 770 conf = IPU_READ4(sc, DC_WRITE_CH_CONF_5); 771 conf &= ~WRITE_CH_CONF_PROG_CHAN_TYP_MASK; 772 conf |= WRITE_CH_CONF_PROG_CHAN_NORMAL; 773 IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); 774 } 775 776 static void 777 ipu_dc_link_event(struct ipu_softc *sc, int event, int addr, int priority) 778 { 779 uint32_t reg; 780 int offset; 781 int shift; 782 783 if (event % 2) 784 shift = 16; 785 else 786 shift = 0; 787 788 offset = DC_RL0_CH_5 + (event / 2) * sizeof(uint32_t); 789 790 reg = IPU_READ4(sc, offset); 791 reg &= ~(0xFFFF << shift); 792 reg |= ((addr << 8) | priority) << shift; 793 IPU_WRITE4(sc, offset, reg); 794 } 795 796 static void 797 ipu_dc_setup_map(struct ipu_softc *sc, int map, 798 int byte, int offset, int mask) 799 { 800 uint32_t reg, shift, ptr; 801 802 ptr = map * 3 + byte; 803 804 reg = IPU_READ4(sc, DC_MAP_CONF_VAL(ptr)); 805 if (ptr & 1) 806 shift = 16; 807 else 808 shift = 0; 809 reg &= ~(0xffff << shift); 810 reg |= ((offset << 8) | mask) << shift; 811 IPU_WRITE4(sc, DC_MAP_CONF_VAL(ptr), reg); 812 813 reg = IPU_READ4(sc, DC_MAP_CONF_PTR(map)); 814 if (map & 1) 815 shift = 16 + 5 * byte; 816 else 817 shift = 5 * byte; 818 reg &= ~(MAP_CONF_PTR_MASK << shift); 819 reg |= (ptr) << shift; 820 IPU_WRITE4(sc, DC_MAP_CONF_PTR(map), reg); 821 } 822 823 static void 824 ipu_dc_reset_map(struct ipu_softc *sc, int map) 825 { 826 uint32_t reg, shift; 827 828 reg = IPU_READ4(sc, DC_MAP_CONF_VAL(map)); 829 if (map & 1) 830 shift = 16; 831 else 832 shift = 0; 833 reg &= ~(MAP_CONF_VAL_MASK << shift); 834 IPU_WRITE4(sc, DC_MAP_CONF_VAL(map), reg); 835 } 836 837 static void 838 ipu_dc_init(struct ipu_softc *sc, int di_port) 839 { 840 int addr; 841 uint32_t conf; 842 843 if (di_port) 844 addr = 2; 845 else 846 addr = 5; 847 848 ipu_dc_link_event(sc, DC_EVENT_NL, addr, 3); 849 ipu_dc_link_event(sc, DC_EVENT_EOL, addr + 1, 2); 850 ipu_dc_link_event(sc, DC_EVENT_NEW_DATA, addr + 2, 1); 851 ipu_dc_link_event(sc, DC_EVENT_NF, 0, 0); 852 ipu_dc_link_event(sc, DC_EVENT_NFIELD, 0, 0); 853 ipu_dc_link_event(sc, DC_EVENT_EOF, 0, 0); 854 ipu_dc_link_event(sc, DC_EVENT_EOFIELD, 0, 0); 855 ipu_dc_link_event(sc, DC_EVENT_NEW_CHAN, 0, 0); 856 ipu_dc_link_event(sc, DC_EVENT_NEW_ADDR, 0, 0); 857 858 conf = WRITE_CH_CONF_PROG_W_SIZE(0x02) | 859 WRITE_CH_CONF_PROG_DISP_ID(DI_PORT) | 860 WRITE_CH_CONF_PROG_DI_ID(DI_PORT); 861 862 IPU_WRITE4(sc, DC_WRITE_CH_CONF_5, conf); 863 IPU_WRITE4(sc, DC_WRITE_CH_ADDR_5, 0x00000000); 864 IPU_WRITE4(sc, DC_GEN, DC_GEN_SYNC_PRIORITY | DC_GEN_SYNC); /* High priority, sync */ 865 } 866 867 static void 868 ipu_init_buffer(struct ipu_softc *sc) 869 { 870 struct ipu_cpmem_ch_param param; 871 uint32_t stride; 872 uint32_t reg, db_mode_sel, cur_buf; 873 874 stride = sc->sc_mode->hdisplay * MODE_BPP / 8; 875 876 /* init channel parameters */ 877 CH_PARAM_RESET(¶m); 878 /* XXX: interlaced modes are not supported yet */ 879 CH_PARAM_SET_FW(¶m, sc->sc_mode->hdisplay - 1); 880 CH_PARAM_SET_FH(¶m, sc->sc_mode->vdisplay - 1); 881 CH_PARAM_SET_SLY(¶m, stride - 1); 882 883 CH_PARAM_SET_EBA0(¶m, (sc->sc_fb_phys >> 3)); 884 CH_PARAM_SET_EBA1(¶m, (sc->sc_fb_phys >> 3)); 885 886 CH_PARAM_SET_BPP(¶m, IPU_PIX_FORMAT_BPP_16); 887 CH_PARAM_SET_PFS(¶m, IPU_PIX_FORMAT_RGB); 888 /* 16 pixels per burst access */ 889 CH_PARAM_SET_NPB(¶m, 16 - 1); 890 891 CH_PARAM_SET_RED_OFFSET(¶m, 0); 892 CH_PARAM_SET_RED_WIDTH(¶m, 5 - 1); 893 CH_PARAM_SET_GREEN_OFFSET(¶m, 5); 894 CH_PARAM_SET_GREEN_WIDTH(¶m, 6 - 1); 895 CH_PARAM_SET_BLUE_OFFSET(¶m, 11); 896 CH_PARAM_SET_BLUE_WIDTH(¶m, 5 - 1); 897 CH_PARAM_SET_ALPHA_OFFSET(¶m, 16); 898 CH_PARAM_SET_ALPHA_WIDTH(¶m, 8 - 1); 899 900 CH_PARAM_SET_UBO(¶m, 0); 901 CH_PARAM_SET_VBO(¶m, 0); 902 903 IPU_WRITE_CH_PARAM(sc, DMA_CHANNEL, ¶m); 904 #ifdef DEBUG 905 ipu_print_channel(¶m); 906 #endif 907 908 /* init DMFC */ 909 IPU_WRITE4(sc, DMFC_IC_CTRL, DMFC_IC_CTRL_DISABLED); 910 /* High resolution DP */ 911 IPU_WRITE4(sc, DMFC_WR_CHAN, DMFC_WR_CHAN_BURST_SIZE_8 | 912 DMFC_WR_CHAN_FIFO_SIZE_128); 913 IPU_WRITE4(sc, DMFC_WR_CHAN_DEF, DMFC_WR_CHAN_DEF_WM_CLR_2C(1) | 914 DMFC_WR_CHAN_DEF_WM_CLR_1C(1) | 915 DMFC_WR_CHAN_DEF_WM_CLR_2(1) | 916 DMFC_WR_CHAN_DEF_WM_CLR_1(7) | 917 DMFC_WR_CHAN_DEF_WM_SET_1(5) | 918 DMFC_WR_CHAN_DEF_WM_EN_1); 919 920 IPU_WRITE4(sc, DMFC_DP_CHAN, 921 DMFC_DP_CHAN_BURST_SIZE_5F(DMFC_DP_CHAN_BURST_SIZE_8) | 922 DMFC_DP_CHAN_FIFO_SIZE_5F(DMFC_DP_CHAN_FIFO_SIZE_128) | 923 DMFC_DP_CHAN_ST_ADDR_SIZE_5F(6) /* segment 6 */ | 924 DMFC_DP_CHAN_BURST_SIZE_5B(DMFC_DP_CHAN_BURST_SIZE_8) | 925 DMFC_DP_CHAN_FIFO_SIZE_5B(DMFC_DP_CHAN_FIFO_SIZE_256) | 926 DMFC_DP_CHAN_ST_ADDR_SIZE_5B(2) /* segment 2 */); 927 928 IPU_WRITE4(sc, DMFC_DP_CHAN_DEF, DMFC_DP_CHAN_DEF_WM_CLR_6F(1) | 929 DMFC_DP_CHAN_DEF_WM_CLR_6B(1) | 930 DMFC_DP_CHAN_DEF_WM_CLR_5F(7) | 931 DMFC_DP_CHAN_DEF_WM_SET_5F(5) | 932 DMFC_DP_CHAN_DEF_WM_EN_5F | 933 DMFC_DP_CHAN_DEF_WM_CLR_5B(7) | 934 DMFC_DP_CHAN_DEF_WM_SET_5B(5) | 935 DMFC_DP_CHAN_DEF_WM_EN_5B); 936 937 reg = IPU_READ4(sc, DMFC_GENERAL_1); 938 reg &= ~(DMFC_GENERAL_1_WAIT4EOT_5B); 939 IPU_WRITE4(sc, DMFC_GENERAL_1, reg); 940 941 /* XXX: set priority? */ 942 943 /* Set single buffer mode */ 944 if (DMA_CHANNEL < 32) { 945 db_mode_sel = IPU_CH_DB_MODE_SEL_0; 946 cur_buf = IPU_CUR_BUF_0; 947 } else { 948 db_mode_sel = IPU_CH_DB_MODE_SEL_1; 949 cur_buf = IPU_CUR_BUF_1; 950 } 951 952 reg = IPU_READ4(sc, db_mode_sel); 953 reg |= (1UL << (DMA_CHANNEL & 0x1f)); 954 IPU_WRITE4(sc, db_mode_sel, reg); 955 956 IPU_WRITE4(sc, cur_buf, (1UL << (DMA_CHANNEL & 0x1f))); 957 } 958 959 static int 960 ipu_init(struct ipu_softc *sc) 961 { 962 uint32_t reg, off; 963 int i, err; 964 size_t dma_size; 965 966 IPU_WRITE4(sc, IPU_CONF, DI_PORT ? IPU_CONF_DI1_EN : IPU_CONF_DI0_EN); 967 968 IPU_WRITE4(sc, IPU_MEM_RST, IPU_MEM_RST_ALL); 969 i = 1000; 970 while (i-- > 0) { 971 if (!(IPU_READ4(sc, IPU_MEM_RST) & IPU_MEM_RST_START)) 972 break; 973 DELAY(1); 974 } 975 976 if (i <= 0) { 977 err = ETIMEDOUT; 978 device_printf(sc->sc_dev, "timeout while resetting memory\n"); 979 goto fail; 980 } 981 982 ipu_dc_reset_map(sc, 0); 983 ipu_dc_setup_map(sc, 0, 0, 7, 0xff); 984 ipu_dc_setup_map(sc, 0, 1, 15, 0xff); 985 ipu_dc_setup_map(sc, 0, 2, 23, 0xff); 986 987 dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8)); 988 989 /* 990 * Now allocate framebuffer memory 991 */ 992 err = bus_dma_tag_create( 993 bus_get_dma_tag(sc->sc_dev), 994 4, 0, /* alignment, boundary */ 995 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 996 BUS_SPACE_MAXADDR, /* highaddr */ 997 NULL, NULL, /* filter, filterarg */ 998 dma_size, 1, /* maxsize, nsegments */ 999 dma_size, 0, /* maxsegsize, flags */ 1000 NULL, NULL, /* lockfunc, lockarg */ 1001 &sc->sc_dma_tag); 1002 if (err) 1003 goto fail; 1004 1005 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 1006 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_dma_map); 1007 1008 if (err) { 1009 device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 1010 goto fail; 1011 } 1012 1013 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 1014 dma_size, ipu_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 1015 1016 if (err) { 1017 device_printf(sc->sc_dev, "cannot load DMA map\n"); 1018 goto fail; 1019 } 1020 1021 /* Calculate actual FB Size */ 1022 sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8; 1023 1024 ipu_dc_init(sc, DI_PORT); 1025 reg = IPU_READ4(sc, IPU_CONF); 1026 reg |= IPU_CONF_DMFC_EN | IPU_CONF_DC_EN | IPU_CONF_DP_EN; 1027 IPU_WRITE4(sc, IPU_CONF, reg); 1028 1029 ipu_config_timing(sc, DI_PORT); 1030 ipu_init_buffer(sc); 1031 ipu_di_enable(sc, DI_PORT); 1032 1033 /* Enable DMA channel */ 1034 off = (DMA_CHANNEL > 31) ? IPU_IDMAC_CH_EN_2 : IPU_IDMAC_CH_EN_1; 1035 reg = IPU_READ4(sc, off); 1036 reg |= (1 << (DMA_CHANNEL & 0x1f)); 1037 IPU_WRITE4(sc, off, reg); 1038 1039 ipu_dc_enable(sc); 1040 1041 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 1042 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 1043 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 1044 sc->sc_fb_info.fb_size = sc->sc_fb_size; 1045 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = MODE_BPP; 1046 sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8; 1047 sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay; 1048 sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay; 1049 1050 device_t fbd = device_add_child(sc->sc_dev, "fbd", 1051 device_get_unit(sc->sc_dev)); 1052 if (fbd == NULL) { 1053 device_printf(sc->sc_dev, "Failed to add fbd child\n"); 1054 goto fail; 1055 } 1056 if (device_probe_and_attach(fbd) != 0) { 1057 device_printf(sc->sc_dev, "Failed to attach fbd device\n"); 1058 goto fail; 1059 } 1060 1061 return (0); 1062 fail: 1063 1064 return (err); 1065 } 1066 1067 static int 1068 ipu_mode_is_valid(const struct videomode *mode) 1069 { 1070 if ((mode->dot_clock < 13500) || (mode->dot_clock > 216000)) 1071 return (0); 1072 1073 return (1); 1074 } 1075 1076 static const struct videomode * 1077 ipu_pick_mode(struct edid_info *ei) 1078 { 1079 const struct videomode *videomode; 1080 const struct videomode *m; 1081 int n; 1082 1083 videomode = NULL; 1084 1085 /* 1086 * Pick a mode. 1087 */ 1088 if (ei->edid_preferred_mode != NULL) { 1089 if (ipu_mode_is_valid(ei->edid_preferred_mode)) 1090 videomode = ei->edid_preferred_mode; 1091 } 1092 1093 if (videomode == NULL) { 1094 m = ei->edid_modes; 1095 1096 sort_modes(ei->edid_modes, 1097 &ei->edid_preferred_mode, 1098 ei->edid_nmodes); 1099 for (n = 0; n < ei->edid_nmodes; n++) 1100 if (ipu_mode_is_valid(&m[n])) { 1101 videomode = &m[n]; 1102 break; 1103 } 1104 } 1105 1106 return videomode; 1107 } 1108 1109 static void 1110 ipu_hdmi_event(void *arg, device_t hdmi_dev) 1111 { 1112 struct ipu_softc *sc; 1113 uint8_t *edid; 1114 uint32_t edid_len; 1115 struct edid_info ei; 1116 const struct videomode *videomode; 1117 1118 sc = arg; 1119 1120 edid = NULL; 1121 edid_len = 0; 1122 if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 1123 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 1124 } 1125 1126 videomode = NULL; 1127 1128 if ( edid && (edid_parse(edid, &ei) == 0)) { 1129 if (bootverbose) 1130 edid_print(&ei); 1131 videomode = ipu_pick_mode(&ei); 1132 } else 1133 device_printf(sc->sc_dev, "failed to parse EDID\n"); 1134 1135 /* Use standard VGA as fallback */ 1136 if (videomode == NULL) 1137 videomode = pick_mode_by_ref(640, 480, 60); 1138 1139 if (videomode == NULL) { 1140 device_printf(sc->sc_dev, "failed to find usable videomode\n"); 1141 return; 1142 } 1143 1144 sc->sc_mode = videomode; 1145 1146 if (bootverbose) 1147 device_printf(sc->sc_dev, "detected videomode: %dx%d\n", 1148 videomode->hdisplay, videomode->vdisplay); 1149 1150 ipu_init(sc); 1151 1152 HDMI_SET_VIDEOMODE(hdmi_dev, sc->sc_mode); 1153 } 1154 1155 static int 1156 ipu_probe(device_t dev) 1157 { 1158 1159 if (have_ipu) 1160 return (ENXIO); 1161 1162 if (!ofw_bus_status_okay(dev)) 1163 return (ENXIO); 1164 1165 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ipu")) 1166 return (ENXIO); 1167 1168 device_set_desc(dev, "Freescale IPU"); 1169 1170 return (BUS_PROBE_DEFAULT); 1171 } 1172 1173 static int 1174 ipu_attach(device_t dev) 1175 { 1176 struct ipu_softc *sc; 1177 1178 if (have_ipu) 1179 return (ENXIO); 1180 1181 sc = device_get_softc(dev); 1182 sc->sc_dev = dev; 1183 1184 sc->sc_mem_rid = 0; 1185 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1186 &sc->sc_mem_rid, RF_ACTIVE); 1187 if (!sc->sc_mem_res) { 1188 device_printf(dev, "cannot allocate memory window\n"); 1189 return (ENXIO); 1190 } 1191 1192 sc->sc_irq_rid = 0; 1193 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1194 &sc->sc_irq_rid, RF_ACTIVE); 1195 if (!sc->sc_irq_res) { 1196 bus_release_resource(dev, SYS_RES_MEMORY, 1197 sc->sc_mem_rid, sc->sc_mem_res); 1198 device_printf(dev, "cannot allocate interrupt\n"); 1199 return (ENXIO); 1200 } 1201 1202 /* Enable IPU1 */ 1203 if (imx_ccm_pll_video_enable() != 0) { 1204 bus_release_resource(dev, SYS_RES_MEMORY, 1205 sc->sc_mem_rid, sc->sc_mem_res); 1206 bus_release_resource(dev, SYS_RES_IRQ, 1207 sc->sc_irq_rid, sc->sc_irq_res); 1208 device_printf(dev, "failed to set up video PLL\n"); 1209 return (ENXIO); 1210 } 1211 1212 imx_ccm_ipu_enable(1); 1213 1214 if (src_reset_ipu() != 0) { 1215 bus_release_resource(dev, SYS_RES_MEMORY, 1216 sc->sc_mem_rid, sc->sc_mem_res); 1217 bus_release_resource(dev, SYS_RES_IRQ, 1218 sc->sc_irq_rid, sc->sc_irq_res); 1219 device_printf(dev, "failed to reset IPU\n"); 1220 return (ENXIO); 1221 } 1222 1223 IPU_LOCK_INIT(sc); 1224 1225 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1226 ipu_hdmi_event, sc, 0); 1227 1228 have_ipu = 1; 1229 1230 return (0); 1231 } 1232 1233 static int 1234 ipu_detach(device_t dev) 1235 { 1236 /* Do not let unload driver */ 1237 return (EBUSY); 1238 } 1239 1240 static struct fb_info * 1241 ipu_fb_getinfo(device_t dev) 1242 { 1243 struct ipu_softc *sc; 1244 1245 sc = device_get_softc(dev); 1246 1247 return (&sc->sc_fb_info); 1248 } 1249 1250 static device_method_t ipu_methods[] = { 1251 DEVMETHOD(device_probe, ipu_probe), 1252 DEVMETHOD(device_attach, ipu_attach), 1253 DEVMETHOD(device_detach, ipu_detach), 1254 1255 /* Framebuffer service methods */ 1256 DEVMETHOD(fb_getinfo, ipu_fb_getinfo), 1257 1258 DEVMETHOD_END 1259 }; 1260 1261 static driver_t ipu_driver = { 1262 "fb", 1263 ipu_methods, 1264 sizeof(struct ipu_softc), 1265 }; 1266 1267 static devclass_t ipu_devclass; 1268 1269 DRIVER_MODULE(ipu, simplebus, ipu_driver, ipu_devclass, 0, 0); 1270 MODULE_VERSION(ipu, 1); 1271 MODULE_DEPEND(ipu, simplebus, 1, 1, 1);
Cache object: 6369e4b903b5c3274681d885edd20a41
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