The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/imx/imx6_machdep.c

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    1 /*-
    2  * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include "opt_platform.h"
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD: releng/11.0/sys/arm/freescale/imx/imx6_machdep.c 298854 2016-04-30 17:27:33Z andrew $");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/reboot.h>
   36 #include <sys/devmap.h>
   37 
   38 #include <vm/vm.h>
   39 
   40 #include <machine/bus.h>
   41 #include <machine/intr.h>
   42 #include <machine/machdep.h>
   43 #include <machine/platformvar.h>
   44 
   45 #include <arm/arm/mpcore_timervar.h>
   46 #include <arm/freescale/imx/imx6_anatopreg.h>
   47 #include <arm/freescale/imx/imx6_anatopvar.h>
   48 #include <arm/freescale/imx/imx_machdep.h>
   49 
   50 #include <dev/fdt/fdt_common.h>
   51 #include <dev/ofw/openfirm.h>
   52 
   53 #include "platform_if.h"
   54 
   55 struct fdt_fixup_entry fdt_fixup_table[] = {
   56         { NULL, NULL }
   57 };
   58 
   59 static uint32_t gpio1_node;
   60 
   61 #ifndef INTRNG
   62 /*
   63  * Work around the linux workaround for imx6 erratum 006687, in which some
   64  * ethernet interrupts don't go to the GPC and thus won't wake the system from
   65  * Wait mode. We don't use Wait mode (which halts the GIC, leaving only GPC
   66  * interrupts able to wake the system), so we don't experience the bug at all.
   67  * The linux workaround is to reconfigure GPIO1_6 as the ENET interrupt by
   68  * writing magic values to an undocumented IOMUX register, then letting the gpio
   69  * interrupt driver notify the ethernet driver.  We'll be able to do all that
   70  * (even though we don't need to) once the INTRNG project is committed and the
   71  * imx_gpio driver becomes an interrupt driver.  Until then, this crazy little
   72  * workaround watches for requests to map an interrupt 6 with the interrupt
   73  * controller node referring to gpio1, and it substitutes the proper ffec
   74  * interrupt number.
   75  */
   76 static int
   77 imx6_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
   78     int *trig, int *pol)
   79 {
   80 
   81         if (fdt32_to_cpu(intr[0]) == 6 && 
   82             OF_node_from_xref(iparent) == gpio1_node) {
   83                 *interrupt = 150;
   84                 *trig = INTR_TRIGGER_CONFORM;
   85                 *pol  = INTR_POLARITY_CONFORM;
   86                 return (0);
   87         }
   88         return (gic_decode_fdt(iparent, intr, interrupt, trig, pol));
   89 }
   90 
   91 fdt_pic_decode_t fdt_pic_table[] = {
   92         &imx6_decode_fdt,
   93         NULL
   94 };
   95 #endif
   96 
   97 /*
   98  * Fix FDT data related to interrupts.
   99  *
  100  * Driven by the needs of linux and its drivers (as always), the published FDT
  101  * data for imx6 now sets the interrupt parent for most devices to the GPC
  102  * interrupt controller, which is for use when the chip is in deep-sleep mode.
  103  * We don't support deep sleep or have a GPC-PIC driver; we need all interrupts
  104  * to be handled by the GIC.
  105  *
  106  * Luckily, the change to the FDT data was to assign the GPC as the interrupt
  107  * parent for the soc node and letting that get inherited by all other devices
  108  * (except a few that directly name GIC as their interrupt parent).  So we can
  109  * set the world right by just changing the interrupt-parent property of the soc
  110  * node to refer to GIC instead of GPC.  This will get us by until we write our
  111  * own GPC driver (or until linux changes its mind and the FDT data again).
  112  *
  113  * We validate that we have data that looks like we expect before changing it:
  114  *  - SOC node exists and has GPC as its interrupt parent.
  115  *  - GPC node exists and has GIC as its interrupt parent.
  116  *  - GIC node exists and is its own interrupt parent.
  117  *
  118  * This applies to all models of imx6.  Luckily all of them have the devices
  119  * involved at the same addresses on the same busses, so we don't need any
  120  * per-soc logic.  We handle this at platform attach time rather than via the
  121  * fdt_fixup_table, because the latter requires matching on the FDT "model"
  122  * property, and this applies to all boards including those not yet invented.
  123  */
  124 static void
  125 fix_fdt_interrupt_data(void)
  126 {
  127         phandle_t gicipar, gicnode, gicxref;
  128         phandle_t gpcipar, gpcnode, gpcxref;
  129         phandle_t socipar, socnode;
  130         int result;
  131 
  132         socnode = OF_finddevice("/soc");
  133         if (socnode == -1)
  134             return;
  135         result = OF_getencprop(socnode, "interrupt-parent", &socipar,
  136             sizeof(socipar));
  137         if (result <= 0)
  138                 return;
  139 
  140         gicnode = OF_finddevice("/soc/interrupt-controller@00a01000");
  141         if (gicnode == -1)
  142                 return;
  143         result = OF_getencprop(gicnode, "interrupt-parent", &gicipar,
  144             sizeof(gicipar));
  145         if (result <= 0)
  146                 return;
  147         gicxref = OF_xref_from_node(gicnode);
  148 
  149         gpcnode = OF_finddevice("/soc/aips-bus@02000000/gpc@020dc000");
  150         if (gpcnode == -1)
  151                 return;
  152         result = OF_getencprop(gpcnode, "interrupt-parent", &gpcipar,
  153             sizeof(gpcipar));
  154         if (result <= 0)
  155                 return;
  156         gpcxref = OF_xref_from_node(gpcnode);
  157 
  158         if (socipar != gpcxref || gpcipar != gicxref || gicipar != gicxref)
  159                 return;
  160 
  161         gicxref = cpu_to_fdt32(gicxref);
  162         OF_setprop(socnode, "interrupt-parent", &gicxref, sizeof(gicxref));
  163 }
  164 
  165 static vm_offset_t
  166 imx6_lastaddr(platform_t plat)
  167 {
  168 
  169         return (devmap_lastaddr());
  170 }
  171 
  172 static int
  173 imx6_attach(platform_t plat)
  174 {
  175 
  176         /* Fix soc interrupt-parent property. */
  177         fix_fdt_interrupt_data();
  178 
  179         /* Inform the MPCore timer driver that its clock is variable. */
  180         arm_tmr_change_frequency(ARM_TMR_FREQUENCY_VARIES);
  181 
  182         return (0);
  183 }
  184 
  185 static void
  186 imx6_late_init(platform_t plat)
  187 {
  188         const uint32_t IMX6_WDOG_SR_PHYS = 0x020bc004;
  189 
  190         imx_wdog_init_last_reset(IMX6_WDOG_SR_PHYS);
  191 
  192         /* Cache the gpio1 node handle for imx6_decode_fdt() workaround code. */
  193         gpio1_node = OF_node_from_xref(
  194             OF_finddevice("/soc/aips-bus@02000000/gpio@0209c000"));
  195 }
  196 
  197 /*
  198  * Set up static device mappings.
  199  *
  200  * This attempts to cover the most-used devices with 1MB section mappings, which
  201  * is good for performance (uses fewer TLB entries for device access).
  202  *
  203  * ARMMP covers the interrupt controller, MPCore timers, global timer, and the
  204  * L2 cache controller.  Most of the 1MB range is unused reserved space.
  205  *
  206  * AIPS1/AIPS2 cover most of the on-chip devices such as uart, spi, i2c, etc.
  207  *
  208  * Notably not mapped right now are HDMI, GPU, and other devices below ARMMP in
  209  * the memory map.  When we get support for graphics it might make sense to
  210  * static map some of that area.  Be careful with other things in that area such
  211  * as OCRAM that probably shouldn't be mapped as VM_MEMATTR_DEVICE memory.
  212  */
  213 static int
  214 imx6_devmap_init(platform_t plat)
  215 {
  216         const uint32_t IMX6_ARMMP_PHYS = 0x00a00000;
  217         const uint32_t IMX6_ARMMP_SIZE = 0x00100000;
  218         const uint32_t IMX6_AIPS1_PHYS = 0x02000000;
  219         const uint32_t IMX6_AIPS1_SIZE = 0x00100000;
  220         const uint32_t IMX6_AIPS2_PHYS = 0x02100000;
  221         const uint32_t IMX6_AIPS2_SIZE = 0x00100000;
  222 
  223         devmap_add_entry(IMX6_ARMMP_PHYS, IMX6_ARMMP_SIZE);
  224         devmap_add_entry(IMX6_AIPS1_PHYS, IMX6_AIPS1_SIZE);
  225         devmap_add_entry(IMX6_AIPS2_PHYS, IMX6_AIPS2_SIZE);
  226 
  227         return (0);
  228 }
  229 
  230 void
  231 cpu_reset(void)
  232 {
  233         const uint32_t IMX6_WDOG_CR_PHYS = 0x020bc000;
  234 
  235         imx_wdog_cpu_reset(IMX6_WDOG_CR_PHYS);
  236 }
  237 
  238 /*
  239  * Determine what flavor of imx6 we're running on.
  240  *
  241  * This code is based on the way u-boot does it.  Information found on the web
  242  * indicates that Freescale themselves were the original source of this logic,
  243  * including the strange check for number of CPUs in the SCU configuration
  244  * register, which is apparently needed on some revisions of the SOLO.
  245  *
  246  * According to the documentation, there is such a thing as an i.MX6 Dual
  247  * (non-lite flavor).  However, Freescale doesn't seem to have assigned it a
  248  * number or provided any logic to handle it in their detection code.
  249  *
  250  * Note that the ANALOG_DIGPROG and SCU configuration registers are not
  251  * documented in the chip reference manual.  (SCU configuration is mentioned,
  252  * but not mapped out in detail.)  I think the bottom two bits of the scu config
  253  * register may be ncpu-1.
  254  *
  255  * This hasn't been tested yet on a dual[-lite].
  256  *
  257  * On a solo:
  258  *      digprog    = 0x00610001
  259  *      hwsoc      = 0x00000062
  260  *      scu config = 0x00000500
  261  * On a quad:
  262  *      digprog    = 0x00630002
  263  *      hwsoc      = 0x00000063
  264  *      scu config = 0x00005503
  265  */
  266 u_int imx_soc_type()
  267 {
  268         uint32_t digprog, hwsoc;
  269         uint32_t *pcr;
  270         static u_int soctype;
  271         const vm_offset_t SCU_CONFIG_PHYSADDR = 0x00a00004;
  272 #define HWSOC_MX6SL     0x60
  273 #define HWSOC_MX6DL     0x61
  274 #define HWSOC_MX6SOLO   0x62
  275 #define HWSOC_MX6Q      0x63
  276 
  277         if (soctype != 0)
  278                 return (soctype);
  279 
  280         digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG_SL);
  281         hwsoc = (digprog >> IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT) & 
  282             IMX6_ANALOG_DIGPROG_SOCTYPE_MASK;
  283 
  284         if (hwsoc != HWSOC_MX6SL) {
  285                 digprog = imx6_anatop_read_4(IMX6_ANALOG_DIGPROG);
  286                 hwsoc = (digprog & IMX6_ANALOG_DIGPROG_SOCTYPE_MASK) >>
  287                     IMX6_ANALOG_DIGPROG_SOCTYPE_SHIFT;
  288                 /*printf("digprog = 0x%08x\n", digprog);*/
  289                 if (hwsoc == HWSOC_MX6DL) {
  290                         pcr = devmap_ptov(SCU_CONFIG_PHYSADDR, 4);
  291                         if (pcr != NULL) {
  292                                 /*printf("scu config = 0x%08x\n", *pcr);*/
  293                                 if ((*pcr & 0x03) == 0) {
  294                                         hwsoc = HWSOC_MX6SOLO;
  295                                 }
  296                         }
  297                 }
  298         }
  299         /* printf("hwsoc 0x%08x\n", hwsoc); */
  300 
  301         switch (hwsoc) {
  302         case HWSOC_MX6SL:
  303                 soctype = IMXSOC_6SL;
  304                 break;
  305         case HWSOC_MX6SOLO:
  306                 soctype = IMXSOC_6S;
  307                 break;
  308         case HWSOC_MX6DL:
  309                 soctype = IMXSOC_6DL;
  310                 break;
  311         case HWSOC_MX6Q :
  312                 soctype = IMXSOC_6Q;
  313                 break;
  314         default:
  315                 printf("imx_soc_type: Don't understand hwsoc 0x%02x, "
  316                     "digprog 0x%08x; assuming IMXSOC_6Q\n", hwsoc, digprog);
  317                 soctype = IMXSOC_6Q;
  318                 break;
  319         }
  320 
  321         return (soctype);
  322 }
  323 
  324 /*
  325  * Early putc routine for EARLY_PRINTF support.  To use, add to kernel config:
  326  *   option SOCDEV_PA=0x02000000
  327  *   option SOCDEV_VA=0x02000000
  328  *   option EARLY_PRINTF
  329  * Resist the temptation to change the #if 0 to #ifdef EARLY_PRINTF here. It
  330  * makes sense now, but if multiple SOCs do that it will make early_putc another
  331  * duplicate symbol to be eliminated on the path to a generic kernel.
  332  */
  333 #if 0 
  334 static void 
  335 imx6_early_putc(int c)
  336 {
  337         volatile uint32_t * UART_STAT_REG = (uint32_t *)0x02020098;
  338         volatile uint32_t * UART_TX_REG   = (uint32_t *)0x02020040;
  339         const uint32_t      UART_TXRDY    = (1 << 3);
  340 
  341         while ((*UART_STAT_REG & UART_TXRDY) == 0)
  342                 continue;
  343         *UART_TX_REG = c;
  344 }
  345 early_putc_t *early_putc = imx6_early_putc;
  346 #endif
  347 
  348 static platform_method_t imx6_methods[] = {
  349         PLATFORMMETHOD(platform_attach,         imx6_attach),
  350         PLATFORMMETHOD(platform_lastaddr,       imx6_lastaddr),
  351         PLATFORMMETHOD(platform_devmap_init,    imx6_devmap_init),
  352         PLATFORMMETHOD(platform_late_init,      imx6_late_init),
  353 
  354         PLATFORMMETHOD_END,
  355 };
  356 
  357 FDT_PLATFORM_DEF2(imx6, imx6s, "i.MX6 Solo", 0, "fsl,imx6s", 0);
  358 FDT_PLATFORM_DEF2(imx6, imx6d, "i.MX6 Dual", 0, "fsl,imx6d", 0);
  359 FDT_PLATFORM_DEF2(imx6, imx6q, "i.MX6 Quad", 0, "fsl,imx6q", 0);

Cache object: c619027e509ac94a0b3a7c46a4f6bf0d


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