The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/imx/imx6_sdma.c

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    1 /*-
    2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * i.MX6 Smart Direct Memory Access Controller (sDMA)
   29  * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual,
   30  * Rev. 1, 04/2013
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/11.0/sys/arm/freescale/imx/imx6_sdma.c 297793 2016-04-10 23:07:00Z pfg $");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/kernel.h>
   40 #include <sys/module.h>
   41 #include <sys/malloc.h>
   42 #include <sys/endian.h>
   43 #include <sys/rman.h>
   44 #include <sys/timeet.h>
   45 #include <sys/timetc.h>
   46 #include <sys/firmware.h>
   47 
   48 #include <vm/vm.h>
   49 #include <vm/vm_extern.h>
   50 #include <vm/vm_kern.h>
   51 #include <vm/pmap.h>
   52 
   53 #include <dev/fdt/fdt_common.h>
   54 #include <dev/ofw/openfirm.h>
   55 #include <dev/ofw/ofw_bus.h>
   56 #include <dev/ofw/ofw_bus_subr.h>
   57 
   58 #include <machine/bus.h>
   59 #include <machine/cpu.h>
   60 #include <machine/intr.h>
   61 
   62 #include <arm/freescale/imx/imx6_sdma.h>
   63 
   64 #define MAX_BD  (PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
   65 
   66 #define READ4(_sc, _reg)        \
   67         bus_space_read_4(_sc->bst, _sc->bsh, _reg)
   68 #define WRITE4(_sc, _reg, _val) \
   69         bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
   70 
   71 struct sdma_softc *sdma_sc;
   72 
   73 static struct resource_spec sdma_spec[] = {
   74         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   75         { SYS_RES_IRQ,          0,      RF_ACTIVE },
   76         { -1, 0 }
   77 };
   78 
   79 static void
   80 sdma_intr(void *arg)
   81 {
   82         struct sdma_buffer_descriptor *bd;
   83         struct sdma_channel *channel;
   84         struct sdma_conf *conf;
   85         struct sdma_softc *sc;
   86         int pending;
   87         int i;
   88         int j;
   89 
   90         sc = arg;
   91 
   92         pending = READ4(sc, SDMAARM_INTR);
   93 
   94         /* Ack intr */
   95         WRITE4(sc, SDMAARM_INTR, pending);
   96 
   97         for (i = 0; i < SDMA_N_CHANNELS; i++) {
   98                 if ((pending & (1 << i)) == 0)
   99                         continue;
  100                 channel = &sc->channel[i];
  101                 conf = channel->conf;
  102                 if (!conf)
  103                         continue;
  104                 for (j = 0; j < conf->num_bd; j++) {
  105                         bd = &channel->bd[j];
  106                         bd->mode.status |= BD_DONE;
  107                         if (bd->mode.status & BD_RROR)
  108                                 printf("sDMA error\n");
  109                 }
  110 
  111                 conf->ih(conf->ih_user, 1);
  112 
  113                 WRITE4(sc, SDMAARM_HSTART, (1 << i));
  114         }
  115 }
  116 
  117 static int
  118 sdma_probe(device_t dev)
  119 {
  120 
  121         if (!ofw_bus_status_okay(dev))
  122                 return (ENXIO);
  123 
  124         if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma"))
  125                 return (ENXIO);
  126 
  127         device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller");
  128         return (BUS_PROBE_DEFAULT);
  129 }
  130 
  131 int
  132 sdma_start(int chn)
  133 {
  134         struct sdma_softc *sc;
  135 
  136         sc = sdma_sc;
  137 
  138         WRITE4(sc, SDMAARM_HSTART, (1 << chn));
  139 
  140         return (0);
  141 }
  142 
  143 int
  144 sdma_stop(int chn)
  145 {
  146         struct sdma_softc *sc;
  147 
  148         sc = sdma_sc;
  149 
  150         WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
  151 
  152         return (0);
  153 }
  154 
  155 int
  156 sdma_alloc(void)
  157 {
  158         struct sdma_channel *channel;
  159         struct sdma_softc *sc;
  160         int found;
  161         int chn;
  162         int i;
  163 
  164         sc = sdma_sc;
  165         found = 0;
  166 
  167         /* Channel 0 can't be used */
  168         for (i = 1; i < SDMA_N_CHANNELS; i++) {
  169                 channel = &sc->channel[i];
  170                 if (channel->in_use == 0) {
  171                         channel->in_use = 1;
  172                         found = 1;
  173                         break;
  174                 }
  175         }
  176 
  177         if (!found)
  178                 return (-1);
  179 
  180         chn = i;
  181 
  182         /* Allocate area for buffer descriptors */
  183         channel->bd = (void *)kmem_alloc_contig(kernel_arena,
  184             PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0,
  185             VM_MEMATTR_UNCACHEABLE);
  186 
  187         return (chn);
  188 }
  189 
  190 int
  191 sdma_free(int chn)
  192 {
  193         struct sdma_channel *channel;
  194         struct sdma_softc *sc;
  195 
  196         sc = sdma_sc;
  197 
  198         channel = &sc->channel[chn];
  199         channel->in_use = 0;
  200 
  201         kmem_free(kernel_arena, (vm_offset_t)channel->bd,
  202                         PAGE_SIZE);
  203 
  204         return (0);
  205 }
  206 
  207 static int
  208 sdma_overrides(struct sdma_softc *sc, int chn,
  209                 int evt, int host, int dsp)
  210 {
  211         int reg;
  212 
  213         /* Ignore sDMA requests */
  214         reg = READ4(sc, SDMAARM_EVTOVR);
  215         if (evt)
  216                 reg |= (1 << chn);
  217         else
  218                 reg &= ~(1 << chn);
  219         WRITE4(sc, SDMAARM_EVTOVR, reg);
  220 
  221         /* Ignore enable bit (HE) */
  222         reg = READ4(sc, SDMAARM_HOSTOVR);
  223         if (host)
  224                 reg |= (1 << chn);
  225         else
  226                 reg &= ~(1 << chn);
  227         WRITE4(sc, SDMAARM_HOSTOVR, reg);
  228 
  229         /* Prevent sDMA channel from starting */
  230         reg = READ4(sc, SDMAARM_DSPOVR);
  231         if (!dsp)
  232                 reg |= (1 << chn);
  233         else
  234                 reg &= ~(1 << chn);
  235         WRITE4(sc, SDMAARM_DSPOVR, reg);
  236 
  237         return (0);
  238 }
  239 
  240 int
  241 sdma_configure(int chn, struct sdma_conf *conf)
  242 {
  243         struct sdma_buffer_descriptor *bd0;
  244         struct sdma_buffer_descriptor *bd;
  245         struct sdma_context_data *context;
  246         struct sdma_channel *channel;
  247         struct sdma_softc *sc;
  248 #if 0
  249         int timeout;
  250         int ret;
  251 #endif
  252         int i;
  253 
  254         sc = sdma_sc;
  255 
  256         channel = &sc->channel[chn];
  257         channel->conf = conf;
  258 
  259         /* Ensure operation has stopped */
  260         sdma_stop(chn);
  261 
  262         /* Set priority and enable the channel */
  263         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  264         WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn));
  265 
  266         sdma_overrides(sc, chn, 0, 0, 0);
  267 
  268         if (conf->num_bd > MAX_BD) {
  269                 device_printf(sc->dev, "Error: too much buffer"
  270                                 " descriptors requested\n");
  271                 return (-1);
  272         }
  273 
  274         for (i = 0; i < conf->num_bd; i++) {
  275                 bd = &channel->bd[i];
  276                 bd->mode.command = conf->command;
  277                 bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
  278                 if (i == (conf->num_bd - 1))
  279                         bd->mode.status |= BD_WRAP;
  280                 bd->mode.count = conf->period;
  281                 bd->buffer_addr = conf->saddr + (conf->period * i);
  282                 bd->ext_buffer_addr = 0;
  283         }
  284 
  285         sc->ccb[chn].base_bd_ptr = vtophys(channel->bd);
  286         sc->ccb[chn].current_bd_ptr = vtophys(channel->bd);
  287 
  288         /*
  289          * Load context.
  290          *
  291          * i.MX6 Reference Manual: Appendix A SDMA Scripts
  292          * A.3.1.7.1 (mcu_2_app)
  293          */
  294 
  295         /*
  296          * TODO: allow using other scripts
  297          */
  298         context = sc->context;
  299         memset(context, 0, sizeof(*context));
  300         context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr;
  301 
  302         /*
  303          * Tx FIFO 0 address (r6)
  304          * Event_mask (r1)
  305          * Event2_mask (r0)
  306          * Watermark level (r7)
  307          */
  308 
  309         if (conf->event > 32) {
  310                 context->gReg[0] = (1 << (conf->event % 32));
  311                 context->gReg[1] = 0;
  312         } else {
  313                 context->gReg[0] = 0;
  314                 context->gReg[1] = (1 << conf->event);
  315         }
  316 
  317         context->gReg[6] = conf->daddr;
  318         context->gReg[7] = conf->word_length;
  319 
  320         bd0 = sc->bd0;
  321         bd0->mode.command = C0_SETDM;
  322         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
  323         bd0->mode.count = sizeof(*context) / 4;
  324         bd0->buffer_addr = sc->context_phys;
  325         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn;
  326 
  327         WRITE4(sc, SDMAARM_HSTART, 1);
  328 
  329 #if 0
  330         /* Debug purposes */
  331 
  332         timeout = 1000;
  333         while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
  334                 if (timeout-- <= 0)
  335                         break;
  336                 DELAY(10);
  337         };
  338 
  339         if (!ret) {
  340                 device_printf(sc->dev, "Failed to load context.\n");
  341                 return (-1);
  342         }
  343 
  344         WRITE4(sc, SDMAARM_INTR, ret);
  345 
  346         device_printf(sc->dev, "Context loaded successfully.\n");
  347 #endif
  348 
  349         return (0);
  350 }
  351 
  352 static int
  353 load_firmware(struct sdma_softc *sc)
  354 {
  355         struct sdma_firmware_header *header;
  356         const struct firmware *fp;
  357 
  358         fp = firmware_get("sdma_fw");
  359         if (fp == NULL) {
  360                 device_printf(sc->dev, "Can't get firmware.\n");
  361                 return (-1);
  362         }
  363 
  364         header = (struct sdma_firmware_header *)fp->data;
  365         if (header->magic != FW_HEADER_MAGIC) {
  366                 device_printf(sc->dev, "Can't use firmware.\n");
  367                 return (-1);
  368         }
  369 
  370         sc->fw_header = header;
  371         sc->fw_scripts = (void *)((char *)header +
  372                                 header->script_addrs_start);
  373 
  374         return (0);
  375 }
  376 
  377 static int
  378 boot_firmware(struct sdma_softc *sc)
  379 {
  380         struct sdma_buffer_descriptor *bd0;
  381         uint32_t *ram_code;
  382         int timeout;
  383         int ret;
  384         int chn;
  385         int sz;
  386         int i;
  387 
  388         ram_code = (void *)((char *)sc->fw_header +
  389                         sc->fw_header->ram_code_start);
  390 
  391         /* Make sure SDMA has not started yet */
  392         WRITE4(sc, SDMAARM_MC0PTR, 0);
  393 
  394         sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \
  395             sizeof(struct sdma_context_data);
  396         sc->ccb = (void *)kmem_alloc_contig(kernel_arena,
  397             sz, M_ZERO, 0, ~0, PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
  398         sc->ccb_phys = vtophys(sc->ccb);
  399 
  400         sc->context = (void *)((char *)sc->ccb + \
  401             SDMA_N_CHANNELS * sizeof(struct sdma_channel_control));
  402         sc->context_phys = vtophys(sc->context);
  403 
  404         /* Disable all the channels */
  405         for (i = 0; i < SDMA_N_EVENTS; i++)
  406                 WRITE4(sc, SDMAARM_CHNENBL(i), 0);
  407 
  408         /* All channels have priority 0 */
  409         for (i = 0; i < SDMA_N_CHANNELS; i++)
  410                 WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0);
  411 
  412         /* Channel 0 is used for booting firmware */
  413         chn = 0;
  414 
  415         sc->bd0 = (void *)kmem_alloc_contig(kernel_arena,
  416             PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE, 0,
  417             VM_MEMATTR_UNCACHEABLE);
  418         bd0 = sc->bd0;
  419         sc->ccb[chn].base_bd_ptr = vtophys(bd0);
  420         sc->ccb[chn].current_bd_ptr = vtophys(bd0);
  421 
  422         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  423 
  424         sdma_overrides(sc, chn, 1, 0, 0);
  425 
  426         /* XXX: not sure what is that */
  427         WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050);
  428 
  429         WRITE4(sc, SDMAARM_CONFIG, 0);
  430         WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys);
  431         WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM);
  432         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  433 
  434         bd0->mode.command = C0_SETPM;
  435         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
  436         bd0->mode.count = sc->fw_header->ram_code_size / 2;
  437         bd0->buffer_addr = vtophys(ram_code);
  438         bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr;
  439 
  440         WRITE4(sc, SDMAARM_HSTART, 1);
  441 
  442         timeout = 100;
  443         while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
  444                 if (timeout-- <= 0)
  445                         break;
  446                 DELAY(10);
  447         }
  448 
  449         if (ret == 0) {
  450                 device_printf(sc->dev, "SDMA failed to boot\n");
  451                 return (-1);
  452         }
  453 
  454         WRITE4(sc, SDMAARM_INTR, ret);
  455 
  456 #if 0
  457         device_printf(sc->dev, "SDMA booted successfully.\n");
  458 #endif
  459 
  460         /* Debug is disabled */
  461         WRITE4(sc, SDMAARM_ONCE_ENB, 0);
  462 
  463         return (0);
  464 }
  465 
  466 static int
  467 sdma_attach(device_t dev)
  468 {
  469         struct sdma_softc *sc;
  470         int err;
  471 
  472         sc = device_get_softc(dev);
  473         sc->dev = dev;
  474 
  475         if (bus_alloc_resources(dev, sdma_spec, sc->res)) {
  476                 device_printf(dev, "could not allocate resources\n");
  477                 return (ENXIO);
  478         }
  479 
  480         /* Memory interface */
  481         sc->bst = rman_get_bustag(sc->res[0]);
  482         sc->bsh = rman_get_bushandle(sc->res[0]);
  483 
  484         sdma_sc = sc;
  485 
  486         /* Setup interrupt handler */
  487         err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
  488             NULL, sdma_intr, sc, &sc->ih);
  489         if (err) {
  490                 device_printf(dev, "Unable to alloc interrupt resource.\n");
  491                 return (ENXIO);
  492         }
  493 
  494         if (load_firmware(sc) == -1)
  495                 return (ENXIO);
  496 
  497         if (boot_firmware(sc) == -1)
  498                 return (ENXIO);
  499 
  500         return (0);
  501 };
  502 
  503 static device_method_t sdma_methods[] = {
  504         /* Device interface */
  505         DEVMETHOD(device_probe,         sdma_probe),
  506         DEVMETHOD(device_attach,        sdma_attach),
  507         { 0, 0 }
  508 };
  509 
  510 static driver_t sdma_driver = {
  511         "sdma",
  512         sdma_methods,
  513         sizeof(struct sdma_softc),
  514 };
  515 
  516 static devclass_t sdma_devclass;
  517 
  518 DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0);

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