imx6_sdma.c

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    1 /*-
    2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * i.MX6 Smart Direct Memory Access Controller (sDMA)
   29  * Chapter 41, i.MX 6Dual/6Quad Applications Processor Reference Manual,
   30  * Rev. 1, 04/2013
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD$");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/kernel.h>
   40 #include <sys/module.h>
   41 #include <sys/malloc.h>
   42 #include <sys/endian.h>
   43 #include <sys/rman.h>
   44 #include <sys/timeet.h>
   45 #include <sys/timetc.h>
   46 #include <sys/firmware.h>
   47 
   48 #include <vm/vm.h>
   49 #include <vm/vm_extern.h>
   50 #include <vm/vm_kern.h>
   51 #include <vm/pmap.h>
   52 
   53 #include <dev/ofw/openfirm.h>
   54 #include <dev/ofw/ofw_bus.h>
   55 #include <dev/ofw/ofw_bus_subr.h>
   56 
   57 #include <machine/bus.h>
   58 #include <machine/cpu.h>
   59 #include <machine/intr.h>
   60 
   61 #include <arm/freescale/imx/imx6_sdma.h>
   62 
   63 #define MAX_BD  (PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
   64 
   65 #define READ4(_sc, _reg)        \
   66         bus_space_read_4(_sc->bst, _sc->bsh, _reg)
   67 #define WRITE4(_sc, _reg, _val) \
   68         bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
   69 
   70 struct sdma_softc *sdma_sc;
   71 
   72 static struct resource_spec sdma_spec[] = {
   73         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   74         { SYS_RES_IRQ,          0,      RF_ACTIVE },
   75         { -1, 0 }
   76 };
   77 
   78 static void
   79 sdma_intr(void *arg)
   80 {
   81         struct sdma_buffer_descriptor *bd;
   82         struct sdma_channel *channel;
   83         struct sdma_conf *conf;
   84         struct sdma_softc *sc;
   85         int pending;
   86         int i;
   87         int j;
   88 
   89         sc = arg;
   90 
   91         pending = READ4(sc, SDMAARM_INTR);
   92 
   93         /* Ack intr */
   94         WRITE4(sc, SDMAARM_INTR, pending);
   95 
   96         for (i = 0; i < SDMA_N_CHANNELS; i++) {
   97                 if ((pending & (1 << i)) == 0)
   98                         continue;
   99                 channel = &sc->channel[i];
  100                 conf = channel->conf;
  101                 if (!conf)
  102                         continue;
  103                 for (j = 0; j < conf->num_bd; j++) {
  104                         bd = &channel->bd[j];
  105                         bd->mode.status |= BD_DONE;
  106                         if (bd->mode.status & BD_RROR)
  107                                 printf("sDMA error\n");
  108                 }
  109 
  110                 conf->ih(conf->ih_user, 1);
  111 
  112                 WRITE4(sc, SDMAARM_HSTART, (1 << i));
  113         }
  114 }
  115 
  116 static int
  117 sdma_probe(device_t dev)
  118 {
  119 
  120         if (!ofw_bus_status_okay(dev))
  121                 return (ENXIO);
  122 
  123         if (!ofw_bus_is_compatible(dev, "fsl,imx6q-sdma"))
  124                 return (ENXIO);
  125 
  126         device_set_desc(dev, "i.MX6 Smart Direct Memory Access Controller");
  127         return (BUS_PROBE_DEFAULT);
  128 }
  129 
  130 int
  131 sdma_start(int chn)
  132 {
  133         struct sdma_softc *sc;
  134 
  135         sc = sdma_sc;
  136 
  137         WRITE4(sc, SDMAARM_HSTART, (1 << chn));
  138 
  139         return (0);
  140 }
  141 
  142 int
  143 sdma_stop(int chn)
  144 {
  145         struct sdma_softc *sc;
  146 
  147         sc = sdma_sc;
  148 
  149         WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
  150 
  151         return (0);
  152 }
  153 
  154 int
  155 sdma_alloc(void)
  156 {
  157         struct sdma_channel *channel;
  158         struct sdma_softc *sc;
  159         int found;
  160         int chn;
  161         int i;
  162 
  163         sc = sdma_sc;
  164         found = 0;
  165 
  166         /* Channel 0 can't be used */
  167         for (i = 1; i < SDMA_N_CHANNELS; i++) {
  168                 channel = &sc->channel[i];
  169                 if (channel->in_use == 0) {
  170                         channel->in_use = 1;
  171                         found = 1;
  172                         break;
  173                 }
  174         }
  175 
  176         if (!found)
  177                 return (-1);
  178 
  179         chn = i;
  180 
  181         /* Allocate area for buffer descriptors */
  182         channel->bd = (void *)kmem_alloc_contig(PAGE_SIZE, M_ZERO, 0, ~0,
  183             PAGE_SIZE, 0, VM_MEMATTR_UNCACHEABLE);
  184 
  185         return (chn);
  186 }
  187 
  188 int
  189 sdma_free(int chn)
  190 {
  191         struct sdma_channel *channel;
  192         struct sdma_softc *sc;
  193 
  194         sc = sdma_sc;
  195 
  196         channel = &sc->channel[chn];
  197         channel->in_use = 0;
  198 
  199         kmem_free((vm_offset_t)channel->bd, PAGE_SIZE);
  200 
  201         return (0);
  202 }
  203 
  204 static int
  205 sdma_overrides(struct sdma_softc *sc, int chn,
  206                 int evt, int host, int dsp)
  207 {
  208         int reg;
  209 
  210         /* Ignore sDMA requests */
  211         reg = READ4(sc, SDMAARM_EVTOVR);
  212         if (evt)
  213                 reg |= (1 << chn);
  214         else
  215                 reg &= ~(1 << chn);
  216         WRITE4(sc, SDMAARM_EVTOVR, reg);
  217 
  218         /* Ignore enable bit (HE) */
  219         reg = READ4(sc, SDMAARM_HOSTOVR);
  220         if (host)
  221                 reg |= (1 << chn);
  222         else
  223                 reg &= ~(1 << chn);
  224         WRITE4(sc, SDMAARM_HOSTOVR, reg);
  225 
  226         /* Prevent sDMA channel from starting */
  227         reg = READ4(sc, SDMAARM_DSPOVR);
  228         if (!dsp)
  229                 reg |= (1 << chn);
  230         else
  231                 reg &= ~(1 << chn);
  232         WRITE4(sc, SDMAARM_DSPOVR, reg);
  233 
  234         return (0);
  235 }
  236 
  237 int
  238 sdma_configure(int chn, struct sdma_conf *conf)
  239 {
  240         struct sdma_buffer_descriptor *bd0;
  241         struct sdma_buffer_descriptor *bd;
  242         struct sdma_context_data *context;
  243         struct sdma_channel *channel;
  244         struct sdma_softc *sc;
  245 #if 0
  246         int timeout;
  247         int ret;
  248 #endif
  249         int i;
  250 
  251         sc = sdma_sc;
  252 
  253         channel = &sc->channel[chn];
  254         channel->conf = conf;
  255 
  256         /* Ensure operation has stopped */
  257         sdma_stop(chn);
  258 
  259         /* Set priority and enable the channel */
  260         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  261         WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn));
  262 
  263         sdma_overrides(sc, chn, 0, 0, 0);
  264 
  265         if (conf->num_bd > MAX_BD) {
  266                 device_printf(sc->dev, "Error: too much buffer"
  267                                 " descriptors requested\n");
  268                 return (-1);
  269         }
  270 
  271         for (i = 0; i < conf->num_bd; i++) {
  272                 bd = &channel->bd[i];
  273                 bd->mode.command = conf->command;
  274                 bd->mode.status = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
  275                 if (i == (conf->num_bd - 1))
  276                         bd->mode.status |= BD_WRAP;
  277                 bd->mode.count = conf->period;
  278                 bd->buffer_addr = conf->saddr + (conf->period * i);
  279                 bd->ext_buffer_addr = 0;
  280         }
  281 
  282         sc->ccb[chn].base_bd_ptr = vtophys(channel->bd);
  283         sc->ccb[chn].current_bd_ptr = vtophys(channel->bd);
  284 
  285         /*
  286          * Load context.
  287          *
  288          * i.MX6 Reference Manual: Appendix A SDMA Scripts
  289          * A.3.1.7.1 (mcu_2_app)
  290          */
  291 
  292         /*
  293          * TODO: allow using other scripts
  294          */
  295         context = sc->context;
  296         memset(context, 0, sizeof(*context));
  297         context->channel_state.pc = sc->fw_scripts->mcu_2_app_addr;
  298 
  299         /*
  300          * Tx FIFO 0 address (r6)
  301          * Event_mask (r1)
  302          * Event2_mask (r0)
  303          * Watermark level (r7)
  304          */
  305 
  306         if (conf->event > 32) {
  307                 context->gReg[0] = (1 << (conf->event % 32));
  308                 context->gReg[1] = 0;
  309         } else {
  310                 context->gReg[0] = 0;
  311                 context->gReg[1] = (1 << conf->event);
  312         }
  313 
  314         context->gReg[6] = conf->daddr;
  315         context->gReg[7] = conf->word_length;
  316 
  317         bd0 = sc->bd0;
  318         bd0->mode.command = C0_SETDM;
  319         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
  320         bd0->mode.count = sizeof(*context) / 4;
  321         bd0->buffer_addr = sc->context_phys;
  322         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * chn;
  323 
  324         WRITE4(sc, SDMAARM_HSTART, 1);
  325 
  326 #if 0
  327         /* Debug purposes */
  328 
  329         timeout = 1000;
  330         while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
  331                 if (timeout-- <= 0)
  332                         break;
  333                 DELAY(10);
  334         };
  335 
  336         if (!ret) {
  337                 device_printf(sc->dev, "Failed to load context.\n");
  338                 return (-1);
  339         }
  340 
  341         WRITE4(sc, SDMAARM_INTR, ret);
  342 
  343         device_printf(sc->dev, "Context loaded successfully.\n");
  344 #endif
  345 
  346         return (0);
  347 }
  348 
  349 static int
  350 load_firmware(struct sdma_softc *sc)
  351 {
  352         const struct sdma_firmware_header *header;
  353         const struct firmware *fp;
  354 
  355         fp = firmware_get("sdma_fw");
  356         if (fp == NULL) {
  357                 device_printf(sc->dev, "Can't get firmware.\n");
  358                 return (-1);
  359         }
  360 
  361         header = fp->data;
  362         if (header->magic != FW_HEADER_MAGIC) {
  363                 device_printf(sc->dev, "Can't use firmware.\n");
  364                 return (-1);
  365         }
  366 
  367         sc->fw_header = header;
  368         sc->fw_scripts = (const void *)((const char *)header +
  369                                 header->script_addrs_start);
  370 
  371         return (0);
  372 }
  373 
  374 static int
  375 boot_firmware(struct sdma_softc *sc)
  376 {
  377         struct sdma_buffer_descriptor *bd0;
  378         const uint32_t *ram_code;
  379         int timeout;
  380         int ret;
  381         int chn;
  382         int sz;
  383         int i;
  384 
  385         ram_code = (const void *)((const char *)sc->fw_header +
  386                         sc->fw_header->ram_code_start);
  387 
  388         /* Make sure SDMA has not started yet */
  389         WRITE4(sc, SDMAARM_MC0PTR, 0);
  390 
  391         sz = SDMA_N_CHANNELS * sizeof(struct sdma_channel_control) + \
  392             sizeof(struct sdma_context_data);
  393         sc->ccb = (void *)kmem_alloc_contig(sz, M_ZERO, 0, ~0, PAGE_SIZE, 0,
  394             VM_MEMATTR_UNCACHEABLE);
  395         sc->ccb_phys = vtophys(sc->ccb);
  396 
  397         sc->context = (void *)((char *)sc->ccb + \
  398             SDMA_N_CHANNELS * sizeof(struct sdma_channel_control));
  399         sc->context_phys = vtophys(sc->context);
  400 
  401         /* Disable all the channels */
  402         for (i = 0; i < SDMA_N_EVENTS; i++)
  403                 WRITE4(sc, SDMAARM_CHNENBL(i), 0);
  404 
  405         /* All channels have priority 0 */
  406         for (i = 0; i < SDMA_N_CHANNELS; i++)
  407                 WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0);
  408 
  409         /* Channel 0 is used for booting firmware */
  410         chn = 0;
  411 
  412         sc->bd0 = (void *)kmem_alloc_contig(PAGE_SIZE, M_ZERO, 0, ~0, PAGE_SIZE,
  413             0, VM_MEMATTR_UNCACHEABLE);
  414         bd0 = sc->bd0;
  415         sc->ccb[chn].base_bd_ptr = vtophys(bd0);
  416         sc->ccb[chn].current_bd_ptr = vtophys(bd0);
  417 
  418         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  419 
  420         sdma_overrides(sc, chn, 1, 0, 0);
  421 
  422         /* XXX: not sure what is that */
  423         WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050);
  424 
  425         WRITE4(sc, SDMAARM_CONFIG, 0);
  426         WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys);
  427         WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM);
  428         WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
  429 
  430         bd0->mode.command = C0_SETPM;
  431         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
  432         bd0->mode.count = sc->fw_header->ram_code_size / 2;
  433         bd0->buffer_addr = vtophys(ram_code);
  434         bd0->ext_buffer_addr = sc->fw_scripts->ram_code_start_addr;
  435 
  436         WRITE4(sc, SDMAARM_HSTART, 1);
  437 
  438         timeout = 100;
  439         while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {
  440                 if (timeout-- <= 0)
  441                         break;
  442                 DELAY(10);
  443         }
  444 
  445         if (ret == 0) {
  446                 device_printf(sc->dev, "SDMA failed to boot\n");
  447                 return (-1);
  448         }
  449 
  450         WRITE4(sc, SDMAARM_INTR, ret);
  451 
  452 #if 0
  453         device_printf(sc->dev, "SDMA booted successfully.\n");
  454 #endif
  455 
  456         /* Debug is disabled */
  457         WRITE4(sc, SDMAARM_ONCE_ENB, 0);
  458 
  459         return (0);
  460 }
  461 
  462 static int
  463 sdma_attach(device_t dev)
  464 {
  465         struct sdma_softc *sc;
  466         int err;
  467 
  468         sc = device_get_softc(dev);
  469         sc->dev = dev;
  470 
  471         if (bus_alloc_resources(dev, sdma_spec, sc->res)) {
  472                 device_printf(dev, "could not allocate resources\n");
  473                 return (ENXIO);
  474         }
  475 
  476         /* Memory interface */
  477         sc->bst = rman_get_bustag(sc->res[0]);
  478         sc->bsh = rman_get_bushandle(sc->res[0]);
  479 
  480         sdma_sc = sc;
  481 
  482         /* Setup interrupt handler */
  483         err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
  484             NULL, sdma_intr, sc, &sc->ih);
  485         if (err) {
  486                 device_printf(dev, "Unable to alloc interrupt resource.\n");
  487                 return (ENXIO);
  488         }
  489 
  490         if (load_firmware(sc) == -1)
  491                 return (ENXIO);
  492 
  493         if (boot_firmware(sc) == -1)
  494                 return (ENXIO);
  495 
  496         return (0);
  497 };
  498 
  499 static device_method_t sdma_methods[] = {
  500         /* Device interface */
  501         DEVMETHOD(device_probe,         sdma_probe),
  502         DEVMETHOD(device_attach,        sdma_attach),
  503         { 0, 0 }
  504 };
  505 
  506 static driver_t sdma_driver = {
  507         "sdma",
  508         sdma_methods,
  509         sizeof(struct sdma_softc),
  510 };
  511 
  512 static devclass_t sdma_devclass;
  513 
  514 EARLY_DRIVER_MODULE(sdma, simplebus, sdma_driver, sdma_devclass, 0, 0,
  515     BUS_PASS_RESOURCE);
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FreeBSD/Linux Kernel Cross Reference sys/arm/freescale/imx/imx6_sdma.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/imx/imx6_sdma.c
