imx6_sdma.h

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    1 /*-
    2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD$
   27  */
   28 
   29 #define SDMAARM_MC0PTR          0x00    /* ARM platform Channel 0 Pointer */
   30 #define SDMAARM_INTR            0x04    /* Channel Interrupts */
   31 #define SDMAARM_STOP_STAT       0x08    /* Channel Stop/Channel Status */
   32 #define SDMAARM_HSTART          0x0C    /* Channel Start */
   33 #define SDMAARM_EVTOVR          0x10    /* Channel Event Override */
   34 #define SDMAARM_DSPOVR          0x14    /* Channel BP Override */
   35 #define SDMAARM_HOSTOVR         0x18    /* Channel ARM platform Override */
   36 #define SDMAARM_EVTPEND         0x1C    /* Channel Event Pending */
   37 #define SDMAARM_RESET           0x24    /* Reset Register */
   38 #define SDMAARM_EVTERR          0x28    /* DMA Request Error Register */
   39 #define SDMAARM_INTRMASK        0x2C    /* Channel ARM platform Interrupt Mask */
   40 #define SDMAARM_PSW             0x30    /* Schedule Status */
   41 #define SDMAARM_EVTERRDBG       0x34    /* DMA Request Error Register */
   42 #define SDMAARM_CONFIG          0x38    /* Configuration Register */
   43 #define  CONFIG_CSM             0x3
   44 #define SDMAARM_SDMA_LOCK       0x3C    /* SDMA LOCK */
   45 #define SDMAARM_ONCE_ENB        0x40    /* OnCE Enable */
   46 #define SDMAARM_ONCE_DATA       0x44    /* OnCE Data Register */
   47 #define SDMAARM_ONCE_INSTR      0x48    /* OnCE Instruction Register */
   48 #define SDMAARM_ONCE_STAT       0x4C    /* OnCE Status Register */
   49 #define SDMAARM_ONCE_CMD        0x50    /* OnCE Command Register */
   50 #define SDMAARM_ILLINSTADDR     0x58    /* Illegal Instruction Trap Address */
   51 #define SDMAARM_CHN0ADDR        0x5C    /* Channel 0 Boot Address */
   52 #define SDMAARM_EVT_MIRROR      0x60    /* DMA Requests */
   53 #define SDMAARM_EVT_MIRROR2     0x64    /* DMA Requests 2 */
   54 #define SDMAARM_XTRIG_CONF1     0x70    /* Cross-Trigger Events Configuration Register 1 */
   55 #define SDMAARM_XTRIG_CONF2     0x74    /* Cross-Trigger Events Configuration Register 2 */
   56 #define SDMAARM_SDMA_CHNPRI(n)  (0x100 + 0x4 * n)       /* Channel Priority Registers */
   57 #define SDMAARM_CHNENBL(n)      (0x200 + 0x4 * n)       /* Channel Enable RAM */
   58 
   59 /* SDMA Event Mappings */
   60 #define SSI1_RX_1       35
   61 #define SSI1_TX_1       36
   62 #define SSI1_RX_0       37
   63 #define SSI1_TX_0       38
   64 #define SSI2_RX_1       39
   65 #define SSI2_TX_1       40
   66 #define SSI2_RX_0       41
   67 #define SSI2_TX_0       42
   68 #define SSI3_RX_1       43
   69 #define SSI3_TX_1       44
   70 #define SSI3_RX_0       45
   71 #define SSI3_TX_0       46
   72 
   73 #define C0_ADDR         0x01
   74 #define C0_LOAD         0x02
   75 #define C0_DUMP         0x03
   76 #define C0_SETCTX       0x07
   77 #define C0_GETCTX       0x03
   78 #define C0_SETDM        0x01
   79 #define C0_SETPM        0x04
   80 #define C0_GETDM        0x02
   81 #define C0_GETPM        0x08
   82 
   83 #define BD_DONE         0x01
   84 #define BD_WRAP         0x02
   85 #define BD_CONT         0x04
   86 #define BD_INTR         0x08
   87 #define BD_RROR         0x10
   88 #define BD_LAST         0x20
   89 #define BD_EXTD         0x80
   90 
   91 /* sDMA data transfer length */
   92 #define CMD_4BYTES      0
   93 #define CMD_3BYTES      3
   94 #define CMD_2BYTES      2
   95 #define CMD_1BYTES      1
   96 
   97 struct sdma_firmware_header {
   98         uint32_t        magic;
   99         uint32_t        version_major;
  100         uint32_t        version_minor;
  101         uint32_t        script_addrs_start;
  102         uint32_t        num_script_addrs;
  103         uint32_t        ram_code_start;
  104         uint32_t        ram_code_size;
  105 };
  106 
  107 struct sdma_mode_count {
  108         uint16_t count;
  109         uint8_t status;
  110         uint8_t command;
  111 };
  112 
  113 struct sdma_buffer_descriptor {
  114         struct sdma_mode_count  mode;
  115         uint32_t                buffer_addr;
  116         uint32_t                ext_buffer_addr;
  117 } __packed;
  118 
  119 struct sdma_channel_control {
  120         uint32_t        current_bd_ptr;
  121         uint32_t        base_bd_ptr;
  122         uint32_t        unused[2];
  123 } __packed;
  124 
  125 struct sdma_state_registers {
  126         uint32_t        pc     :14;
  127         uint32_t        unused1: 1;
  128         uint32_t        t      : 1;
  129         uint32_t        rpc    :14;
  130         uint32_t        unused0: 1;
  131         uint32_t        sf     : 1;
  132         uint32_t        spc    :14;
  133         uint32_t        unused2: 1;
  134         uint32_t        df     : 1;
  135         uint32_t        epc    :14;
  136         uint32_t        lm     : 2;
  137 } __packed;
  138 
  139 struct sdma_context_data {
  140         struct sdma_state_registers     channel_state;
  141         uint32_t        gReg[8];
  142         uint32_t        mda;
  143         uint32_t        msa;
  144         uint32_t        ms;
  145         uint32_t        md;
  146         uint32_t        pda;
  147         uint32_t        psa;
  148         uint32_t        ps;
  149         uint32_t        pd;
  150         uint32_t        ca;
  151         uint32_t        cs;
  152         uint32_t        dda;
  153         uint32_t        dsa;
  154         uint32_t        ds;
  155         uint32_t        dd;
  156         uint32_t        unused[8];
  157 } __packed;
  158 
  159 /* SDMA firmware script pointers */
  160 struct sdma_script_start_addrs {
  161         int32_t ap_2_ap_addr;
  162         int32_t ap_2_bp_addr;
  163         int32_t ap_2_ap_fixed_addr;
  164         int32_t bp_2_ap_addr;
  165         int32_t loopback_on_dsp_side_addr;
  166         int32_t mcu_interrupt_only_addr;
  167         int32_t firi_2_per_addr;
  168         int32_t firi_2_mcu_addr;
  169         int32_t per_2_firi_addr;
  170         int32_t mcu_2_firi_addr;
  171         int32_t uart_2_per_addr;
  172         int32_t uart_2_mcu_addr;
  173         int32_t per_2_app_addr;
  174         int32_t mcu_2_app_addr;
  175         int32_t per_2_per_addr;
  176         int32_t uartsh_2_per_addr;
  177         int32_t uartsh_2_mcu_addr;
  178         int32_t per_2_shp_addr;
  179         int32_t mcu_2_shp_addr;
  180         int32_t ata_2_mcu_addr;
  181         int32_t mcu_2_ata_addr;
  182         int32_t app_2_per_addr;
  183         int32_t app_2_mcu_addr;
  184         int32_t shp_2_per_addr;
  185         int32_t shp_2_mcu_addr;
  186         int32_t mshc_2_mcu_addr;
  187         int32_t mcu_2_mshc_addr;
  188         int32_t spdif_2_mcu_addr;
  189         int32_t mcu_2_spdif_addr;
  190         int32_t asrc_2_mcu_addr;
  191         int32_t ext_mem_2_ipu_addr;
  192         int32_t descrambler_addr;
  193         int32_t dptc_dvfs_addr;
  194         int32_t utra_addr;
  195         int32_t ram_code_start_addr;
  196         int32_t mcu_2_ssish_addr;
  197         int32_t ssish_2_mcu_addr;
  198         int32_t hdmi_dma_addr;
  199 };
  200 
  201 #define SDMA_N_CHANNELS 32
  202 #define SDMA_N_EVENTS   48
  203 #define FW_HEADER_MAGIC 0x414d4453
  204 
  205 struct sdma_channel {
  206         struct sdma_conf                *conf;
  207         struct sdma_buffer_descriptor   *bd;
  208         uint8_t                         in_use;
  209 };
  210 
  211 struct sdma_softc {
  212         struct resource                 *res[2];
  213         bus_space_tag_t                 bst;
  214         bus_space_handle_t              bsh;
  215         device_t                        dev;
  216         void                            *ih;
  217         struct sdma_channel_control     *ccb;
  218         struct sdma_buffer_descriptor   *bd0;
  219         struct sdma_context_data        *context;
  220         struct sdma_channel             channel[SDMA_N_CHANNELS];
  221         uint32_t                        num_bd;
  222         uint32_t                        ccb_phys;
  223         uint32_t                        context_phys;
  224         const struct sdma_firmware_header       *fw_header;
  225         const struct sdma_script_start_addrs    *fw_scripts;
  226 };
  227 
  228 struct sdma_conf {
  229         bus_addr_t      saddr;
  230         bus_addr_t      daddr;
  231         uint32_t        word_length;
  232         uint32_t        nbits;
  233         uint32_t        command;
  234         uint32_t        num_bd;
  235         uint32_t        event;
  236         uint32_t        period;
  237         uint32_t        (*ih)(void *, int);
  238         void            *ih_user;
  239 };
  240 
  241 int sdma_configure(int, struct sdma_conf *);
  242 int sdma_start(int);
  243 int sdma_stop(int);
  244 int sdma_alloc(void);
  245 int sdma_free(int);

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FreeBSD/Linux Kernel Cross Reference sys/arm/freescale/imx/imx6_sdma.h

FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/imx/imx6_sdma.h